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AsmParser
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[AArch64] Add Tiny Code Model for AArch64
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2018-08-22 11:31:39 +00:00 |
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Disassembler
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[aarch64][mc] Don't lookup symbols when there is no symbol lookup callback
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2018-08-21 15:47:25 +00:00 |
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InstPrinter
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[AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction
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2018-07-06 08:03:12 +00:00 |
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MCTargetDesc
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Find PLT entries for x86, x86_64, and AArch64.
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2018-08-24 15:21:56 +00:00 |
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TargetInfo
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Add backend name to Target to enable runtime info to be fed back into TableGen
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2017-11-15 23:55:44 +00:00 |
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Utils
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[AArch64] Armv8.4-A: TLB support
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2018-07-06 13:00:16 +00:00 |
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AArch64.h
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Revert r331816 and r331820 - [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
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2018-05-09 05:00:17 +00:00 |
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AArch64.td
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[ARM/AArch64] Support FP16 +fp16fml instructions
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2018-08-17 11:29:49 +00:00 |
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AArch64A53Fix835769.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64A57FPLoadBalancing.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64AdvSIMDScalarPass.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64AsmPrinter.cpp
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[COFF] Hoist constant pool handling from X86AsmPrinter into AsmPrinter
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2018-07-25 18:35:31 +00:00 |
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AArch64CallLowering.cpp
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[GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value
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2018-08-02 08:33:31 +00:00 |
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AArch64CallLowering.h
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[GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value
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2018-08-02 08:33:31 +00:00 |
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AArch64CallingConvention.h
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…
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AArch64CallingConvention.td
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AArch64: Implement support for the shadowcallstack attribute.
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2018-04-04 21:55:44 +00:00 |
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AArch64CleanupLocalDynamicTLSPass.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
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AArch64CollectLOH.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64CondBrTuning.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64ConditionOptimizer.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64ConditionalCompares.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64DeadRegisterDefinitionsPass.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64ExpandPseudoInsts.cpp
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[AArch64] Add Tiny Code Model for AArch64
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2018-08-22 11:31:39 +00:00 |
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AArch64FalkorHWPFFix.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64FastISel.cpp
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DAG: Add calling convention argument to calling convention funcs
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2018-07-28 13:25:19 +00:00 |
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AArch64FrameLowering.cpp
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[AArch64] Add Tiny Code Model for AArch64
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2018-08-22 11:31:39 +00:00 |
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AArch64FrameLowering.h
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Remove \brief commands from doxygen comments.
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2018-05-01 15:54:18 +00:00 |
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AArch64GenRegisterBankInfo.def
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[AArch64][RegisterBankInfo] Teach instruction mapping about gpr32 -> fpr16 cross copies
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2017-11-18 04:28:56 +00:00 |
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AArch64ISelDAGToDAG.cpp
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[SDAG] Remove the reliance on MI's allocation strategy for
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2018-08-14 23:30:32 +00:00 |
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AArch64ISelLowering.cpp
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[AArch64] Reject inline asm with FP registers when FP is disabled.
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2018-08-24 19:12:13 +00:00 |
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AArch64ISelLowering.h
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[AArch64] Add Tiny Code Model for AArch64
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2018-08-22 11:31:39 +00:00 |
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AArch64InstrAtomics.td
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[AArch64] Improve v8.1-A code-gen for atomic load-and
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2018-02-12 17:03:11 +00:00 |
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AArch64InstrFormats.td
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[AArch64] Optimise load(adr address) to ldr address
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2018-08-30 11:55:16 +00:00 |
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AArch64InstrInfo.cpp
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[AArch64] Hook up the missed machine operand flag name for MO_DLLIMPORT
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2018-08-31 08:00:34 +00:00 |
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AArch64InstrInfo.h
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[MachineOutliner][AArch64] Add support for saving LR to a register
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2018-07-30 17:45:28 +00:00 |
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AArch64InstrInfo.td
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[AArch64] Optimise load(adr address) to ldr address
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2018-08-30 11:55:16 +00:00 |
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AArch64InstructionSelector.cpp
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[AArch64] Add Tiny Code Model for AArch64
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2018-08-22 11:31:39 +00:00 |
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AArch64LegalizerInfo.cpp
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[AArch64][GlobalISel] Make G_BLOCK_ADDR legal.
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2018-07-31 00:08:56 +00:00 |
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AArch64LegalizerInfo.h
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[aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal
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2017-11-28 20:21:15 +00:00 |
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AArch64LoadStoreOptimizer.cpp
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[MI] Change the array of `MachineMemOperand` pointers to be
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2018-08-16 21:30:05 +00:00 |
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AArch64MCInstLower.cpp
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Move TargetLoweringObjectFile from CodeGen to Target to fix layering
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2018-03-23 23:58:19 +00:00 |
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AArch64MCInstLower.h
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…
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AArch64MachineFunctionInfo.h
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Remove trailing space
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2018-07-30 19:41:25 +00:00 |
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AArch64MacroFusion.cpp
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Remove \brief commands from doxygen comments.
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2018-05-01 15:54:18 +00:00 |
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AArch64MacroFusion.h
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…
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AArch64PBQPRegAlloc.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64PBQPRegAlloc.h
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…
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AArch64PerfectShuffle.h
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…
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AArch64PromoteConstant.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64RedundantCopyElimination.cpp
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[CodeGen][AArch64] Use RegUnits to track register aliases. (NFC)
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2018-05-23 17:49:38 +00:00 |
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AArch64RegisterBankInfo.cpp
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[AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR
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2017-11-18 04:28:59 +00:00 |
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AArch64RegisterBankInfo.h
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…
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AArch64RegisterBanks.td
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…
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AArch64RegisterInfo.cpp
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[CodeGen] emit inline asm clobber list warnings for reserved (cont)
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2018-08-30 12:52:35 +00:00 |
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AArch64RegisterInfo.h
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[CodeGen] emit inline asm clobber list warnings for reserved (cont)
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2018-08-30 12:52:35 +00:00 |
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AArch64RegisterInfo.td
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[AArch64][SVE] Asm: Add MOVPRFX instructions.
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2018-07-30 15:42:46 +00:00 |
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AArch64SIMDInstrOpt.cpp
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[TargetSchedule] shrink interface for init(); NFCI
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2018-04-08 19:56:04 +00:00 |
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AArch64SVEInstrInfo.td
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[AArch64][SVE] Asm: Enable instructions to be prefixed.
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2018-07-30 16:05:45 +00:00 |
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AArch64SchedA53.td
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[AArch64] Clean-up a few over-eager regexps in models.
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2018-03-23 11:00:42 +00:00 |
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AArch64SchedA57.td
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…
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AArch64SchedA57WriteRes.td
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…
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AArch64SchedCyclone.td
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…
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AArch64SchedExynosM1.td
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[ExynosM1][Sched] Fix resource usage in scheduling model.
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2018-06-11 07:33:08 +00:00 |
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AArch64SchedExynosM3.td
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[ExynosM3] Fix scheduling info.
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2018-05-18 13:10:41 +00:00 |
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AArch64SchedFalkor.td
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[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
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2018-03-18 19:56:15 +00:00 |
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AArch64SchedFalkorDetails.td
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[AArch64][Falkor] Correct load/store increment scheduling details
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2018-03-20 13:46:35 +00:00 |
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AArch64SchedKryo.td
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[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
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2018-03-18 19:56:15 +00:00 |
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AArch64SchedKryoDetails.td
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AArch64SchedThunderX.td
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[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
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2018-03-18 19:56:15 +00:00 |
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AArch64SchedThunderX2T99.td
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[TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.
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2018-06-13 09:41:49 +00:00 |
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AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp
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AArch64/X86: Factor out common bzero logic; NFC
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2017-12-18 23:14:28 +00:00 |
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AArch64SelectionDAGInfo.h
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…
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AArch64StorePairSuppress.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64Subtarget.cpp
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[AArch64] Add Tiny Code Model for AArch64
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2018-08-22 11:31:39 +00:00 |
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AArch64Subtarget.h
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[ARM/AArch64] Support FP16 +fp16fml instructions
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2018-08-17 11:29:49 +00:00 |
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AArch64SystemOperands.td
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[AArch64][SVE] Asm: Add SVE System registers
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2018-08-20 09:16:59 +00:00 |
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AArch64TargetMachine.cpp
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[AArch64] Add Tiny Code Model for AArch64
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2018-08-22 11:31:39 +00:00 |
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AArch64TargetMachine.h
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(Re-landing) Expose a TargetMachine::getTargetTransformInfo function
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2017-12-22 18:21:59 +00:00 |
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AArch64TargetObjectFile.cpp
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[AArch64] DWARF: do not generate AT_location for thread local
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2018-08-01 23:46:49 +00:00 |
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AArch64TargetObjectFile.h
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Move TargetLoweringObjectFile from CodeGen to Target to fix layering
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2018-03-23 23:58:19 +00:00 |
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AArch64TargetTransformInfo.cpp
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Remove trailing space
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2018-07-30 19:41:25 +00:00 |
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AArch64TargetTransformInfo.h
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[TTI, AArch64] Add transpose shuffle kind
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2018-04-26 13:48:33 +00:00 |
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CMakeLists.txt
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Revert r331816 and r331820 - [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
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2018-05-09 05:00:17 +00:00 |
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LLVMBuild.txt
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…
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SVEInstrFormats.td
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[AArch64][SVE] Asm: Enable instructions to be prefixed.
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2018-07-30 16:05:45 +00:00 |
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