forked from OSchip/llvm-project
52 lines
1.7 KiB
LLVM
52 lines
1.7 KiB
LLVM
; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=2 < %s | FileCheck %s
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; Test that the generatePhi code doesn't rename a a Phi instruction that's defined
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; in the same block. The bug causes a Phi to incorrectly depend on another Phi.
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; CHECK: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: memh([[REG0:(r[0-9]+)]]++#2:circ
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; CHECK: = mem{{u?}}h([[REG0]]+#0)
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; CHECK: endloop0
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; Function Attrs: argmemonly nounwind
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declare i8* @llvm.hexagon.circ.sthhi(i8*, i32, i32, i32) #1
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; Function Attrs: nounwind optsize
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define signext i16 @f0(i16* %a0, i16* %a1, i16 signext %a2, i16 signext %a3) #0 {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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%v0 = phi i16* [ %v10, %b1 ], [ %a1, %b0 ]
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%v1 = phi i32 [ %v13, %b1 ], [ 1, %b0 ]
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%v2 = phi i16 [ %v12, %b1 ], [ 0, %b0 ]
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%v3 = bitcast i16* %v0 to i8*
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%v4 = add nsw i32 %v1, 10
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%v5 = getelementptr inbounds i16, i16* %a0, i32 %v4
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%v6 = load i16, i16* %v5, align 2, !tbaa !0
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%v7 = sext i16 %v6 to i32
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%v8 = add nsw i32 %v7, 40000
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%v9 = tail call i8* @llvm.hexagon.circ.sthhi(i8* %v3, i32 %v8, i32 117441022, i32 2)
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%v10 = bitcast i8* %v9 to i16*
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%v11 = load i16, i16* %v10, align 2, !tbaa !0
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%v12 = add i16 %v11, %v2
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%v13 = add i32 %v1, 1
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%v14 = icmp eq i32 %v13, 1000
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br i1 %v14, label %b2, label %b1
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b2: ; preds = %b1
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br label %b3
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b3: ; preds = %b2
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ret i16 %v12
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}
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attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" }
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attributes #1 = { argmemonly nounwind }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"short", !2}
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!2 = !{!"omnipotent char", !3}
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!3 = !{!"Simple C/C++ TBAA"}
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