forked from OSchip/llvm-project
58 lines
1.9 KiB
LLVM
58 lines
1.9 KiB
LLVM
; RUN: llc -march=hexagon -mattr=+hvxv60,+hvx-length64b < %s | FileCheck %s
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; Test that we generate code for the vector byte enabled store intrinsics.
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; CHECK-LABEL: f0:
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; CHECK: if (q{{[0-3]}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
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define void @f0(<16 x i32> %a0, i8* %a1, <16 x i32> %a2) local_unnamed_addr {
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b0:
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%v0 = bitcast <16 x i32> %a0 to <512 x i1>
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tail call void @llvm.hexagon.V6.vS32b.qpred.ai(<512 x i1> %v0, i8* %a1, <16 x i32> %a2)
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ret void
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}
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; Function Attrs: argmemonly nounwind
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declare void @llvm.hexagon.V6.vS32b.qpred.ai(<512 x i1>, i8*, <16 x i32>) #0
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; CHECK-LABEL: f1:
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; CHECK: if (!q{{[0-3]}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
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define void @f1(<16 x i32> %a0, i8* %a1, <16 x i32> %a2) local_unnamed_addr {
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b0:
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%v0 = bitcast <16 x i32> %a0 to <512 x i1>
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tail call void @llvm.hexagon.V6.vS32b.nqpred.ai(<512 x i1> %v0, i8* %a1, <16 x i32> %a2)
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ret void
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}
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; Function Attrs: argmemonly nounwind
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declare void @llvm.hexagon.V6.vS32b.nqpred.ai(<512 x i1>, i8*, <16 x i32>) #0
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; CHECK-LABEL: f2:
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; CHECK: if (q{{[0-3]}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}}
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define void @f2(<16 x i32> %a0, i8* %a1, <16 x i32> %a2) local_unnamed_addr {
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b0:
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%v0 = bitcast <16 x i32> %a0 to <512 x i1>
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tail call void @llvm.hexagon.V6.vS32b.nt.qpred.ai(<512 x i1> %v0, i8* %a1, <16 x i32> %a2)
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ret void
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}
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; Function Attrs: argmemonly nounwind
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declare void @llvm.hexagon.V6.vS32b.nt.qpred.ai(<512 x i1>, i8*, <16 x i32>) #0
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; CHECK-LABEL: f3:
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; CHECK: if (!q{{[0-3]}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}}
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define void @f3(<16 x i32> %a0, i8* %a1, <16 x i32> %a2) local_unnamed_addr {
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b0:
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%v0 = bitcast <16 x i32> %a0 to <512 x i1>
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tail call void @llvm.hexagon.V6.vS32b.nt.nqpred.ai(<512 x i1> %v0, i8* %a1, <16 x i32> %a2)
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ret void
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}
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; Function Attrs: argmemonly nounwind
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declare void @llvm.hexagon.V6.vS32b.nt.nqpred.ai(<512 x i1>, i8*, <16 x i32>) #0
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attributes #0 = { argmemonly nounwind }
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