forked from OSchip/llvm-project
853 lines
28 KiB
TableGen
853 lines
28 KiB
TableGen
//=- AArch64SchedVulcan.td - Vulcan Scheduling Defs ----------*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// 1. Introduction
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//
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// This file defines the machine model for Broadcom Vulcan to support
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// instruction scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// 2. Pipeline Description.
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def VulcanModel : SchedMachineModel {
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let IssueWidth = 4; // 4 micro-ops dispatched at a time.
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let MicroOpBufferSize = 180; // 180 entries in micro-op re-order buffer.
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let LoadLatency = 4; // Optimistic load latency.
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let MispredictPenalty = 12; // Extra cycles for mispredicted branch.
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// Determined via a mix of micro-arch details and experimentation.
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let LoopMicroOpBufferSize = 32;
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let PostRAScheduler = 1; // Using PostRA sched.
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let CompleteModel = 1;
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}
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// Define the issue ports.
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// Port 0: ALU, FP/SIMD.
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def VulcanP0 : ProcResource<1>;
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// Port 1: ALU, FP/SIMD, integer mul/div.
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def VulcanP1 : ProcResource<1>;
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// Port 2: ALU, Branch.
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def VulcanP2 : ProcResource<1>;
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// Port 3: Store data.
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def VulcanP3 : ProcResource<1>;
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// Port 4: Load/store.
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def VulcanP4 : ProcResource<1>;
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// Port 5: Load/store.
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def VulcanP5 : ProcResource<1>;
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let SchedModel = VulcanModel in {
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// Define groups for the functional units on each issue port. Each group
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// created will be used by a WriteRes later on.
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//
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// NOTE: Some groups only contain one member. This is a way to create names for
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// the various functional units that share a single issue port. For example,
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// "VulcanI1" for ALU ops on port 1 and "VulcanF1" for FP ops on port 1.
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// Integer divide and multiply micro-ops only on port 1.
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def VulcanI1 : ProcResGroup<[VulcanP1]>;
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// Branch micro-ops only on port 2.
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def VulcanI2 : ProcResGroup<[VulcanP2]>;
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// ALU micro-ops on ports 0, 1, and 2.
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def VulcanI012 : ProcResGroup<[VulcanP0, VulcanP1, VulcanP2]>;
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// Crypto FP/SIMD micro-ops only on port 1.
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def VulcanF1 : ProcResGroup<[VulcanP1]>;
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// FP/SIMD micro-ops on ports 0 and 1.
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def VulcanF01 : ProcResGroup<[VulcanP0, VulcanP1]>;
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// Store data micro-ops only on port 3.
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def VulcanSD : ProcResGroup<[VulcanP3]>;
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// Load/store micro-ops on ports 4 and 5.
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def VulcanLS01 : ProcResGroup<[VulcanP4, VulcanP5]>;
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// 60 entry unified scheduler.
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def VulcanAny : ProcResGroup<[VulcanP0, VulcanP1, VulcanP2,
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VulcanP3, VulcanP4, VulcanP5]> {
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let BufferSize=60;
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}
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// Define commonly used write types for InstRW specializations.
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// All definitions follow the format: VulcanWrite_<NumCycles>Cyc_<Resources>.
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// 3 cycles on I1.
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def VulcanWrite_3Cyc_I1 : SchedWriteRes<[VulcanI1]> { let Latency = 3; }
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// 4 cycles on I1.
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def VulcanWrite_4Cyc_I1 : SchedWriteRes<[VulcanI1]> { let Latency = 4; }
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// 1 cycle on I0, I1, or I2.
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def VulcanWrite_1Cyc_I012 : SchedWriteRes<[VulcanI012]> { let Latency = 1; }
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// 5 cycles on F1.
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def VulcanWrite_5Cyc_F1 : SchedWriteRes<[VulcanF1]> { let Latency = 5; }
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// 7 cycles on F1.
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def VulcanWrite_7Cyc_F1 : SchedWriteRes<[VulcanF1]> { let Latency = 7; }
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// 4 cycles on F0 or F1.
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def VulcanWrite_4Cyc_F01 : SchedWriteRes<[VulcanF01]> { let Latency = 4; }
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// 5 cycles on F0 or F1.
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def VulcanWrite_5Cyc_F01 : SchedWriteRes<[VulcanF01]> { let Latency = 5; }
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// 6 cycles on F0 or F1.
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def VulcanWrite_6Cyc_F01 : SchedWriteRes<[VulcanF01]> { let Latency = 6; }
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// 7 cycles on F0 or F1.
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def VulcanWrite_7Cyc_F01 : SchedWriteRes<[VulcanF01]> { let Latency = 7; }
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// 8 cycles on F0 or F1.
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def VulcanWrite_8Cyc_F01 : SchedWriteRes<[VulcanF01]> { let Latency = 8; }
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// 16 cycles on F0 or F1.
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def VulcanWrite_16Cyc_F01 : SchedWriteRes<[VulcanF01]> {
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let Latency = 16;
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let ResourceCycles = [8];
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}
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// 23 cycles on F0 or F1.
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def VulcanWrite_23Cyc_F01 : SchedWriteRes<[VulcanF01]> {
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let Latency = 23;
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let ResourceCycles = [11];
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}
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// 1 cycles on LS0 or LS1.
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def VulcanWrite_1Cyc_LS01 : SchedWriteRes<[VulcanLS01]> { let Latency = 1; }
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// 4 cycles on LS0 or LS1.
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def VulcanWrite_4Cyc_LS01 : SchedWriteRes<[VulcanLS01]> { let Latency = 4; }
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// 5 cycles on LS0 or LS1.
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def VulcanWrite_5Cyc_LS01 : SchedWriteRes<[VulcanLS01]> { let Latency = 5; }
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// 6 cycles on LS0 or LS1.
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def VulcanWrite_6Cyc_LS01 : SchedWriteRes<[VulcanLS01]> { let Latency = 6; }
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// 5 cycles on LS0 or LS1 and I0, I1, or I2.
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def VulcanWrite_5Cyc_LS01_I012 : SchedWriteRes<[VulcanLS01, VulcanI012]> {
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let Latency = 5;
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let NumMicroOps = 2;
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}
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// 5 cycles on LS0 or LS1 and 2 of I0, I1, or I2.
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def VulcanWrite_6Cyc_LS01_I012_I012 :
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SchedWriteRes<[VulcanLS01, VulcanI012, VulcanI012]> {
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let Latency = 6;
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let NumMicroOps = 3;
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}
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// 1 cycles on LS0 or LS1 and F0 or F1.
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def VulcanWrite_1Cyc_LS01_F01 : SchedWriteRes<[VulcanLS01, VulcanF01]> {
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let Latency = 1;
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let NumMicroOps = 2;
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}
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// 5 cycles on LS0 or LS1 and F0 or F1.
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def VulcanWrite_5Cyc_LS01_F01 : SchedWriteRes<[VulcanLS01, VulcanF01]> {
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let Latency = 5;
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let NumMicroOps = 2;
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}
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// 6 cycles on LS0 or LS1 and F0 or F1.
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def VulcanWrite_6Cyc_LS01_F01 : SchedWriteRes<[VulcanLS01, VulcanF01]> {
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let Latency = 6;
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let NumMicroOps = 2;
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}
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// 7 cycles on LS0 or LS1 and F0 or F1.
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def VulcanWrite_7Cyc_LS01_F01 : SchedWriteRes<[VulcanLS01, VulcanF01]> {
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let Latency = 7;
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let NumMicroOps = 2;
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}
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// 8 cycles on LS0 or LS1 and F0 or F1.
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def VulcanWrite_8Cyc_LS01_F01 : SchedWriteRes<[VulcanLS01, VulcanF01]> {
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let Latency = 8;
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let NumMicroOps = 2;
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}
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// Define commonly used read types.
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// No forwarding is provided for these types.
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def : ReadAdvance<ReadI, 0>;
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def : ReadAdvance<ReadISReg, 0>;
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def : ReadAdvance<ReadIEReg, 0>;
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def : ReadAdvance<ReadIM, 0>;
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def : ReadAdvance<ReadIMA, 0>;
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def : ReadAdvance<ReadID, 0>;
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def : ReadAdvance<ReadExtrHi, 0>;
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def : ReadAdvance<ReadAdrBase, 0>;
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def : ReadAdvance<ReadVLD, 0>;
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}
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//===----------------------------------------------------------------------===//
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// 3. Instruction Tables.
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let SchedModel = VulcanModel in {
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//---
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// 3.1 Branch Instructions
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//---
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// Branch, immed
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// Branch and link, immed
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// Compare and branch
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def : WriteRes<WriteBr, [VulcanI2]> { let Latency = 1; }
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def : WriteRes<WriteSys, []> { let Latency = 1; }
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def : WriteRes<WriteBarrier, []> { let Latency = 1; }
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def : WriteRes<WriteHint, []> { let Latency = 1; }
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def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
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// Branch, register
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// Branch and link, register != LR
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// Branch and link, register = LR
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def : WriteRes<WriteBrReg, [VulcanI2]> { let Latency = 1; }
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//---
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// 3.2 Arithmetic and Logical Instructions
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// 3.3 Move and Shift Instructions
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//---
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// ALU, basic
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// Conditional compare
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// Conditional select
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// Address generation
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def : WriteRes<WriteI, [VulcanI012]> { let Latency = 1; }
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def : InstRW<[WriteI], (instrs COPY)>;
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// ALU, extend and/or shift
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def : WriteRes<WriteISReg, [VulcanI012]> {
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let Latency = 2;
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let ResourceCycles = [2];
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}
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def : WriteRes<WriteIEReg, [VulcanI012]> {
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let Latency = 2;
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let ResourceCycles = [2];
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}
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// Move immed
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def : WriteRes<WriteImm, [VulcanI012]> { let Latency = 1; }
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// Variable shift
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def : WriteRes<WriteIS, [VulcanI012]> { let Latency = 1; }
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//---
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// 3.4 Divide and Multiply Instructions
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//---
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// Divide, W-form
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// Latency range of 13-23. Take the average.
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def : WriteRes<WriteID32, [VulcanI1]> {
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let Latency = 18;
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let ResourceCycles = [18];
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}
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// Divide, X-form
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// Latency range of 13-39. Take the average.
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def : WriteRes<WriteID64, [VulcanI1]> {
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let Latency = 26;
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let ResourceCycles = [26];
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}
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// Multiply accumulate, W-form
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def : WriteRes<WriteIM32, [VulcanI012]> { let Latency = 5; }
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// Multiply accumulate, X-form
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def : WriteRes<WriteIM64, [VulcanI012]> { let Latency = 5; }
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// Bitfield extract, two reg
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def : WriteRes<WriteExtr, [VulcanI012]> { let Latency = 1; }
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// Bitfield move, basic
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// Bitfield move, insert
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// NOTE: Handled by WriteIS.
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// Count leading
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def : InstRW<[VulcanWrite_3Cyc_I1], (instregex "^CLS(W|X)r$",
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"^CLZ(W|X)r$")>;
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// Reverse bits/bytes
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// NOTE: Handled by WriteI.
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//---
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// 3.6 Load Instructions
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// 3.10 FP Load Instructions
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//---
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// Load register, literal
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// Load register, unscaled immed
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// Load register, immed unprivileged
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// Load register, unsigned immed
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def : WriteRes<WriteLD, [VulcanLS01]> { let Latency = 4; }
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// Load register, immed post-index
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// NOTE: Handled by WriteLD, WriteI.
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// Load register, immed pre-index
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// NOTE: Handled by WriteLD, WriteAdr.
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def : WriteRes<WriteAdr, [VulcanI012]> { let Latency = 1; }
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// Load register offset, basic
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// Load register, register offset, scale by 4/8
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// Load register, register offset, scale by 2
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// Load register offset, extend
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// Load register, register offset, extend, scale by 4/8
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// Load register, register offset, extend, scale by 2
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def VulcanWriteLDIdx : SchedWriteVariant<[
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SchedVar<ScaledIdxPred, [VulcanWrite_6Cyc_LS01_I012_I012]>,
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SchedVar<NoSchedPred, [VulcanWrite_5Cyc_LS01_I012]>]>;
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def : SchedAlias<WriteLDIdx, VulcanWriteLDIdx>;
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def VulcanReadAdrBase : SchedReadVariant<[
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SchedVar<ScaledIdxPred, [ReadDefault]>,
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SchedVar<NoSchedPred, [ReadDefault]>]>;
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def : SchedAlias<ReadAdrBase, VulcanReadAdrBase>;
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// Load pair, immed offset, normal
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// Load pair, immed offset, signed words, base != SP
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// Load pair, immed offset signed words, base = SP
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// LDP only breaks into *one* LS micro-op. Thus
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// the resources are handling by WriteLD.
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def : WriteRes<WriteLDHi, []> {
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let Latency = 5;
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}
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// Load pair, immed pre-index, normal
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// Load pair, immed pre-index, signed words
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// Load pair, immed post-index, normal
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// Load pair, immed post-index, signed words
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// NOTE: Handled by WriteLD, WriteLDHi, WriteAdr.
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//--
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// 3.7 Store Instructions
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// 3.11 FP Store Instructions
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//--
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// Store register, unscaled immed
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// Store register, immed unprivileged
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// Store register, unsigned immed
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def : WriteRes<WriteST, [VulcanLS01, VulcanSD]> {
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let Latency = 1;
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let NumMicroOps = 2;
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}
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// Store register, immed post-index
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// NOTE: Handled by WriteAdr, WriteST, ReadAdrBase
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// Store register, immed pre-index
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// NOTE: Handled by WriteAdr, WriteST
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// Store register, register offset, basic
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// Store register, register offset, scaled by 4/8
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// Store register, register offset, scaled by 2
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// Store register, register offset, extend
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// Store register, register offset, extend, scale by 4/8
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// Store register, register offset, extend, scale by 1
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def : WriteRes<WriteSTIdx, [VulcanLS01, VulcanSD, VulcanI012]> {
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let Latency = 1;
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let NumMicroOps = 3;
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}
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// Store pair, immed offset, W-form
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// Store pair, immed offset, X-form
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def : WriteRes<WriteSTP, [VulcanLS01, VulcanSD]> {
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let Latency = 1;
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let NumMicroOps = 2;
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}
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// Store pair, immed post-index, W-form
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// Store pair, immed post-index, X-form
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// Store pair, immed pre-index, W-form
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// Store pair, immed pre-index, X-form
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// NOTE: Handled by WriteAdr, WriteSTP.
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//---
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// 3.8 FP Data Processing Instructions
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//---
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// FP absolute value
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// FP min/max
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// FP negate
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def : WriteRes<WriteF, [VulcanF01]> { let Latency = 5; }
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// FP arithmetic
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def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FADD", "^FSUB")>;
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// FP compare
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def : WriteRes<WriteFCmp, [VulcanF01]> { let Latency = 5; }
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// FP divide, S-form
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// FP square root, S-form
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def : WriteRes<WriteFDiv, [VulcanF01]> {
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let Latency = 16;
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let ResourceCycles = [8];
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}
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// FP divide, D-form
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// FP square root, D-form
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def : InstRW<[VulcanWrite_23Cyc_F01], (instrs FDIVDrr, FSQRTDr)>;
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// FP multiply
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// FP multiply accumulate
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def : WriteRes<WriteFMul, [VulcanF01]> { let Latency = 6; }
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// FP round to integral
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def : InstRW<[VulcanWrite_7Cyc_F01],
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(instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>;
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// FP select
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def : InstRW<[VulcanWrite_4Cyc_F01], (instregex "^FCSEL")>;
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//---
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// 3.9 FP Miscellaneous Instructions
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//---
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// FP convert, from vec to vec reg
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// FP convert, from gen to vec reg
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// FP convert, from vec to gen reg
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def : WriteRes<WriteFCvt, [VulcanF01]> { let Latency = 7; }
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// FP move, immed
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// FP move, register
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def : WriteRes<WriteFImm, [VulcanF01]> { let Latency = 4; }
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// FP transfer, from gen to vec reg
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// FP transfer, from vec to gen reg
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def : WriteRes<WriteFCopy, [VulcanF01]> { let Latency = 4; }
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def : InstRW<[VulcanWrite_5Cyc_F01], (instrs FMOVXDHighr, FMOVDXHighr)>;
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//---
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// 3.12 ASIMD Integer Instructions
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//---
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// ASIMD absolute diff, D-form
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// ASIMD absolute diff, Q-form
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// ASIMD absolute diff accum, D-form
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// ASIMD absolute diff accum, Q-form
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// ASIMD absolute diff accum long
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// ASIMD absolute diff long
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// ASIMD arith, basic
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// ASIMD arith, complex
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// ASIMD compare
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// ASIMD logical (AND, BIC, EOR)
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// ASIMD max/min, basic
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// ASIMD max/min, reduce, 4H/4S
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// ASIMD max/min, reduce, 8B/8H
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// ASIMD max/min, reduce, 16B
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// ASIMD multiply, D-form
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// ASIMD multiply, Q-form
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// ASIMD multiply accumulate long
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// ASIMD multiply accumulate saturating long
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// ASIMD multiply long
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// ASIMD pairwise add and accumulate
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// ASIMD shift accumulate
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// ASIMD shift by immed, basic
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// ASIMD shift by immed and insert, basic, D-form
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// ASIMD shift by immed and insert, basic, Q-form
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// ASIMD shift by immed, complex
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// ASIMD shift by register, basic, D-form
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// ASIMD shift by register, basic, Q-form
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// ASIMD shift by register, complex, D-form
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// ASIMD shift by register, complex, Q-form
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def : WriteRes<WriteV, [VulcanF01]> { let Latency = 7; }
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// ASIMD arith, reduce, 4H/4S
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// ASIMD arith, reduce, 8B/8H
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// ASIMD arith, reduce, 16B
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def : InstRW<[VulcanWrite_5Cyc_F01],
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(instregex "^ADDVv", "^SADDLVv", "^UADDLVv")>;
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// ASIMD logical (MOV, MVN, ORN, ORR)
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def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^ORRv", "^ORNv", "^NOTv")>;
|
|
|
|
// ASIMD polynomial (8x8) multiply long
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instrs PMULLv8i8, PMULLv16i8)>;
|
|
|
|
//---
|
|
// 3.13 ASIMD Floating-point Instructions
|
|
//---
|
|
|
|
// ASIMD FP absolute value
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FABSv")>;
|
|
|
|
// ASIMD FP arith, normal, D-form
|
|
// ASIMD FP arith, normal, Q-form
|
|
def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FABDv", "^FADDv", "^FSUBv")>;
|
|
|
|
// ASIMD FP arith,pairwise, D-form
|
|
// ASIMD FP arith, pairwise, Q-form
|
|
def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FADDPv")>;
|
|
|
|
// ASIMD FP compare, D-form
|
|
// ASIMD FP compare, Q-form
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FACGEv", "^FACGTv")>;
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FCMEQv", "^FCMGEv",
|
|
"^FCMGTv", "^FCMLEv",
|
|
"^FCMLTv")>;
|
|
|
|
// ASIMD FP convert, long
|
|
// ASIMD FP convert, narrow
|
|
// ASIMD FP convert, other, D-form
|
|
// ASIMD FP convert, other, Q-form
|
|
// NOTE: Handled by WriteV.
|
|
|
|
// ASIMD FP divide, D-form, F32
|
|
def : InstRW<[VulcanWrite_16Cyc_F01], (instrs FDIVv2f32)>;
|
|
|
|
// ASIMD FP divide, Q-form, F32
|
|
def : InstRW<[VulcanWrite_16Cyc_F01], (instrs FDIVv4f32)>;
|
|
|
|
// ASIMD FP divide, Q-form, F64
|
|
def : InstRW<[VulcanWrite_23Cyc_F01], (instrs FDIVv2f64)>;
|
|
|
|
// ASIMD FP max/min, normal, D-form
|
|
// ASIMD FP max/min, normal, Q-form
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FMAXv", "^FMAXNMv",
|
|
"^FMINv", "^FMINNMv")>;
|
|
|
|
// ASIMD FP max/min, pairwise, D-form
|
|
// ASIMD FP max/min, pairwise, Q-form
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FMAXPv", "^FMAXNMPv",
|
|
"^FMINPv", "^FMINNMPv")>;
|
|
|
|
// ASIMD FP max/min, reduce
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FMAXVv", "^FMAXNMVv",
|
|
"^FMINVv", "^FMINNMVv")>;
|
|
|
|
// ASIMD FP multiply, D-form, FZ
|
|
// ASIMD FP multiply, D-form, no FZ
|
|
// ASIMD FP multiply, Q-form, FZ
|
|
// ASIMD FP multiply, Q-form, no FZ
|
|
def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FMULv", "^FMULXv")>;
|
|
|
|
// ASIMD FP multiply accumulate, Dform, FZ
|
|
// ASIMD FP multiply accumulate, Dform, no FZ
|
|
// ASIMD FP multiply accumulate, Qform, FZ
|
|
// ASIMD FP multiply accumulate, Qform, no FZ
|
|
def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FMLAv", "^FMLSv")>;
|
|
|
|
// ASIMD FP negate
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FNEGv")>;
|
|
|
|
// ASIMD FP round, D-form
|
|
// ASIMD FP round, Q-form
|
|
// NOTE: Handled by WriteV.
|
|
|
|
//--
|
|
// 3.14 ASIMD Miscellaneous Instructions
|
|
//--
|
|
|
|
// ASIMD bit reverse
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^RBITv")>;
|
|
|
|
// ASIMD bitwise insert, D-form
|
|
// ASIMD bitwise insert, Q-form
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^BIFv", "^BITv", "^BSLv")>;
|
|
|
|
// ASIMD count, D-form
|
|
// ASIMD count, Q-form
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^CLSv", "^CLZv", "^CNTv")>;
|
|
|
|
// ASIMD duplicate, gen reg
|
|
// ASIMD duplicate, element
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^DUPv")>;
|
|
|
|
// ASIMD extract
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^EXTv")>;
|
|
|
|
// ASIMD extract narrow
|
|
// ASIMD extract narrow, saturating
|
|
// NOTE: Handled by WriteV.
|
|
|
|
// ASIMD insert, element to element
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^INSv")>;
|
|
|
|
// ASIMD move, integer immed
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^MOVIv", "^MOVIDv")>;
|
|
|
|
// ASIMD move, FP immed
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FMOVv")>;
|
|
|
|
// ASIMD reciprocal estimate, D-form
|
|
// ASIMD reciprocal estimate, Q-form
|
|
def : InstRW<[VulcanWrite_5Cyc_F01],
|
|
(instregex "^FRECPEv", "^FRECPXv", "^URECPEv",
|
|
"^FRSQRTEv", "^URSQRTEv")>;
|
|
|
|
// ASIMD reciprocal step, D-form, FZ
|
|
// ASIMD reciprocal step, D-form, no FZ
|
|
// ASIMD reciprocal step, Q-form, FZ
|
|
// ASIMD reciprocal step, Q-form, no FZ
|
|
def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FRECPSv", "^FRSQRTSv")>;
|
|
|
|
// ASIMD reverse
|
|
def : InstRW<[VulcanWrite_5Cyc_F01],
|
|
(instregex "^REV16v", "^REV32v", "^REV64v")>;
|
|
|
|
// ASIMD table lookup, D-form
|
|
// ASIMD table lookup, Q-form
|
|
def : InstRW<[VulcanWrite_8Cyc_F01], (instregex "^TBLv", "^TBXv")>;
|
|
|
|
// ASIMD transfer, element to word or word
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^UMOVv")>;
|
|
|
|
// ASIMD transfer, element to gen reg
|
|
def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^SMOVv", "^UMOVv")>;
|
|
|
|
// ASIMD transfer gen reg to element
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^INSv")>;
|
|
|
|
// ASIMD transpose
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^TRN1v", "^TRN2v",
|
|
"^UZP1v", "^UZP2v")>;
|
|
|
|
// ASIMD unzip/zip
|
|
def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^ZIP1v", "^ZIP2v")>;
|
|
|
|
//--
|
|
// 3.15 ASIMD Load Instructions
|
|
//--
|
|
|
|
// ASIMD load, 1 element, multiple, 1 reg, D-form
|
|
// ASIMD load, 1 element, multiple, 1 reg, Q-form
|
|
def : InstRW<[VulcanWrite_4Cyc_LS01],
|
|
(instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_4Cyc_LS01, WriteAdr],
|
|
(instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD load, 1 element, multiple, 2 reg, D-form
|
|
// ASIMD load, 1 element, multiple, 2 reg, Q-form
|
|
def : InstRW<[VulcanWrite_4Cyc_LS01],
|
|
(instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_4Cyc_LS01, WriteAdr],
|
|
(instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD load, 1 element, multiple, 3 reg, D-form
|
|
// ASIMD load, 1 element, multiple, 3 reg, Q-form
|
|
def : InstRW<[VulcanWrite_5Cyc_LS01],
|
|
(instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_5Cyc_LS01, WriteAdr],
|
|
(instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD load, 1 element, multiple, 4 reg, D-form
|
|
// ASIMD load, 1 element, multiple, 4 reg, Q-form
|
|
def : InstRW<[VulcanWrite_6Cyc_LS01],
|
|
(instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_6Cyc_LS01, WriteAdr],
|
|
(instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD load, 1 element, one lane, B/H/S
|
|
// ASIMD load, 1 element, one lane, D
|
|
def : InstRW<[VulcanWrite_5Cyc_LS01_F01], (instregex "^LD1i(8|16|32|64)$")>;
|
|
def : InstRW<[VulcanWrite_5Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^LD1i(8|16|32|64)_POST$")>;
|
|
|
|
// ASIMD load, 1 element, all lanes, D-form, B/H/S
|
|
// ASIMD load, 1 element, all lanes, D-form, D
|
|
// ASIMD load, 1 element, all lanes, Q-form
|
|
def : InstRW<[VulcanWrite_5Cyc_LS01_F01],
|
|
(instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_5Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD load, 2 element, multiple, D-form, B/H/S
|
|
// ASIMD load, 2 element, multiple, Q-form, D
|
|
def : InstRW<[VulcanWrite_5Cyc_LS01_F01],
|
|
(instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_5Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD load, 2 element, one lane, B/H
|
|
// ASIMD load, 2 element, one lane, S
|
|
// ASIMD load, 2 element, one lane, D
|
|
def : InstRW<[VulcanWrite_5Cyc_LS01_F01], (instregex "^LD2i(8|16|32|64)$")>;
|
|
def : InstRW<[VulcanWrite_5Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^LD2i(8|16|32|64)_POST$")>;
|
|
|
|
// ASIMD load, 2 element, all lanes, D-form, B/H/S
|
|
// ASIMD load, 2 element, all lanes, D-form, D
|
|
// ASIMD load, 2 element, all lanes, Q-form
|
|
def : InstRW<[VulcanWrite_5Cyc_LS01_F01],
|
|
(instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_5Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD load, 3 element, multiple, D-form, B/H/S
|
|
// ASIMD load, 3 element, multiple, Q-form, B/H/S
|
|
// ASIMD load, 3 element, multiple, Q-form, D
|
|
def : InstRW<[VulcanWrite_8Cyc_LS01_F01],
|
|
(instregex "^LD3Threev(8b|4h|2s|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_8Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^LD3Threev(8b|4h|2s|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD load, 3 element, one lone, B/H
|
|
// ASIMD load, 3 element, one lane, S
|
|
// ASIMD load, 3 element, one lane, D
|
|
def : InstRW<[VulcanWrite_7Cyc_LS01_F01], (instregex "^LD3i(8|16|32|64)$")>;
|
|
def : InstRW<[VulcanWrite_7Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^LD3i(8|16|32|64)_POST$")>;
|
|
|
|
// ASIMD load, 3 element, all lanes, D-form, B/H/S
|
|
// ASIMD load, 3 element, all lanes, D-form, D
|
|
// ASIMD load, 3 element, all lanes, Q-form, B/H/S
|
|
// ASIMD load, 3 element, all lanes, Q-form, D
|
|
def : InstRW<[VulcanWrite_7Cyc_LS01_F01],
|
|
(instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_7Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD load, 4 element, multiple, D-form, B/H/S
|
|
// ASIMD load, 4 element, multiple, Q-form, B/H/S
|
|
// ASIMD load, 4 element, multiple, Q-form, D
|
|
def : InstRW<[VulcanWrite_8Cyc_LS01_F01],
|
|
(instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_8Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD load, 4 element, one lane, B/H
|
|
// ASIMD load, 4 element, one lane, S
|
|
// ASIMD load, 4 element, one lane, D
|
|
def : InstRW<[VulcanWrite_6Cyc_LS01_F01], (instregex "^LD4i(8|16|32|64)$")>;
|
|
def : InstRW<[VulcanWrite_6Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^LD4i(8|16|32|64)_POST$")>;
|
|
|
|
// ASIMD load, 4 element, all lanes, D-form, B/H/S
|
|
// ASIMD load, 4 element, all lanes, D-form, D
|
|
// ASIMD load, 4 element, all lanes, Q-form, B/H/S
|
|
// ASIMD load, 4 element, all lanes, Q-form, D
|
|
def : InstRW<[VulcanWrite_6Cyc_LS01_F01],
|
|
(instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_6Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
|
|
|
//--
|
|
// 3.16 ASIMD Store Instructions
|
|
//--
|
|
|
|
// ASIMD store, 1 element, multiple, 1 reg, D-form
|
|
// ASIMD store, 1 element, multiple, 1 reg, Q-form
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01],
|
|
(instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01, WriteAdr],
|
|
(instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD store, 1 element, multiple, 2 reg, D-form
|
|
// ASIMD store, 1 element, multiple, 2 reg, Q-form
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01],
|
|
(instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01, WriteAdr],
|
|
(instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD store, 1 element, multiple, 3 reg, D-form
|
|
// ASIMD store, 1 element, multiple, 3 reg, Q-form
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01],
|
|
(instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01, WriteAdr],
|
|
(instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD store, 1 element, multiple, 4 reg, D-form
|
|
// ASIMD store, 1 element, multiple, 4 reg, Q-form
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01],
|
|
(instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01, WriteAdr],
|
|
(instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD store, 1 element, one lane, B/H/S
|
|
// ASIMD store, 1 element, one lane, D
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01_F01],
|
|
(instregex "^ST1i(8|16|32|64)$")>;
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^ST1i(8|16|32|64)_POST$")>;
|
|
|
|
// ASIMD store, 2 element, multiple, D-form, B/H/S
|
|
// ASIMD store, 2 element, multiple, Q-form, B/H/S
|
|
// ASIMD store, 2 element, multiple, Q-form, D
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01_F01],
|
|
(instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD store, 2 element, one lane, B/H/S
|
|
// ASIMD store, 2 element, one lane, D
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01_F01],
|
|
(instregex "^ST2i(8|16|32|64)$")>;
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^ST2i(8|16|32|64)_POST$")>;
|
|
|
|
// ASIMD store, 3 element, multiple, D-form, B/H/S
|
|
// ASIMD store, 3 element, multiple, Q-form, B/H/S
|
|
// ASIMD store, 3 element, multiple, Q-form, D
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01_F01],
|
|
(instregex "^ST3Threev(8b|4h|2s|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^ST3Threev(8b|4h|2s|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD store, 3 element, one lane, B/H
|
|
// ASIMD store, 3 element, one lane, S
|
|
// ASIMD store, 3 element, one lane, D
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01_F01], (instregex "^ST3i(8|16|32|64)$")>;
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^ST3i(8|16|32|64)_POST$")>;
|
|
|
|
// ASIMD store, 4 element, multiple, D-form, B/H/S
|
|
// ASIMD store, 4 element, multiple, Q-form, B/H/S
|
|
// ASIMD store, 4 element, multiple, Q-form, D
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01_F01],
|
|
(instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|2d)$")>;
|
|
def : InstRW<[VulcanWrite_1Cyc_LS01_F01, WriteAdr],
|
|
(instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|2d)_POST$")>;
|
|
|
|
// ASIMD store, 4 element, one lane, B/H
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// ASIMD store, 4 element, one lane, S
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// ASIMD store, 4 element, one lane, D
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def : InstRW<[VulcanWrite_1Cyc_LS01_F01], (instregex "^ST4i(8|16|32|64)$")>;
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def : InstRW<[VulcanWrite_1Cyc_LS01_F01, WriteAdr],
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(instregex "^ST4i(8|16|32|64)_POST$")>;
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//--
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// 3.17 Cryptography Extensions
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//--
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// Crypto AES ops
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def : InstRW<[VulcanWrite_5Cyc_F1], (instregex "^AES")>;
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// Crypto polynomial (64x64) multiply long
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def : InstRW<[VulcanWrite_5Cyc_F1], (instrs PMULLv1i64, PMULLv2i64)>;
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// Crypto SHA1 xor ops
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// Crypto SHA1 schedule acceleration ops
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// Crypto SHA256 schedule acceleration op (1 u-op)
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// Crypto SHA256 schedule acceleration op (2 u-ops)
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// Crypto SHA256 hash acceleration ops
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def : InstRW<[VulcanWrite_7Cyc_F1], (instregex "^SHA")>;
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//--
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// 3.18 CRC
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//--
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// CRC checksum ops
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def : InstRW<[VulcanWrite_4Cyc_I1], (instregex "^CRC32")>;
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} // SchedModel = VulcanModel
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