forked from OSchip/llvm-project
230 lines
7.6 KiB
LLVM
230 lines
7.6 KiB
LLVM
; Test basic address sanitizer instrumentation.
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;
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; RUN: opt < %s -asan -asan-module -S | FileCheck --check-prefixes=CHECK,CHECK-S3 %s
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; RUN: opt < %s -asan -asan-module -asan-mapping-scale=5 -S | FileCheck --check-prefixes=CHECK,CHECK-S5 %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-unknown-linux-gnu"
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; CHECK: @llvm.global_ctors = {{.*}}@asan.module_ctor
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define i32 @test_load(i32* %a) sanitize_address {
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; CHECK-LABEL: @test_load
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; CHECK-NOT: load
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; CHECK: %[[LOAD_ADDR:[^ ]*]] = ptrtoint i32* %a to i64
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; CHECK-S3: lshr i64 %[[LOAD_ADDR]], 3
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; CHECK-S5: lshr i64 %[[LOAD_ADDR]], 5
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; CHECK: {{or|add}}
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; CHECK: %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr
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; CHECK: %[[LOAD_SHADOW:[^ ]*]] = load i8, i8* %[[LOAD_SHADOW_PTR]]
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; CHECK: icmp ne i8
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; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}!prof ![[PROF:[0-9]+]]
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;
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; First instrumentation block refines the shadow test.
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; CHECK-S3: and i64 %[[LOAD_ADDR]], 7
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; CHECK-S5: and i64 %[[LOAD_ADDR]], 31
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; CHECK: add i64 %{{.*}}, 3
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; CHECK: trunc i64 %{{.*}} to i8
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; CHECK: icmp sge i8 %{{.*}}, %[[LOAD_SHADOW]]
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; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
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;
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; The crash block reports the error.
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; CHECK: call void @__asan_report_load4(i64 %[[LOAD_ADDR]])
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; CHECK: unreachable
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;
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; The actual load.
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; CHECK: %tmp1 = load i32, i32* %a
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; CHECK: ret i32 %tmp1
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entry:
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%tmp1 = load i32, i32* %a, align 4
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ret i32 %tmp1
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}
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define void @test_store(i32* %a) sanitize_address {
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; CHECK-LABEL: @test_store
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; CHECK-NOT: store
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; CHECK: %[[STORE_ADDR:[^ ]*]] = ptrtoint i32* %a to i64
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; CHECK-S3: lshr i64 %[[STORE_ADDR]], 3
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; CHECK-S5: lshr i64 %[[STORE_ADDR]], 5
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; CHECK: {{or|add}}
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; CHECK: %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
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; CHECK: %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]]
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; CHECK: icmp ne i8
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; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
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;
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; First instrumentation block refines the shadow test.
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; CHECK-S3: and i64 %[[STORE_ADDR]], 7
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; CHECK-S5: and i64 %[[STORE_ADDR]], 31
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; CHECK: add i64 %{{.*}}, 3
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; CHECK: trunc i64 %{{.*}} to i8
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; CHECK: icmp sge i8 %{{.*}}, %[[STORE_SHADOW]]
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; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
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;
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; The crash block reports the error.
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; CHECK: call void @__asan_report_store4(i64 %[[STORE_ADDR]])
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; CHECK: unreachable
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;
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; The actual load.
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; CHECK: store i32 42, i32* %a
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; CHECK: ret void
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;
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entry:
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store i32 42, i32* %a, align 4
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ret void
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}
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; Check that asan leaves just one alloca.
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declare void @alloca_test_use([10 x i8]*)
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define void @alloca_test() sanitize_address {
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entry:
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%x = alloca [10 x i8], align 1
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%y = alloca [10 x i8], align 1
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%z = alloca [10 x i8], align 1
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call void @alloca_test_use([10 x i8]* %x)
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call void @alloca_test_use([10 x i8]* %y)
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call void @alloca_test_use([10 x i8]* %z)
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ret void
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}
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; CHECK-LABEL: define void @alloca_test()
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; CHECK: %asan_local_stack_base = alloca
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; CHECK: = alloca
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; CHECK-NOT: = alloca
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; CHECK: ret void
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define void @LongDoubleTest(x86_fp80* nocapture %a) nounwind uwtable sanitize_address {
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entry:
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store x86_fp80 0xK3FFF8000000000000000, x86_fp80* %a, align 16
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ret void
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}
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; CHECK-LABEL: LongDoubleTest
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; CHECK: __asan_report_store_n
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; CHECK: __asan_report_store_n
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; CHECK: ret void
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define void @i40test(i40* %a, i40* %b) nounwind uwtable sanitize_address {
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entry:
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%t = load i40, i40* %a
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store i40 %t, i40* %b, align 8
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ret void
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}
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; CHECK-LABEL: i40test
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; CHECK: __asan_report_load_n{{.*}}, i64 5)
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; CHECK: __asan_report_load_n{{.*}}, i64 5)
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; CHECK: __asan_report_store_n{{.*}}, i64 5)
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; CHECK: __asan_report_store_n{{.*}}, i64 5)
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; CHECK: ret void
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define void @i64test_align1(i64* %b) nounwind uwtable sanitize_address {
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entry:
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store i64 0, i64* %b, align 1
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ret void
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}
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; CHECK-LABEL: i64test_align1
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; CHECK: __asan_report_store_n{{.*}}, i64 8)
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; CHECK: __asan_report_store_n{{.*}}, i64 8)
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; CHECK: ret void
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define void @i80test(i80* %a, i80* %b) nounwind uwtable sanitize_address {
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entry:
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%t = load i80, i80* %a
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store i80 %t, i80* %b, align 8
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ret void
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}
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; CHECK-LABEL: i80test
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; CHECK: __asan_report_load_n{{.*}}, i64 10)
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; CHECK: __asan_report_load_n{{.*}}, i64 10)
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; CHECK: __asan_report_store_n{{.*}}, i64 10)
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; CHECK: __asan_report_store_n{{.*}}, i64 10)
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; CHECK: ret void
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; asan should not instrument functions with available_externally linkage.
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define available_externally i32 @f_available_externally(i32* %a) sanitize_address {
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entry:
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%tmp1 = load i32, i32* %a
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ret i32 %tmp1
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}
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; CHECK-LABEL: @f_available_externally
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; CHECK-NOT: __asan_report
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; CHECK: ret i32
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind
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declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1) nounwind
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1) nounwind
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define void @memintr_test(i8* %a, i8* %b) nounwind uwtable sanitize_address {
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entry:
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tail call void @llvm.memset.p0i8.i64(i8* %a, i8 0, i64 100, i1 false)
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tail call void @llvm.memmove.p0i8.p0i8.i64(i8* %a, i8* %b, i64 100, i1 false)
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 100, i1 false)
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ret void
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}
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; CHECK-LABEL: memintr_test
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; CHECK: __asan_memset
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; CHECK: __asan_memmove
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; CHECK: __asan_memcpy
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; CHECK: ret void
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declare void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* nocapture writeonly, i8, i64, i32) nounwind
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declare void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32) nounwind
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declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32) nounwind
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define void @memintr_element_atomic_test(i8* %a, i8* %b) nounwind uwtable sanitize_address {
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; This is a canary test to make sure that these don't get lowered into calls that don't
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; have the element-atomic property. Eventually, asan will have to be enhanced to lower
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; these properly.
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; CHECK-LABEL: memintr_element_atomic_test
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; CHECK-NEXT: tail call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 1 %a, i8 0, i64 100, i32 1)
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; CHECK-NEXT: tail call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 100, i32 1)
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; CHECK-NEXT: tail call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 100, i32 1)
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; CHECK-NEXT: ret void
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tail call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 1 %a, i8 0, i64 100, i32 1)
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tail call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 100, i32 1)
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tail call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 100, i32 1)
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ret void
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}
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; CHECK-LABEL: @test_swifterror
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; CHECK-NOT: __asan_report_load
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; CHECK: ret void
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define void @test_swifterror(i8** swifterror) sanitize_address {
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%swifterror_ptr_value = load i8*, i8** %0
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ret void
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}
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; CHECK-LABEL: @test_swifterror_2
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; CHECK-NOT: __asan_report_store
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; CHECK: ret void
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define void @test_swifterror_2(i8** swifterror) sanitize_address {
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store i8* null, i8** %0
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ret void
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}
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; CHECK-LABEL: @test_swifterror_3
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; CHECK-NOT: __asan_report_store
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; CHECK: ret void
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define void @test_swifterror_3() sanitize_address {
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%swifterror_addr = alloca swifterror i8*
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store i8* null, i8** %swifterror_addr
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call void @test_swifterror_2(i8** swifterror %swifterror_addr)
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ret void
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}
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; CHECK: define internal void @asan.module_ctor()
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; CHECK: call void @__asan_init()
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; PROF
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; CHECK: ![[PROF]] = !{!"branch_weights", i32 1, i32 100000}
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