forked from OSchip/llvm-project
65 lines
1.8 KiB
YAML
65 lines
1.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
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--- |
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define void @test_insert_128() {
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ret void
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}
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define void @test_insert_256() {
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ret void
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}
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...
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---
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name: test_insert_128
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $zmm0, $ymm1
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; ALL-LABEL: name: test_insert_128
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; ALL: [[COPY:%[0-9]+]]:_(<16 x s32>) = COPY $zmm0
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; ALL: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $xmm1
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; ALL: [[INSERT:%[0-9]+]]:_(<16 x s32>) = G_INSERT [[COPY]], [[COPY1]](<4 x s32>), 0
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; ALL: $zmm0 = COPY [[INSERT]](<16 x s32>)
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; ALL: RET 0, implicit $ymm0
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%0(<16 x s32>) = COPY $zmm0
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%1(<4 x s32>) = COPY $xmm1
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%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0
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$zmm0 = COPY %2(<16 x s32>)
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RET 0, implicit $ymm0
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...
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---
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name: test_insert_256
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $zmm0, $ymm1
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; ALL-LABEL: name: test_insert_256
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; ALL: [[COPY:%[0-9]+]]:_(<16 x s32>) = COPY $zmm0
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; ALL: [[COPY1:%[0-9]+]]:_(<8 x s32>) = COPY $ymm1
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; ALL: [[INSERT:%[0-9]+]]:_(<16 x s32>) = G_INSERT [[COPY]], [[COPY1]](<8 x s32>), 0
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; ALL: $zmm0 = COPY [[INSERT]](<16 x s32>)
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; ALL: RET 0, implicit $ymm0
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%0(<16 x s32>) = COPY $zmm0
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%1(<8 x s32>) = COPY $ymm1
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%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0
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$zmm0 = COPY %2(<16 x s32>)
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RET 0, implicit $ymm0
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...
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