forked from OSchip/llvm-project
117 lines
4.3 KiB
C++
117 lines
4.3 KiB
C++
//===- WebAssemblyDisassemblerEmitter.cpp - Disassembler tables -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the WebAssembly Disassembler Emitter.
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// It contains the implementation of the disassembler tables.
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// Documentation for the disassembler emitter in general can be found in
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// WebAssemblyDisassemblerEmitter.h.
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//
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//===----------------------------------------------------------------------===//
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#include "WebAssemblyDisassemblerEmitter.h"
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#include "llvm/TableGen/Record.h"
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namespace llvm {
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void emitWebAssemblyDisassemblerTables(
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raw_ostream &OS,
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const ArrayRef<const CodeGenInstruction *> &NumberedInstructions) {
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// First lets organize all opcodes by (prefix) byte. Prefix 0 is the
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// starting table.
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std::map<unsigned,
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std::map<unsigned, std::pair<unsigned, const CodeGenInstruction *>>>
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OpcodeTable;
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for (unsigned I = 0; I != NumberedInstructions.size(); ++I) {
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auto &CGI = *NumberedInstructions[I];
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auto &Def = *CGI.TheDef;
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if (!Def.getValue("Inst"))
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continue;
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auto &Inst = *Def.getValueAsBitsInit("Inst");
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auto Opc = static_cast<unsigned>(
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reinterpret_cast<IntInit *>(Inst.convertInitializerTo(IntRecTy::get()))
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->getValue());
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if (Opc == 0xFFFFFFFF)
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continue; // No opcode defined.
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assert(Opc <= 0xFFFF);
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auto Prefix = Opc >> 8;
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Opc = Opc & 0xFF;
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auto &CGIP = OpcodeTable[Prefix][Opc];
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if (!CGIP.second ||
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// Make sure we store the variant with the least amount of operands,
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// which is the one without explicit registers. Only few instructions
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// have these currently, would be good to have for all of them.
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// FIXME: this picks the first of many typed variants, which is
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// currently the except_ref one, though this shouldn't matter for
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// disassembly purposes.
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CGIP.second->Operands.OperandList.size() >
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CGI.Operands.OperandList.size()) {
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CGIP = std::make_pair(I, &CGI);
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}
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}
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OS << "#include \"MCTargetDesc/WebAssemblyMCTargetDesc.h\"\n";
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OS << "\n";
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OS << "namespace llvm {\n\n";
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OS << "enum EntryType : uint8_t { ";
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OS << "ET_Unused, ET_Prefix, ET_Instruction };\n\n";
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OS << "struct WebAssemblyInstruction {\n";
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OS << " uint16_t Opcode;\n";
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OS << " EntryType ET;\n";
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OS << " uint8_t NumOperands;\n";
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OS << " uint8_t Operands[4];\n";
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OS << "};\n\n";
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// Output one table per prefix.
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for (auto &PrefixPair : OpcodeTable) {
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if (PrefixPair.second.empty())
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continue;
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OS << "WebAssemblyInstruction InstructionTable" << PrefixPair.first;
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OS << "[] = {\n";
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for (unsigned I = 0; I <= 0xFF; I++) {
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auto InstIt = PrefixPair.second.find(I);
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if (InstIt != PrefixPair.second.end()) {
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// Regular instruction.
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assert(InstIt->second.second);
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auto &CGI = *InstIt->second.second;
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OS << " // 0x";
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OS.write_hex(static_cast<unsigned long long>(I));
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OS << ": " << CGI.AsmString << "\n";
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OS << " { " << InstIt->second.first << ", ET_Instruction, ";
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OS << CGI.Operands.OperandList.size() << ", {\n";
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for (auto &Op : CGI.Operands.OperandList) {
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OS << " " << Op.OperandType << ",\n";
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}
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OS << " }\n";
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} else {
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auto PrefixIt = OpcodeTable.find(I);
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// If we have a non-empty table for it that's not 0, this is a prefix.
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if (PrefixIt != OpcodeTable.end() && I && !PrefixPair.first) {
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OS << " { 0, ET_Prefix, 0, {}";
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} else {
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OS << " { 0, ET_Unused, 0, {}";
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}
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}
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OS << " },\n";
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}
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OS << "};\n\n";
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}
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// Create a table of all extension tables:
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OS << "struct { uint8_t Prefix; const WebAssemblyInstruction *Table; }\n";
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OS << "PrefixTable[] = {\n";
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for (auto &PrefixPair : OpcodeTable) {
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if (PrefixPair.second.empty() || !PrefixPair.first)
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continue;
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OS << " { " << PrefixPair.first << ", InstructionTable"
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<< PrefixPair.first;
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OS << " },\n";
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}
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OS << " { 0, nullptr }\n};\n\n";
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OS << "} // End llvm namespace\n";
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}
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} // namespace llvm
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