forked from OSchip/llvm-project
38 lines
1.7 KiB
ArmAsm
38 lines
1.7 KiB
ArmAsm
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,INTEL
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -output-asm-variant=0 < %s | FileCheck %s -check-prefixes=ALL,ATT
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -output-asm-variant=1 < %s | FileCheck %s -check-prefixes=ALL,INTEL
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.intel_syntax noprefix
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mov eax, 1
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mov ebx, 0ffh
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imul esi, edi
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lea eax, [rsi + rdi]
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# ALL: Iterations: 100
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# ALL-NEXT: Instructions: 400
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# ALL-NEXT: Total Cycles: 305
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# ALL-NEXT: Dispatch Width: 2
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# ALL-NEXT: IPC: 1.31
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# ALL-NEXT: Block RThroughput: 2.5
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# ALL: Instruction Info:
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# ALL-NEXT: [1]: #uOps
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# ALL-NEXT: [2]: Latency
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# ALL-NEXT: [3]: RThroughput
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# ALL-NEXT: [4]: MayLoad
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# ALL-NEXT: [5]: MayStore
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# ALL-NEXT: [6]: HasSideEffects (U)
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# ALL: [1] [2] [3] [4] [5] [6] Instructions:
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# ATT-NEXT: 1 1 0.50 movl $1, %eax
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# ATT-NEXT: 1 1 0.50 movl $255, %ebx
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# ATT-NEXT: 2 3 1.00 imull %edi, %esi
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# ATT-NEXT: 1 1 0.50 leal (%rsi,%rdi), %eax
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# INTEL-NEXT: 1 1 0.50 mov eax, 1
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# INTEL-NEXT: 1 1 0.50 mov ebx, 255
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# INTEL-NEXT: 2 3 1.00 imul esi, edi
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# INTEL-NEXT: 1 1 0.50 lea eax, [rsi + rdi]
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