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llvm-project/llvm/test/CodeGen/Mips
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Daniel Sanders de7816b0cd [mips][mips16] Fix machine verifier errors about incorrect register classes on load/stores. 
Summary:
[ls][bh] and [ls][bh]u cannot use sp-relative addresses and must therefore
lower frameindex nodes such that there is a copy to a CPU16Regs register. This
is now done consistently using a separate addressing mode that does not
permit frameindex nodes.

As part of this I've had to remove an optimization that reduced the number of
instructions needed to work around the lack of sp-relative addresses on [ls][bh]
and [ls][bh]u. This optimization used one of the eight CPU16Regs registers as
a copy of the stack pointer and it's implementation was the root cause of many
of the register vs register class mismatches.

lw/sw can use sp-relative addresses but we ought to ensure that we use the
correct version of lw/sw internally for things like IAS. This is not currently
the case and this change does not fix this. However, this change does clean it
up sufficiently well to fix the machine verifier failures.

Also removed irrelevant functions from stchar.ll.

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D21062

llvm-svn: 272882
 		2016-06-16 10:20:59 +00:00
..
Fast-ISel [llvm-objdump] Support detection of feature bits from the object and implement this for Mips. 2016-06-16 09:17:03 +00:00
cconv Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions" 2016-05-12 12:46:06 +00:00
compactbranches [llvm-objdump] Support detection of feature bits from the object and implement this for Mips. 2016-06-16 09:17:03 +00:00
cstmaterialization [mips] Missing test case 2016-06-15 13:49:58 +00:00
llvm-ir [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions 2016-06-15 07:46:24 +00:00
mips32r6 [mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6 2014-05-09 09:46:21 +00:00
mips64r6 [mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6 2014-05-09 09:46:21 +00:00
msa [mips][msa] Fix register/register-class mismatches in emitINSERT_DF_VIDX(). 2016-06-15 08:43:23 +00:00
2008-06-05-Carry.ll
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2008-07-03-SRet.ll [opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction 2015-02-27 19:29:02 +00:00
2008-07-06-fadd64.ll
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2008-07-07-FPExtend.ll
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2008-07-07-Float2Int.ll
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2008-07-07-IntDoubleConvertions.ll
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2008-07-15-InternalConstant.ll [opaque pointer type] Add textual IR support for explicit type parameter to gep operator 2015-03-13 18:20:45 +00:00
2008-07-15-SmallSection.ll [opaque pointer type] Add textual IR support for explicit type parameter to gep operator 2015-03-13 18:20:45 +00:00
2008-07-16-SignExtInReg.ll
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2008-07-22-Cstpool.ll
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2008-07-23-fpcmp.ll
…
2008-07-29-icmp.ll
…
2008-07-31-fcopysign.ll
…
2008-08-01-AsmInline.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
2008-08-03-ReturnDouble.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
2008-08-03-fabs64.ll
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2008-08-04-Bitconvert.ll
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2008-08-06-Alloca.ll
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2008-08-07-CC.ll
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2008-08-07-FPRound.ll
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2008-08-08-bswap.ll
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2008-08-08-ctlz.ll
…
2008-10-13-LegalizerBug.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
2008-11-10-xint_to_fp.ll Now that we have a soft-float attribute, use it instead of the 2015-05-08 00:57:22 +00:00
2009-11-16-CstPoolLoad.ll Move the Mips target to storing the ABI in the TargetMachine rather 2015-01-26 17:33:46 +00:00
2010-07-20-Switch.ll [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00
2010-11-09-CountLeading.ll
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2010-11-09-Mul.ll
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2011-05-26-BranchKillsVreg.ll
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2012-12-12-ExpandMemcpy.ll Revert "Change memcpy/memset/memmove to have dest and source alignments." 2015-11-19 05:56:52 +00:00
2013-11-18-fp64-const0.ll [mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 2014-06-12 11:55:58 +00:00
DbgValueOtherTargets.test
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abicalls.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
abiflags-xx.ll [mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI is 2014-07-14 09:40:29 +00:00
abiflags32.ll Move the Mips target to storing the ABI in the TargetMachine rather 2015-01-26 17:33:46 +00:00
addc.ll
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addi.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
addressing-mode.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
adjust-callstack-sp.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
align16.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
alloca.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
alloca16.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
analyzebranch.ll [mips] MIPS32R6 compact branch support 2016-03-14 16:24:05 +00:00
and1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
asm-large-immediate.ll [mips][ias] Explicitly disable IAS on asm-large-immediate.ll. 2015-11-13 13:02:31 +00:00
assertzext-trunc.ll [mips] Sign-extend i32 values truncated from previously zero-extended i32 values. 2016-04-13 15:07:45 +00:00
atomic.ll [mips][atomics] Fix atomic instruction descriptions and uses. 2016-06-14 11:29:28 +00:00
atomicCmpSwapPW.ll [mips] Fix emitAtomicCmpSwapPartword to handle 64 bit pointers correctly 2016-04-13 16:02:25 +00:00
atomicops.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
beqzc.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
beqzc1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
biggot.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
blez_bgez.ll Revert "[mips] Promote the result of SETCC nodes to GPR width." 2016-03-01 20:25:43 +00:00
blockaddr.ll Revert r237789 - [mips] The naming convention for private labels is ABI dependant. 2015-05-20 14:18:59 +00:00
br-jmp.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brconeq.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brconeqk.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brconeqz.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brconge.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brcongt.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brconle.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brconlt.ll [mips][microMIPS] Revert commit r267137 2016-04-25 15:40:08 +00:00
brconne.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brconnek.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brconnez.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brdelayslot.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
brind.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brsize3.ll [mips][mips16] Use isUnconditionalBranch() in AnalyzeBranch() and constant island pass. 2016-05-06 13:23:51 +00:00
brsize3a.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
bswap.ll [mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... 2014-11-07 16:54:21 +00:00
buildpairextractelementf64.ll [mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 moves 2014-07-14 12:41:31 +00:00
cache-intrinsic.ll [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
call-optimization.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
cannot-copy-registers.ll [mips][microMIPS] Fix for "Cannot copy registers" assertion 2016-04-13 06:17:21 +00:00
cfi_offset.ll [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
check-adde-redundant-moves.ll [mips] Account for constant-zero operands in ADDE nodes. 2015-02-27 09:01:39 +00:00
check-noat.ll
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ci2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
cmov.ll [mips] MIPS32/64 itineraries 2016-06-14 09:35:29 +00:00
cmplarge.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
const-mult.ll [LLVM] Remove unwanted --check-prefix=CHECK from unit tests. NFC. 2016-04-19 23:51:52 +00:00
const1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
const4a.ll [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00
const6.ll [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00
const6a.ll [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00
constantfp0.ll
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countleading.ll [mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions 2016-06-16 07:06:25 +00:00
cprestore.ll
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ctlz-v.ll [mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... 2014-11-07 16:54:21 +00:00
ctlz.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
cttz-v.ll [mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... 2014-11-07 16:54:21 +00:00
dagcombine_crash.ll Use FileCheck for test 2015-04-13 18:47:19 +00:00
delay-slot-fill-forward.ll [mips] Do not place users of $ra in the delay slot of call instructions. 2015-05-14 13:17:56 +00:00
delay-slot-kill.ll Revert r229675 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions. 2015-08-04 14:26:35 +00:00
disable-tail-merge.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
div.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
div_rem.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
divrem.ll [mips] Sign-extend i32 values truncated from previously zero-extended i32 values. 2016-04-13 15:07:45 +00:00
divu.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
divu_remu.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
double2int.ll
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dsp-patterns-cmp-vselect.ll
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dsp-patterns.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
dsp-r1.ll [mips][dsp] Fix use without def on DSPCtrl registers read by rddsp intrinsic. 2016-06-14 09:29:46 +00:00
dsp-r2.ll
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dsp-vec-load-store.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
dynamic-stack-realignment.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
eh-dwarf-cfa.ll [mips] Optimize stack pointer adjustments. 2016-06-14 13:39:43 +00:00
eh-return32.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
eh-return64.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
eh.ll Enhance BranchProbabilityInfo::calcUnreachableHeuristics for InvokeInst 2015-12-21 22:00:51 +00:00
ehframe-indirect.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
elf_eflags.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
emergency-spill-slot-near-fp.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
emit-big-cst.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
emutls_generic.ll [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00
ex2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
extins.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
f16abs.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
fabs.ll Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math 2014-04-09 09:56:43 +00:00
fastcc.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
fcmp.ll [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions 2016-06-15 07:46:24 +00:00
fcopysign-f32-f64.ll [mips] Do not use SLL for ANY_EXTEND nodes as the high bits are undefined. 2016-02-29 15:58:12 +00:00
fcopysign.ll [mips] Make isel select the correct DEXT variant up front. 2016-02-29 15:26:54 +00:00
fixdfsf.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
fmadd1.ll [MIPS]Multiple and add instructions for Mips are currently available in mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. This patch fixes the requested features and updates the corresponding test files. 2015-02-25 15:24:37 +00:00
fneg.ll Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math 2014-04-09 09:56:43 +00:00
fp-indexed-ls.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
fp-spill-reload.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
fp16-promote.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
fp16instrinsmc.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
fp16mix.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
fp16static.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
fp64a.ll [mips] Account for endianess when expanding BuildPairF64/ExtractElementF64 nodes. 2014-10-16 15:41:51 +00:00
fpbr.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
fpneeded.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
fpnotneeded.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
fpxx.ll Move the Mips target to storing the ABI in the TargetMachine rather 2015-01-26 17:33:46 +00:00
frame-address.ll
…
frem.ll
…
global-address.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
global-pointer-reg.ll
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gpreg-lazy-binding.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
gprestore.ll [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
helloworld.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
hf1_body.ll [mips] Implement 'la' macro in PIC mode for O32. 2016-06-03 09:53:06 +00:00
hf16_1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
hf16call32.ll [mips] Enable IAS by default for 32-bit MIPS targets (O32). 2016-05-14 12:43:08 +00:00
hf16call32_body.ll [mips] Enable IAS by default for 32-bit MIPS targets (O32). 2016-05-14 12:43:08 +00:00
hfptrcall.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
i32k.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
i64arg.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
imm.ll
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indirectcall.ll
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init-array.ll Replace -use-init-array with -use-ctors. 2014-09-02 13:54:53 +00:00
inlineasm-assembler-directives.ll [mips][ias] Replace invalid assembly insn in test since IAS parses inline assembly. 2015-11-13 11:44:00 +00:00
inlineasm-cnstrnt-bad-I-1.ll [mips] Use addiu in inline assembly tests since addi is not available in all ISA's 2014-05-22 11:46:58 +00:00
inlineasm-cnstrnt-bad-J.ll [mips] Use addiu in inline assembly tests since addi is not available in all ISA's 2014-05-22 11:46:58 +00:00
inlineasm-cnstrnt-bad-K.ll
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inlineasm-cnstrnt-bad-L.ll [mips] Use addiu in inline assembly tests since addi is not available in all ISA's 2014-05-22 11:46:58 +00:00
inlineasm-cnstrnt-bad-N.ll [mips] Use addiu in inline assembly tests since addi is not available in all ISA's 2014-05-22 11:46:58 +00:00
inlineasm-cnstrnt-bad-O.ll [mips] Use addiu in inline assembly tests since addi is not available in all ISA's 2014-05-22 11:46:58 +00:00
inlineasm-cnstrnt-bad-P.ll [mips] Use addiu in inline assembly tests since addi is not available in all ISA's 2014-05-22 11:46:58 +00:00
inlineasm-cnstrnt-reg.ll [mips][ias] Allow whitespace after commas in inlineasm*.ll tests. 2015-11-16 14:14:59 +00:00
inlineasm-cnstrnt-reg64.ll [mips][ias] Allow whitespace after commas in inlineasm*.ll tests. 2015-11-16 14:14:59 +00:00
inlineasm-operand-code.ll [mips] Enable IAS by default for 32-bit MIPS targets (O32). 2016-05-14 12:43:08 +00:00
inlineasm64.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
inlineasm_constraint.ll [mips] Enable IAS by default for 32-bit MIPS targets (O32). 2016-05-14 12:43:08 +00:00
inlineasm_constraint_R.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
inlineasm_constraint_ZC.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
inlineasm_constraint_m.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
inlineasmmemop.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
insn-zero-size-bb.ll Enhance BranchProbabilityInfo::calcUnreachableHeuristics for InvokeInst 2015-12-21 22:00:51 +00:00
int-to-float-conversion.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
internalfunc.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
interrupt-attr-64-error.ll [mips] Check for the correct error message in tests for interrupt attributes. 2015-10-26 14:24:30 +00:00
interrupt-attr-args-error.ll [mips] Check for the correct error message in tests for interrupt attributes. 2015-10-26 14:24:30 +00:00
interrupt-attr-error.ll [mips] Check for the correct error message in tests for interrupt attributes. 2015-10-26 14:24:30 +00:00
interrupt-attr.ll [mips] Interrupt attribute support for mips32r2+. 2015-10-26 12:38:43 +00:00
jtstat.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
l3mc.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
largeimm1.ll [mips] Optimize stack pointer adjustments. 2016-06-14 13:39:43 +00:00
largeimmprinting.ll [mips] Optimize stack pointer adjustments. 2016-06-14 13:39:43 +00:00
lazy-binding.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
lb1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
lbu1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
lcb2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
lcb3c.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
lcb4a.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
lcb5.ll [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00
lh1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
lhu1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
lit.local.cfg Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00
llcarry.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
load-store-left-right.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
longbranch.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
lw16-base-reg.ll [mips][microMIPS] Fix for "Cannot copy registers" assertion 2016-04-13 06:17:21 +00:00
machineverifier.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
madd-msub.ll [mips] Correct operand order in DSP's mthi/mtlo 2016-01-12 15:15:14 +00:00
mature-mc-support.ll
…
mbrsize4a.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
memcpy.ll Revert "Change memcpy/memset/memmove to have dest and source alignments." 2015-11-19 05:56:52 +00:00
micromips-addiu.ll [mips][micromips] Make getPointerRegClass() result depend on the instruction. 2016-05-09 13:38:25 +00:00
micromips-addu16.ll [mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator 2015-03-04 15:47:42 +00:00
micromips-and16.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
micromips-andi.ll [mips][microMIPS] Revert commits r264245 and r264248. 2016-04-02 23:06:13 +00:00
micromips-atomic.ll [mips][microMIPS] This patch implements functionality in MIPS delay slot 2014-11-21 22:04:35 +00:00
micromips-atomic1.ll [llvm-objdump] Support detection of feature bits from the object and implement this for Mips. 2016-06-16 09:17:03 +00:00
micromips-compact-branches.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
micromips-compact-jump.ll [mips][microMIPS] Delay slot filler: Replace the microMIPS JR with the JRC 2015-02-13 17:51:27 +00:00
micromips-delay-slot-jr.ll [opaque pointer type] Add textual IR support for explicit type parameter to gep operator 2015-03-13 18:20:45 +00:00
micromips-delay-slot.ll [mips][microMIPS] Delay slot filler modifications 2016-03-23 10:29:38 +00:00
micromips-directives.ll [mips] Emit '.set nomicromips' before a function's entry label 2014-04-16 11:46:59 +00:00
micromips-gp-rc.ll [mips][microMIPS] Revert commits r264245 and r264248. 2016-04-02 23:06:13 +00:00
micromips-jal.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
micromips-li.ll [mips][microMIPS] Implement CodeGen support for LI16 instruction. 2014-12-11 13:56:23 +00:00
micromips-load-effective-address.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
micromips-not16.ll [mips][microMIPS] Make usage of NOT16 by code generator 2015-03-11 20:28:31 +00:00
micromips-or16.ll [mips][microMIPS] Prevent usage of OR16_MMR6 instruction when code for microMIPS is generated. 2016-03-04 17:34:31 +00:00
micromips-rdhwr-directives.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
micromips-shift.ll [mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions 2016-04-27 11:02:23 +00:00
micromips-subu16.ll [mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator 2015-03-04 15:47:42 +00:00
micromips-sw-lw-16.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
micromips-xor16.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
mips-shf-gprel.s [MC][ELF] Handle MIPS specific .sdata and .sbss directives 2016-02-11 06:45:54 +00:00
mips16-hf-attr-2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16-hf-attr.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16_32_1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16_32_3.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16_32_4.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16_32_5.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16_32_6.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16_32_7.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16_32_8.ll [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
mips16_32_9.ll
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mips16_32_10.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16_fpret.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16ex.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16fpe.ll [mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine verifier. 2016-05-19 10:42:14 +00:00
mips64-f128-call.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
mips64-f128.ll Summary: 2016-04-14 13:43:17 +00:00
mips64-libcall.ll Now that we have a soft-float attribute, use it instead of the 2015-05-08 00:57:22 +00:00
mips64-sret.ll Replace obsolete -mattr=n64 command line option with -target-abi=n64. No functional changes. 2015-02-26 12:29:48 +00:00
mips64directive.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
mips64ext.ll Replace obsolete -mattr=n64 command line option with -target-abi=n64. No functional changes. 2015-02-26 12:29:48 +00:00
mips64extins.ll [mips] Make isel select the correct DEXT variant up front. 2016-02-29 15:26:54 +00:00
mips64fpimm0.ll Replace obsolete -mattr=n64 command line option with -target-abi=n64. No functional changes. 2015-02-26 12:29:48 +00:00
mips64fpldst.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
mips64imm.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
mips64instrs.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
mips64intldst.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
mips64lea.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
mips64muldiv.ll [mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64. 2014-06-12 10:44:10 +00:00
mips64shift.ll [mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions 2016-06-16 07:06:25 +00:00
mips64signextendsesf.ll Now that we have a soft-float attribute, use it instead of the 2015-05-08 00:57:22 +00:00
mips64sinttofpsf.ll Now that we have a soft-float attribute, use it instead of the 2015-05-08 00:57:22 +00:00
mipslopat.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
misha.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mno-ldc1-sdc1.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
mul.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mulll.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mulull.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
nacl-align.ll [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00
nacl-branch-delay.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
nacl-reserved-regs.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
named-register-n32.ll Move the Mips target to storing the ABI in the TargetMachine rather 2015-01-26 17:33:46 +00:00
named-register-n64.ll [mips] Add support for accessing $gp as a named register. 2015-01-09 17:21:30 +00:00
named-register-o32.ll [mips] Add support for accessing $gp as a named register. 2015-01-09 17:21:30 +00:00
neg1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
no-odd-spreg-msa.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
no-odd-spreg.ll [mips] Do not emit '.module [no]oddspreg' unless we really need to. 2014-07-21 10:45:47 +00:00
nomips16.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
not1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
null-streamer.ll [Mips] Add a target streamer when creating a null streamer. 2014-06-23 19:43:40 +00:00
null.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
o32_cc.ll [mips] Removed invalid test from o32_cc.ll 2016-06-15 09:47:27 +00:00
o32_cc_byval.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
o32_cc_vararg.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
octeon.ll Revert "[mips] Promote the result of SETCC nodes to GPR width." 2016-03-01 20:25:43 +00:00
octeon_popcnt.ll [mips] Sign-extend i32 values truncated from previously zero-extended i32 values. 2016-04-13 15:07:45 +00:00
optimize-fp-math.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
optimize-pic-o0.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
or1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
powif64_16.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
prevent-hoisting.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
private.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
ra-allocatable.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
rdhwr-directives.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
rem.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
remat-immed-load.ll Replace obsolete -mattr=n64 command line option with -target-abi=n64. No functional changes. 2015-02-26 12:29:48 +00:00
remu.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
return-vector.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
return_address.ll
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rotate.ll [mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions 2016-05-04 12:02:12 +00:00
s2rem.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sb1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sel1c.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sel2c.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selTBteqzCmpi.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selTBtnezCmpi.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selTBtnezSlti.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
select.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
selectcc.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
seleq.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
seleqk.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selgek.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selgt.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selle.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selltk.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selne.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selnek.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selpat.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setcc-se.ll
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seteq.ll [mips][microMIPS] Revert commit r267137 2016-04-25 15:40:08 +00:00
seteqz.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setge.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setgek.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setle.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setlt.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setltk.ll [mips][microMIPS] Revert commit r267137 2016-04-25 15:40:08 +00:00
setne.ll [mips][microMIPS] Revert commit r267137 2016-04-25 15:40:08 +00:00
setuge.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setugt.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setule.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setult.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setultk.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sh1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
shift-parts.ll
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simplebr.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sint-fp-store_pattern.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
sitofp-selectcc-opt.ll AsmPrinter: Use emitGlobalConstantFP to emit elements of constant data 2015-12-08 02:37:48 +00:00
sll1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sll2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
small-section-reserve-gp.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
spill-copy-acreg.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
sr1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sra1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sra2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
srl1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
srl2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
stack-alignment.ll
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stackcoloring.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
stacksize.ll
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start-asm-file.ll Move the Mips target to storing the ABI in the TargetMachine rather 2015-01-26 17:33:46 +00:00
stchar.ll [mips][mips16] Fix machine verifier errors about incorrect register classes on load/stores. 2016-06-16 10:20:59 +00:00
stldst.ll [mips][mips16] Fix machine verifier errors about incorrect register classes on load/stores. 2016-06-16 10:20:59 +00:00
sub1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sub2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
swzero.ll [opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction 2015-02-27 19:29:02 +00:00
tail16.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
tailcall.ll [mips][mips16] Fix machine verifier errors about incorrect register classes on load/stores. 2016-06-16 10:20:59 +00:00
thread-pointer.ll [Mips] Add support for llvm.thread.pointer intrinsic. 2016-04-27 17:21:49 +00:00
tls-alias.ll [opaque pointer type] Add textual IR support for explicit type parameter for global aliases 2015-09-11 03:22:04 +00:00
tls-models.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
tls.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
tls16.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
tls16_2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
tnaked.ll
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trap.ll
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trap1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
uitofp.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
ul1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
unalignedload.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
vector-load-store.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
vector-setcc.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
weak.ll
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xor1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
zeroreg.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00