Frank Derry Wanye 9ca6fc4e09 Add a new altera kernel name restriction check to clang-tidy. ... The altera kernel name restriction check finds kernel files and include directives whose filename is "kernel.cl", "Verilog.cl", or "VHDL.cl". Such kernel file names cause the Altera Offline Compiler to generate intermediate design files that have the same names as certain internal files, which leads to a compilation error. As per the "Guidelines for Naming the Kernel" section in the "Intel FPGA SDK for OpenCL Pro Edition: Programming Guide." This reverts the reversion from 43a38a6523.		2020-11-09 09:26:50 -05:00
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checks	Add a new altera kernel name restriction check to clang-tidy.	2020-11-09 09:26:50 -05:00
Contributing.rst	Add an explicit toggle for the static analyzer in clang-tidy	2020-09-10 10:48:17 -04:00
Integrations.rst	Fix table formatting after D87686	2020-09-16 12:27:59 +02:00
index.rst	Add a new altera check for structure packing and alignment.	2020-09-08 09:35:14 -04:00