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Simon Pilgrim c9a0779309 [X86][SSE] Enable commutation for SSE immediate blend instructions 
Patch to allow (v)blendps, (v)blendpd, (v)pblendw and vpblendd instructions to be commuted - swaps the src registers and inverts the blend mask.

This is primarily to improve memory folding (see new tests), but it also improves the quality of shuffles (see modified tests).

Differential Revision: http://reviews.llvm.org/D6015

llvm-svn: 221313
 		2014-11-04 23:25:08 +00:00
..
AArch64 [AArch64] Use the correct register class for ORR. 2014-11-04 22:20:07 +00:00
ARM Remove the cortex-a9-mp CPU. 2014-11-03 17:38:00 +00:00
CPP IR: add "cmpxchg weak" variant to support permitted failure. 2014-06-13 14:24:07 +00:00
Generic Revert "Revert "DI: Fold constant arguments into a single MDString"" 2014-10-03 20:01:09 +00:00
Hexagon Handle ctor/init_array initialization. 2014-11-03 14:56:05 +00:00
Inputs Revert "Revert "DI: Fold constant arguments into a single MDString"" 2014-10-03 20:01:09 +00:00
MSP430 Drop the W postfix on the 16-bit registers. 2014-09-10 06:58:14 +00:00
Mips Revert "[mips] Add names and tests for the hardware registers" 2014-11-04 22:15:05 +00:00
NVPTX [NVPTX] aligned byte-buffers for vector return types 2014-10-25 03:46:16 +00:00
PowerPC [PowerPC] Initial VSX intrinsic support, with min/max for vector double 2014-10-31 19:19:07 +00:00
R600 Reapply: R600: Make sure to inline all internal functions 2014-11-03 19:49:05 +00:00
SPARC Add back tests for empty function in SPARC and PowerPC. 2014-09-15 22:11:07 +00:00
SystemZ IR: add "cmpxchg weak" variant to support permitted failure. 2014-06-13 14:24:07 +00:00
Thumb [ARM, inline-asm] Fix ARMTargetLowering::getRegForInlineAsmConstraint to return 2014-11-03 20:37:04 +00:00
Thumb2 ARM: Fix a bug which was causing convergence failure in constant-island pass. 2014-10-17 01:31:47 +00:00
X86 [X86][SSE] Enable commutation for SSE immediate blend instructions 2014-11-04 23:25:08 +00:00
XCore Fix a bit of confusion about .set and produce more readable assembly. 2014-10-21 01:17:30 +00:00