forked from OSchip/llvm-project
132 lines
2.7 KiB
ReStructuredText
132 lines
2.7 KiB
ReStructuredText
tblgen - Target Description To C++ Code Generator
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=================================================
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SYNOPSIS
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--------
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:program:`tblgen` [*options*] [*filename*]
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DESCRIPTION
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-----------
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:program:`tblgen` translates from target description (``.td``) files into C++
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code that can be included in the definition of an LLVM target library. Most
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users of LLVM will not need to use this program. It is only for assisting with
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writing an LLVM target backend.
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The input and output of :program:`tblgen` is beyond the scope of this short
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introduction. Please see :doc:`../TableGenFundamentals`.
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The *filename* argument specifies the name of a Target Description (``.td``)
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file to read as input.
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OPTIONS
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-------
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.. program:: tblgen
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.. option:: -help
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Print a summary of command line options.
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.. option:: -o filename
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Specify the output file name. If ``filename`` is ``-``, then
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:program:`tblgen` sends its output to standard output.
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.. option:: -I directory
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Specify where to find other target description files for inclusion. The
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``directory`` value should be a full or partial path to a directory that
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contains target description files.
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.. option:: -asmparsernum N
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Make -gen-asm-parser emit assembly writer number ``N``.
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.. option:: -asmwriternum N
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Make -gen-asm-writer emit assembly writer number ``N``.
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.. option:: -class className
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Print the enumeration list for this class.
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.. option:: -print-records
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Print all records to standard output (default).
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.. option:: -print-enums
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Print enumeration values for a class.
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.. option:: -print-sets
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Print expanded sets for testing DAG exprs.
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.. option:: -gen-emitter
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Generate machine code emitter.
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.. option:: -gen-register-info
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Generate registers and register classes info.
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.. option:: -gen-instr-info
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Generate instruction descriptions.
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.. option:: -gen-asm-writer
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Generate the assembly writer.
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.. option:: -gen-disassembler
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Generate disassembler.
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.. option:: -gen-pseudo-lowering
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Generate pseudo instruction lowering.
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.. option:: -gen-dag-isel
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Generate a DAG (Directed Acycle Graph) instruction selector.
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.. option:: -gen-asm-matcher
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Generate assembly instruction matcher.
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.. option:: -gen-dfa-packetizer
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Generate DFA Packetizer for VLIW targets.
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.. option:: -gen-fast-isel
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Generate a "fast" instruction selector.
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.. option:: -gen-subtarget
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Generate subtarget enumerations.
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.. option:: -gen-intrinsic
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Generate intrinsic information.
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.. option:: -gen-tgt-intrinsic
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Generate target intrinsic information.
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.. option:: -gen-enhanced-disassembly-info
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Generate enhanced disassembly info.
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.. option:: -version
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Show the version number of this program.
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EXIT STATUS
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-----------
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If :program:`tblgen` succeeds, it will exit with 0. Otherwise, if an error
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occurs, it will exit with a non-zero value.
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