forked from OSchip/llvm-project
907 lines
33 KiB
C++
907 lines
33 KiB
C++
//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the MachineIRBuidler class.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DebugInfo.h"
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using namespace llvm;
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void MachineIRBuilderBase::setMF(MachineFunction &MF) {
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State.MF = &MF;
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State.MBB = nullptr;
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State.MRI = &MF.getRegInfo();
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State.TII = MF.getSubtarget().getInstrInfo();
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State.DL = DebugLoc();
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State.II = MachineBasicBlock::iterator();
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State.Observer = nullptr;
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}
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void MachineIRBuilderBase::setMBB(MachineBasicBlock &MBB) {
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State.MBB = &MBB;
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State.II = MBB.end();
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assert(&getMF() == MBB.getParent() &&
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"Basic block is in a different function");
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}
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void MachineIRBuilderBase::setInstr(MachineInstr &MI) {
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assert(MI.getParent() && "Instruction is not part of a basic block");
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setMBB(*MI.getParent());
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State.II = MI.getIterator();
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}
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void MachineIRBuilderBase::setInsertPt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II) {
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assert(MBB.getParent() == &getMF() &&
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"Basic block is in a different function");
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State.MBB = &MBB;
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State.II = II;
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}
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void MachineIRBuilderBase::recordInsertion(MachineInstr *InsertedInstr) const {
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if (State.Observer)
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State.Observer->createdInstr(*InsertedInstr);
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}
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void MachineIRBuilderBase::setChangeObserver(GISelChangeObserver &Observer) {
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State.Observer = &Observer;
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}
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void MachineIRBuilderBase::stopObservingChanges() { State.Observer = nullptr; }
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//------------------------------------------------------------------------------
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// Build instruction variants.
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//------------------------------------------------------------------------------
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MachineInstrBuilder MachineIRBuilderBase::buildInstr(unsigned Opcode) {
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return insertInstr(buildInstrNoInsert(Opcode));
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}
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MachineInstrBuilder MachineIRBuilderBase::buildInstrNoInsert(unsigned Opcode) {
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MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
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return MIB;
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}
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MachineInstrBuilder MachineIRBuilderBase::insertInstr(MachineInstrBuilder MIB) {
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getMBB().insert(getInsertPt(), MIB);
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recordInsertion(MIB);
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return MIB;
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}
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MachineInstrBuilder
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MachineIRBuilderBase::buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
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const MDNode *Expr) {
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assert(isa<DILocalVariable>(Variable) && "not a variable");
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assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
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assert(
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cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
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"Expected inlined-at fields to agree");
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return insertInstr(BuildMI(getMF(), getDL(),
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getTII().get(TargetOpcode::DBG_VALUE),
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/*IsIndirect*/ false, Reg, Variable, Expr));
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}
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MachineInstrBuilder MachineIRBuilderBase::buildIndirectDbgValue(
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unsigned Reg, const MDNode *Variable, const MDNode *Expr) {
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assert(isa<DILocalVariable>(Variable) && "not a variable");
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assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
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assert(
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cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
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"Expected inlined-at fields to agree");
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return insertInstr(BuildMI(getMF(), getDL(),
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getTII().get(TargetOpcode::DBG_VALUE),
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/*IsIndirect*/ true, Reg, Variable, Expr));
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}
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MachineInstrBuilder
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MachineIRBuilderBase::buildFIDbgValue(int FI, const MDNode *Variable,
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const MDNode *Expr) {
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assert(isa<DILocalVariable>(Variable) && "not a variable");
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assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
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assert(
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cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
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"Expected inlined-at fields to agree");
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return buildInstr(TargetOpcode::DBG_VALUE)
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.addFrameIndex(FI)
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.addImm(0)
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.addMetadata(Variable)
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.addMetadata(Expr);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildConstDbgValue(
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const Constant &C, const MDNode *Variable, const MDNode *Expr) {
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assert(isa<DILocalVariable>(Variable) && "not a variable");
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assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
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assert(
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cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
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"Expected inlined-at fields to agree");
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auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
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if (auto *CI = dyn_cast<ConstantInt>(&C)) {
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if (CI->getBitWidth() > 64)
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MIB.addCImm(CI);
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else
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MIB.addImm(CI->getZExtValue());
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} else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
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MIB.addFPImm(CFP);
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} else {
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// Insert %noreg if we didn't find a usable constant and had to drop it.
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MIB.addReg(0U);
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}
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return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildDbgLabel(const MDNode *Label) {
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assert(isa<DILabel>(Label) && "not a label");
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assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
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"Expected inlined-at fields to agree");
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auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
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return MIB.addMetadata(Label);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildFrameIndex(unsigned Res,
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int Idx) {
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assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
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return buildInstr(TargetOpcode::G_FRAME_INDEX)
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.addDef(Res)
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.addFrameIndex(Idx);
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}
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MachineInstrBuilder
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MachineIRBuilderBase::buildGlobalValue(unsigned Res, const GlobalValue *GV) {
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assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
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assert(getMRI()->getType(Res).getAddressSpace() ==
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GV->getType()->getAddressSpace() &&
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"address space mismatch");
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return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
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.addDef(Res)
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.addGlobalAddress(GV);
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}
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void MachineIRBuilderBase::validateBinaryOp(unsigned Res, unsigned Op0,
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unsigned Op1) {
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assert((getMRI()->getType(Res).isScalar() ||
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getMRI()->getType(Res).isVector()) &&
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"invalid operand type");
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assert(getMRI()->getType(Res) == getMRI()->getType(Op0) &&
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getMRI()->getType(Res) == getMRI()->getType(Op1) && "type mismatch");
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}
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MachineInstrBuilder MachineIRBuilderBase::buildGEP(unsigned Res, unsigned Op0,
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unsigned Op1) {
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assert(getMRI()->getType(Res).isPointer() &&
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getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
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assert(getMRI()->getType(Op1).isScalar() && "invalid offset type");
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return buildInstr(TargetOpcode::G_GEP)
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.addDef(Res)
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.addUse(Op0)
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.addUse(Op1);
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}
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Optional<MachineInstrBuilder>
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MachineIRBuilderBase::materializeGEP(unsigned &Res, unsigned Op0,
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const LLT &ValueTy, uint64_t Value) {
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assert(Res == 0 && "Res is a result argument");
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assert(ValueTy.isScalar() && "invalid offset type");
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if (Value == 0) {
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Res = Op0;
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return None;
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}
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Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0));
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unsigned TmpReg = getMRI()->createGenericVirtualRegister(ValueTy);
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buildConstant(TmpReg, Value);
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return buildGEP(Res, Op0, TmpReg);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildPtrMask(unsigned Res,
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unsigned Op0,
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uint32_t NumBits) {
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assert(getMRI()->getType(Res).isPointer() &&
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getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
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return buildInstr(TargetOpcode::G_PTR_MASK)
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.addDef(Res)
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.addUse(Op0)
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.addImm(NumBits);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildBr(MachineBasicBlock &Dest) {
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return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildBrIndirect(unsigned Tgt) {
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assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
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return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildCopy(unsigned Res, unsigned Op) {
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assert(getMRI()->getType(Res) == LLT() || getMRI()->getType(Op) == LLT() ||
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getMRI()->getType(Res) == getMRI()->getType(Op));
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return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op);
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}
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MachineInstrBuilder
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MachineIRBuilderBase::buildConstant(unsigned Res, const ConstantInt &Val) {
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LLT Ty = getMRI()->getType(Res);
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assert((Ty.isScalar() || Ty.isPointer()) && "invalid operand type");
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const ConstantInt *NewVal = &Val;
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if (Ty.getSizeInBits() != Val.getBitWidth())
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NewVal = ConstantInt::get(getMF().getFunction().getContext(),
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Val.getValue().sextOrTrunc(Ty.getSizeInBits()));
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return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addCImm(NewVal);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildConstant(unsigned Res,
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int64_t Val) {
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auto IntN = IntegerType::get(getMF().getFunction().getContext(),
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getMRI()->getType(Res).getSizeInBits());
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ConstantInt *CI = ConstantInt::get(IntN, Val, true);
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return buildConstant(Res, *CI);
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}
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MachineInstrBuilder
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MachineIRBuilderBase::buildFConstant(unsigned Res, const ConstantFP &Val) {
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assert(getMRI()->getType(Res).isScalar() && "invalid operand type");
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return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildFConstant(unsigned Res,
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double Val) {
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LLT DstTy = getMRI()->getType(Res);
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auto &Ctx = getMF().getFunction().getContext();
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auto *CFP =
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ConstantFP::get(Ctx, getAPFloatFromSize(Val, DstTy.getSizeInBits()));
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return buildFConstant(Res, *CFP);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildBrCond(unsigned Tst,
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MachineBasicBlock &Dest) {
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assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
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return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildLoad(unsigned Res, unsigned Addr,
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MachineMemOperand &MMO) {
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return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
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}
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MachineInstrBuilder
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MachineIRBuilderBase::buildLoadInstr(unsigned Opcode, unsigned Res,
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unsigned Addr, MachineMemOperand &MMO) {
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assert(getMRI()->getType(Res).isValid() && "invalid operand type");
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assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
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return buildInstr(Opcode)
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.addDef(Res)
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.addUse(Addr)
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.addMemOperand(&MMO);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildStore(unsigned Val,
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unsigned Addr,
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MachineMemOperand &MMO) {
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assert(getMRI()->getType(Val).isValid() && "invalid operand type");
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assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
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return buildInstr(TargetOpcode::G_STORE)
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.addUse(Val)
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.addUse(Addr)
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.addMemOperand(&MMO);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildUAdde(unsigned Res,
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unsigned CarryOut,
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unsigned Op0, unsigned Op1,
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unsigned CarryIn) {
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assert(getMRI()->getType(Res).isScalar() && "invalid operand type");
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assert(getMRI()->getType(Res) == getMRI()->getType(Op0) &&
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getMRI()->getType(Res) == getMRI()->getType(Op1) && "type mismatch");
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assert(getMRI()->getType(CarryOut).isScalar() && "invalid operand type");
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assert(getMRI()->getType(CarryOut) == getMRI()->getType(CarryIn) &&
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"type mismatch");
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return buildInstr(TargetOpcode::G_UADDE)
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.addDef(Res)
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.addDef(CarryOut)
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.addUse(Op0)
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.addUse(Op1)
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.addUse(CarryIn);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildAnyExt(unsigned Res,
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unsigned Op) {
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validateTruncExt(Res, Op, true);
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return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildSExt(unsigned Res, unsigned Op) {
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validateTruncExt(Res, Op, true);
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return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildZExt(unsigned Res, unsigned Op) {
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validateTruncExt(Res, Op, true);
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return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildExtOrTrunc(unsigned ExtOpc,
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unsigned Res,
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unsigned Op) {
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assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
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TargetOpcode::G_SEXT == ExtOpc) &&
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"Expecting Extending Opc");
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assert(getMRI()->getType(Res).isScalar() ||
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getMRI()->getType(Res).isVector());
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assert(getMRI()->getType(Res).isScalar() == getMRI()->getType(Op).isScalar());
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unsigned Opcode = TargetOpcode::COPY;
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if (getMRI()->getType(Res).getSizeInBits() >
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getMRI()->getType(Op).getSizeInBits())
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Opcode = ExtOpc;
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else if (getMRI()->getType(Res).getSizeInBits() <
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getMRI()->getType(Op).getSizeInBits())
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Opcode = TargetOpcode::G_TRUNC;
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else
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assert(getMRI()->getType(Res) == getMRI()->getType(Op));
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return buildInstr(Opcode).addDef(Res).addUse(Op);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildSExtOrTrunc(unsigned Res,
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unsigned Op) {
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return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildZExtOrTrunc(unsigned Res,
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unsigned Op) {
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return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildAnyExtOrTrunc(unsigned Res,
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unsigned Op) {
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return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilderBase::buildCast(unsigned Dst,
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unsigned Src) {
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LLT SrcTy = getMRI()->getType(Src);
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LLT DstTy = getMRI()->getType(Dst);
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if (SrcTy == DstTy)
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return buildCopy(Dst, Src);
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unsigned Opcode;
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if (SrcTy.isPointer() && DstTy.isScalar())
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Opcode = TargetOpcode::G_PTRTOINT;
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else if (DstTy.isPointer() && SrcTy.isScalar())
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Opcode = TargetOpcode::G_INTTOPTR;
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else {
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assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
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Opcode = TargetOpcode::G_BITCAST;
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}
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return buildInstr(Opcode).addDef(Dst).addUse(Src);
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}
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MachineInstrBuilder
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MachineIRBuilderBase::buildExtract(unsigned Res, unsigned Src, uint64_t Index) {
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#ifndef NDEBUG
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assert(getMRI()->getType(Src).isValid() && "invalid operand type");
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assert(getMRI()->getType(Res).isValid() && "invalid operand type");
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assert(Index + getMRI()->getType(Res).getSizeInBits() <=
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getMRI()->getType(Src).getSizeInBits() &&
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"extracting off end of register");
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#endif
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if (getMRI()->getType(Res).getSizeInBits() ==
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getMRI()->getType(Src).getSizeInBits()) {
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assert(Index == 0 && "insertion past the end of a register");
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return buildCast(Res, Src);
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}
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return buildInstr(TargetOpcode::G_EXTRACT)
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.addDef(Res)
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.addUse(Src)
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.addImm(Index);
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}
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void MachineIRBuilderBase::buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
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ArrayRef<uint64_t> Indices) {
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#ifndef NDEBUG
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assert(Ops.size() == Indices.size() && "incompatible args");
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assert(!Ops.empty() && "invalid trivial sequence");
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assert(std::is_sorted(Indices.begin(), Indices.end()) &&
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"sequence offsets must be in ascending order");
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assert(getMRI()->getType(Res).isValid() && "invalid operand type");
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for (auto Op : Ops)
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assert(getMRI()->getType(Op).isValid() && "invalid operand type");
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#endif
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LLT ResTy = getMRI()->getType(Res);
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LLT OpTy = getMRI()->getType(Ops[0]);
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unsigned OpSize = OpTy.getSizeInBits();
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bool MaybeMerge = true;
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for (unsigned i = 0; i < Ops.size(); ++i) {
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if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
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MaybeMerge = false;
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break;
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}
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}
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if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
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buildMerge(Res, Ops);
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return;
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}
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unsigned ResIn = getMRI()->createGenericVirtualRegister(ResTy);
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buildUndef(ResIn);
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for (unsigned i = 0; i < Ops.size(); ++i) {
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unsigned ResOut = i + 1 == Ops.size()
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? Res
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: getMRI()->createGenericVirtualRegister(ResTy);
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buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
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ResIn = ResOut;
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}
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}
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MachineInstrBuilder MachineIRBuilderBase::buildUndef(unsigned Res) {
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return buildInstr(TargetOpcode::G_IMPLICIT_DEF).addDef(Res);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilderBase::buildMerge(unsigned Res,
|
|
ArrayRef<unsigned> Ops) {
|
|
|
|
#ifndef NDEBUG
|
|
assert(!Ops.empty() && "invalid trivial sequence");
|
|
LLT Ty = getMRI()->getType(Ops[0]);
|
|
for (auto Reg : Ops)
|
|
assert(getMRI()->getType(Reg) == Ty && "type mismatch in input list");
|
|
assert(Ops.size() * getMRI()->getType(Ops[0]).getSizeInBits() ==
|
|
getMRI()->getType(Res).getSizeInBits() &&
|
|
"input operands do not cover output register");
|
|
#endif
|
|
|
|
if (Ops.size() == 1)
|
|
return buildCast(Res, Ops[0]);
|
|
|
|
MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_MERGE_VALUES);
|
|
MIB.addDef(Res);
|
|
for (unsigned i = 0; i < Ops.size(); ++i)
|
|
MIB.addUse(Ops[i]);
|
|
return MIB;
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilderBase::buildUnmerge(ArrayRef<unsigned> Res,
|
|
unsigned Op) {
|
|
|
|
#ifndef NDEBUG
|
|
assert(!Res.empty() && "invalid trivial sequence");
|
|
LLT Ty = getMRI()->getType(Res[0]);
|
|
for (auto Reg : Res)
|
|
assert(getMRI()->getType(Reg) == Ty && "type mismatch in input list");
|
|
assert(Res.size() * getMRI()->getType(Res[0]).getSizeInBits() ==
|
|
getMRI()->getType(Op).getSizeInBits() &&
|
|
"input operands do not cover output register");
|
|
#endif
|
|
|
|
MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_UNMERGE_VALUES);
|
|
for (unsigned i = 0; i < Res.size(); ++i)
|
|
MIB.addDef(Res[i]);
|
|
MIB.addUse(Op);
|
|
return MIB;
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildBuildVector(unsigned Res, ArrayRef<unsigned> Ops) {
|
|
#ifndef NDEBUG
|
|
assert((!Ops.empty() || Ops.size() < 2) && "Must have at least 2 operands");
|
|
assert(getMRI()->getType(Res).isVector() && "Res type must be a vector");
|
|
LLT Ty = getMRI()->getType(Ops[0]);
|
|
for (auto Reg : Ops)
|
|
assert(getMRI()->getType(Reg) == Ty && "type mismatch in input list");
|
|
assert(Ops.size() * Ty.getSizeInBits() ==
|
|
getMRI()->getType(Res).getSizeInBits() &&
|
|
"input scalars do not exactly cover the outpur vector register");
|
|
#endif
|
|
MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_BUILD_VECTOR);
|
|
MIB.addDef(Res);
|
|
for (auto Op : Ops)
|
|
MIB.addUse(Op);
|
|
return MIB;
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildBuildVectorTrunc(unsigned Res,
|
|
ArrayRef<unsigned> Ops) {
|
|
#ifndef NDEBUG
|
|
assert((!Ops.empty() || Ops.size() < 2) && "Must have at least 2 operands");
|
|
LLT Ty = getMRI()->getType(Ops[0]);
|
|
for (auto Reg : Ops)
|
|
assert(getMRI()->getType(Reg) == Ty && "type mismatch in input list");
|
|
#endif
|
|
if (getMRI()->getType(Ops[0]).getSizeInBits() ==
|
|
getMRI()->getType(Res).getElementType().getSizeInBits())
|
|
return buildBuildVector(Res, Ops);
|
|
MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC);
|
|
MIB.addDef(Res);
|
|
for (auto Op : Ops)
|
|
MIB.addUse(Op);
|
|
return MIB;
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildConcatVectors(unsigned Res, ArrayRef<unsigned> Ops) {
|
|
#ifndef NDEBUG
|
|
assert((!Ops.empty() || Ops.size() < 2) && "Must have at least 2 operands");
|
|
LLT Ty = getMRI()->getType(Ops[0]);
|
|
for (auto Reg : Ops) {
|
|
assert(getMRI()->getType(Reg).isVector() && "expected vector operand");
|
|
assert(getMRI()->getType(Reg) == Ty && "type mismatch in input list");
|
|
}
|
|
assert(Ops.size() * Ty.getSizeInBits() ==
|
|
getMRI()->getType(Res).getSizeInBits() &&
|
|
"input vectors do not exactly cover the outpur vector register");
|
|
#endif
|
|
MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_CONCAT_VECTORS);
|
|
MIB.addDef(Res);
|
|
for (auto Op : Ops)
|
|
MIB.addUse(Op);
|
|
return MIB;
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilderBase::buildInsert(unsigned Res,
|
|
unsigned Src, unsigned Op,
|
|
unsigned Index) {
|
|
assert(Index + getMRI()->getType(Op).getSizeInBits() <=
|
|
getMRI()->getType(Res).getSizeInBits() &&
|
|
"insertion past the end of a register");
|
|
|
|
if (getMRI()->getType(Res).getSizeInBits() ==
|
|
getMRI()->getType(Op).getSizeInBits()) {
|
|
return buildCast(Res, Op);
|
|
}
|
|
|
|
return buildInstr(TargetOpcode::G_INSERT)
|
|
.addDef(Res)
|
|
.addUse(Src)
|
|
.addUse(Op)
|
|
.addImm(Index);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilderBase::buildIntrinsic(Intrinsic::ID ID,
|
|
unsigned Res,
|
|
bool HasSideEffects) {
|
|
auto MIB =
|
|
buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
|
|
: TargetOpcode::G_INTRINSIC);
|
|
if (Res)
|
|
MIB.addDef(Res);
|
|
MIB.addIntrinsicID(ID);
|
|
return MIB;
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilderBase::buildTrunc(unsigned Res,
|
|
unsigned Op) {
|
|
validateTruncExt(Res, Op, false);
|
|
return buildInstr(TargetOpcode::G_TRUNC).addDef(Res).addUse(Op);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilderBase::buildFPTrunc(unsigned Res,
|
|
unsigned Op) {
|
|
validateTruncExt(Res, Op, false);
|
|
return buildInstr(TargetOpcode::G_FPTRUNC).addDef(Res).addUse(Op);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilderBase::buildICmp(CmpInst::Predicate Pred,
|
|
unsigned Res, unsigned Op0,
|
|
unsigned Op1) {
|
|
#ifndef NDEBUG
|
|
assert(getMRI()->getType(Op0) == getMRI()->getType(Op0) && "type mismatch");
|
|
assert(CmpInst::isIntPredicate(Pred) && "invalid predicate");
|
|
if (getMRI()->getType(Op0).isScalar() || getMRI()->getType(Op0).isPointer())
|
|
assert(getMRI()->getType(Res).isScalar() && "type mismatch");
|
|
else
|
|
assert(getMRI()->getType(Res).isVector() &&
|
|
getMRI()->getType(Res).getNumElements() ==
|
|
getMRI()->getType(Op0).getNumElements() &&
|
|
"type mismatch");
|
|
#endif
|
|
|
|
return buildInstr(TargetOpcode::G_ICMP)
|
|
.addDef(Res)
|
|
.addPredicate(Pred)
|
|
.addUse(Op0)
|
|
.addUse(Op1);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilderBase::buildFCmp(CmpInst::Predicate Pred,
|
|
unsigned Res, unsigned Op0,
|
|
unsigned Op1) {
|
|
#ifndef NDEBUG
|
|
assert((getMRI()->getType(Op0).isScalar() ||
|
|
getMRI()->getType(Op0).isVector()) &&
|
|
"invalid operand type");
|
|
assert(getMRI()->getType(Op0) == getMRI()->getType(Op1) && "type mismatch");
|
|
assert(CmpInst::isFPPredicate(Pred) && "invalid predicate");
|
|
if (getMRI()->getType(Op0).isScalar())
|
|
assert(getMRI()->getType(Res).isScalar() && "type mismatch");
|
|
else
|
|
assert(getMRI()->getType(Res).isVector() &&
|
|
getMRI()->getType(Res).getNumElements() ==
|
|
getMRI()->getType(Op0).getNumElements() &&
|
|
"type mismatch");
|
|
#endif
|
|
|
|
return buildInstr(TargetOpcode::G_FCMP)
|
|
.addDef(Res)
|
|
.addPredicate(Pred)
|
|
.addUse(Op0)
|
|
.addUse(Op1);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilderBase::buildSelect(unsigned Res,
|
|
unsigned Tst,
|
|
unsigned Op0,
|
|
unsigned Op1) {
|
|
#ifndef NDEBUG
|
|
LLT ResTy = getMRI()->getType(Res);
|
|
assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
|
|
"invalid operand type");
|
|
assert(ResTy == getMRI()->getType(Op0) && ResTy == getMRI()->getType(Op1) &&
|
|
"type mismatch");
|
|
if (ResTy.isScalar() || ResTy.isPointer())
|
|
assert(getMRI()->getType(Tst).isScalar() && "type mismatch");
|
|
else
|
|
assert((getMRI()->getType(Tst).isScalar() ||
|
|
(getMRI()->getType(Tst).isVector() &&
|
|
getMRI()->getType(Tst).getNumElements() ==
|
|
getMRI()->getType(Op0).getNumElements())) &&
|
|
"type mismatch");
|
|
#endif
|
|
|
|
return buildInstr(TargetOpcode::G_SELECT)
|
|
.addDef(Res)
|
|
.addUse(Tst)
|
|
.addUse(Op0)
|
|
.addUse(Op1);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildInsertVectorElement(unsigned Res, unsigned Val,
|
|
unsigned Elt, unsigned Idx) {
|
|
#ifndef NDEBUG
|
|
LLT ResTy = getMRI()->getType(Res);
|
|
LLT ValTy = getMRI()->getType(Val);
|
|
LLT EltTy = getMRI()->getType(Elt);
|
|
LLT IdxTy = getMRI()->getType(Idx);
|
|
assert(ResTy.isVector() && ValTy.isVector() && "invalid operand type");
|
|
assert(IdxTy.isScalar() && "invalid operand type");
|
|
assert(ResTy.getNumElements() == ValTy.getNumElements() && "type mismatch");
|
|
assert(ResTy.getElementType() == EltTy && "type mismatch");
|
|
#endif
|
|
|
|
return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT)
|
|
.addDef(Res)
|
|
.addUse(Val)
|
|
.addUse(Elt)
|
|
.addUse(Idx);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildExtractVectorElement(unsigned Res, unsigned Val,
|
|
unsigned Idx) {
|
|
#ifndef NDEBUG
|
|
LLT ResTy = getMRI()->getType(Res);
|
|
LLT ValTy = getMRI()->getType(Val);
|
|
LLT IdxTy = getMRI()->getType(Idx);
|
|
assert(ValTy.isVector() && "invalid operand type");
|
|
assert((ResTy.isScalar() || ResTy.isPointer()) && "invalid operand type");
|
|
assert(IdxTy.isScalar() && "invalid operand type");
|
|
assert(ValTy.getElementType() == ResTy && "type mismatch");
|
|
#endif
|
|
|
|
return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT)
|
|
.addDef(Res)
|
|
.addUse(Val)
|
|
.addUse(Idx);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilderBase::buildAtomicCmpXchgWithSuccess(
|
|
unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal,
|
|
unsigned NewVal, MachineMemOperand &MMO) {
|
|
#ifndef NDEBUG
|
|
LLT OldValResTy = getMRI()->getType(OldValRes);
|
|
LLT SuccessResTy = getMRI()->getType(SuccessRes);
|
|
LLT AddrTy = getMRI()->getType(Addr);
|
|
LLT CmpValTy = getMRI()->getType(CmpVal);
|
|
LLT NewValTy = getMRI()->getType(NewVal);
|
|
assert(OldValResTy.isScalar() && "invalid operand type");
|
|
assert(SuccessResTy.isScalar() && "invalid operand type");
|
|
assert(AddrTy.isPointer() && "invalid operand type");
|
|
assert(CmpValTy.isValid() && "invalid operand type");
|
|
assert(NewValTy.isValid() && "invalid operand type");
|
|
assert(OldValResTy == CmpValTy && "type mismatch");
|
|
assert(OldValResTy == NewValTy && "type mismatch");
|
|
#endif
|
|
|
|
return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
|
|
.addDef(OldValRes)
|
|
.addDef(SuccessRes)
|
|
.addUse(Addr)
|
|
.addUse(CmpVal)
|
|
.addUse(NewVal)
|
|
.addMemOperand(&MMO);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
|
|
unsigned CmpVal, unsigned NewVal,
|
|
MachineMemOperand &MMO) {
|
|
#ifndef NDEBUG
|
|
LLT OldValResTy = getMRI()->getType(OldValRes);
|
|
LLT AddrTy = getMRI()->getType(Addr);
|
|
LLT CmpValTy = getMRI()->getType(CmpVal);
|
|
LLT NewValTy = getMRI()->getType(NewVal);
|
|
assert(OldValResTy.isScalar() && "invalid operand type");
|
|
assert(AddrTy.isPointer() && "invalid operand type");
|
|
assert(CmpValTy.isValid() && "invalid operand type");
|
|
assert(NewValTy.isValid() && "invalid operand type");
|
|
assert(OldValResTy == CmpValTy && "type mismatch");
|
|
assert(OldValResTy == NewValTy && "type mismatch");
|
|
#endif
|
|
|
|
return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
|
|
.addDef(OldValRes)
|
|
.addUse(Addr)
|
|
.addUse(CmpVal)
|
|
.addUse(NewVal)
|
|
.addMemOperand(&MMO);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildAtomicRMW(unsigned Opcode, unsigned OldValRes,
|
|
unsigned Addr, unsigned Val,
|
|
MachineMemOperand &MMO) {
|
|
#ifndef NDEBUG
|
|
LLT OldValResTy = getMRI()->getType(OldValRes);
|
|
LLT AddrTy = getMRI()->getType(Addr);
|
|
LLT ValTy = getMRI()->getType(Val);
|
|
assert(OldValResTy.isScalar() && "invalid operand type");
|
|
assert(AddrTy.isPointer() && "invalid operand type");
|
|
assert(ValTy.isValid() && "invalid operand type");
|
|
assert(OldValResTy == ValTy && "type mismatch");
|
|
#endif
|
|
|
|
return buildInstr(Opcode)
|
|
.addDef(OldValRes)
|
|
.addUse(Addr)
|
|
.addUse(Val)
|
|
.addMemOperand(&MMO);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildAtomicRMWOr(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
|
|
unsigned Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilderBase::buildBlockAddress(unsigned Res, const BlockAddress *BA) {
|
|
#ifndef NDEBUG
|
|
assert(getMRI()->getType(Res).isPointer() && "invalid res type");
|
|
#endif
|
|
|
|
return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
|
|
}
|
|
|
|
void MachineIRBuilderBase::validateTruncExt(unsigned Dst, unsigned Src,
|
|
bool IsExtend) {
|
|
#ifndef NDEBUG
|
|
LLT SrcTy = getMRI()->getType(Src);
|
|
LLT DstTy = getMRI()->getType(Dst);
|
|
|
|
if (DstTy.isVector()) {
|
|
assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
|
|
assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
|
|
"different number of elements in a trunc/ext");
|
|
} else
|
|
assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
|
|
|
|
if (IsExtend)
|
|
assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
|
|
"invalid narrowing extend");
|
|
else
|
|
assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
|
|
"invalid widening trunc");
|
|
#endif
|
|
}
|