forked from OSchip/llvm-project
84 lines
3.6 KiB
Plaintext
84 lines
3.6 KiB
Plaintext
SUMMARY
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-------
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We met to discuss the LLVM instruction format and bytecode representation:
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ISSUES RESOLVED
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---------------
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1. We decided that we shall use a flat namespace to represent our
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variables in SSA form, as opposed to having a two dimensional namespace
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of the original variable and the SSA instance subscript.
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ARGUMENT AGAINST:
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* A two dimensional namespace would be valuable when doing alias
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analysis because the extra information can help limit the scope of
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analysis.
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ARGUMENT FOR:
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* Including this information would require that all users of the LLVM
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bytecode would have to parse and handle it. This would slow down the
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common case and inflate the instruction representation with another
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infinite variable space.
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REASONING:
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* It was decided that because original variable sources could be
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reconstructed from SSA form in linear time, that it would be an
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unjustified expense for the common case to include the extra
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information for one optimization. Alias analysis itself is typically
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greater than linear in asymptotic complexity, so this extra analaysis
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would not affect the runtime of the optimization in a significant
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way. Additionally, this would be an unlikely optimization to do at
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runtime.
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IDEAS TO CONSIDER
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-----------------
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1. Including dominator information in the LLVM bytecode
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representation. This is one example of an analysis result that may be
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packaged with the bytecodes themselves. As a conceptual implementation
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idea, we could include an immediate dominator number for each basic block
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in the LLVM bytecode program. Basic blocks could be numbered according
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to the order of occurrence in the bytecode representation.
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2. Including loop header and body information. This would facilitate
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detection of intervals and natural loops.
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UNRESOLVED ISSUES
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-----------------
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1. Will oSUIF provide enough of an infrastructure to support the research
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that we will be doing? We know that it has less than stellar
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performance, but hope that this will be of little importance for our
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static compiler. This could affect us if we decided to do some IP
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research. Also we do not yet understand the level of exception support
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currently implemented.
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2. Should we consider the requirements of a direct hardware implementation
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of the LLVM when we design it? If so, several design issues should
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have their priorities shifted. The other option is to focus on a
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software layer interpreting the LLVM in all cases.
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3. Should we use some form of packetized format to improve forward
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compatibility? For example, we could design the system to encode a
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packet type and length field before analysis information, to allow a
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runtime to skip information that it didn't understand in a bytecode
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stream. The obvious benefit would be for compatibility, the drawback
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is that it would tend to splinter that 'standard' LLVM definition.
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4. Should we use fixed length instructions or variable length
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instructions? Fetching variable length instructions is expensive (for
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either hardware or software based LLVM runtimes), but we have several
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'infinite' spaces that instructions operate in (SSA register numbers,
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type spaces, or packet length [if packets were implemented]). Several
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options were mentioned including:
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A. Using 16 or 32 bit numbers, which would be 'big enough'
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B. A scheme similar to how UTF-8 works, to encode infinite numbers
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while keeping small number small.
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C. Use something similar to Huffman encoding, so that the most common
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numbers are the smallest.
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-Chris
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