forked from OSchip/llvm-project
58 lines
1.6 KiB
Plaintext
58 lines
1.6 KiB
Plaintext
{
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"arrays" : [
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{
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"name" : "MemRef_C",
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"sizes" : [ "1536" ],
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"type" : "float"
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},
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{
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"name" : "MemRef_A",
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"sizes" : [ "1536" ],
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"type" : "float"
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},
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{
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"name" : "MemRef_B",
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"sizes" : [ "1536" ],
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"type" : "float"
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}
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],
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"context" : "{ : }",
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"name" : "%for.cond1.preheader---%for.end30",
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"statements" : [
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{
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"accesses" : [
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{
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"kind" : "write",
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"relation" : "{ Stmt_for_body3[i0, i1] -> MemRef_C[i0, i1] }"
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}
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],
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"domain" : "{ Stmt_for_body3[i0, i1] : 0 <= i0 <= 1535 and 0 <= i1 <= 1535 }",
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"name" : "Stmt_for_body3",
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"schedule" : "{ Stmt_for_body3[i0, i1] -> [0, i0, i1, 0] }"
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},
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{
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"accesses" : [
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{
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"kind" : "read",
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"relation" : "{ Stmt_for_body8[i0, i1, i2] -> MemRef_C[i0, i1] }"
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},
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{
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"kind" : "read",
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"relation" : "{ Stmt_for_body8[i0, i1, i2] -> MemRef_A[i0, i2] }"
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},
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{
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"kind" : "read",
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"relation" : "{ Stmt_for_body8[i0, i1, i2] -> MemRef_B[i2, i1] }"
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},
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{
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"kind" : "write",
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"relation" : "{ Stmt_for_body8[i0, i1, i2] -> MemRef_C[i0, i1] }"
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}
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],
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"domain" : "{ Stmt_for_body8[i0, i1, i2] : 0 <= i0 <= 1535 and 0 <= i1 <= 1535 and 0 <= i2 <= 1535 }",
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"name" : "Stmt_for_body8",
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"schedule" : "{ Stmt_for_body8[i0, i1, i2] -> [1, i0, i2, i1] }"
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}
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]
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}
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