forked from OSchip/llvm-project
105 lines
4.2 KiB
ArmAsm
105 lines
4.2 KiB
ArmAsm
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefixes=GCN,GFX9 %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck -check-prefixes=GCN,VI %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck -check-prefixes=ERR-SICIVI %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefixes=ERR-SICIVI %s
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// FIXME: pre-gfx9 errors should be more useful
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// FIXME: These should parse to VOP2 encoding
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v_add_u32 v1, v2, v3
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// GFX9: v_add_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x34,0xd1,0x02,0x07,0x02,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_add_u32 v1, v2, s1
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// GFX9: v_add_u32_e64 v1, v2, s1 ; encoding: [0x01,0x00,0x34,0xd1,0x02,0x03,0x00,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_add_u32 v1, s1, v2
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// GFX9: v_add_u32_e64 v1, s1, v2 ; encoding: [0x01,0x00,0x34,0xd1,0x01,0x04,0x02,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_add_u32 v1, 4.0, v2
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// GFX9: v_add_u32_e64 v1, 4.0, v2 ; encoding: [0x01,0x00,0x34,0xd1,0xf6,0x04,0x02,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_add_u32 v1, v2, 4.0
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// GFX9: v_add_u32_e64 v1, v2, 4.0 ; encoding: [0x01,0x00,0x34,0xd1,0x02,0xed,0x01,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_add_u32_e32 v1, v2, v3
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// GFX9: v_add_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x68]
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// ERR-SICIVI: :19: error: invalid operand for instruction
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v_add_u32_e32 v1, s1, v3
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// GFX9: v_add_u32_e32 v1, s1, v3 ; encoding: [0x01,0x06,0x02,0x68]
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// ERR-SICIVI: :19: error: invalid operand for instruction
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v_sub_u32 v1, v2, v3
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// GFX9: v_sub_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x35,0xd1,0x02,0x07,0x02,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_sub_u32 v1, v2, s1
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// GFX9: v_sub_u32_e64 v1, v2, s1 ; encoding: [0x01,0x00,0x35,0xd1,0x02,0x03,0x00,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_sub_u32 v1, s1, v2
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// GFX9: v_sub_u32_e64 v1, s1, v2 ; encoding: [0x01,0x00,0x35,0xd1,0x01,0x04,0x02,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_sub_u32 v1, 4.0, v2
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// GFX9: v_sub_u32_e64 v1, 4.0, v2 ; encoding: [0x01,0x00,0x35,0xd1,0xf6,0x04,0x02,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_sub_u32 v1, v2, 4.0
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// GFX9: v_sub_u32_e64 v1, v2, 4.0 ; encoding: [0x01,0x00,0x35,0xd1,0x02,0xed,0x01,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_sub_u32_e32 v1, v2, v3
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// GFX9: v_sub_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x6a]
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// ERR-SICIVI: :19: error: invalid operand for instruction
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v_sub_u32_e32 v1, s1, v3
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// GFX9: v_sub_u32_e32 v1, s1, v3 ; encoding: [0x01,0x06,0x02,0x6a]
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// ERR-SICIVI: :19: error: invalid operand for instruction
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v_subrev_u32 v1, v2, v3
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// GFX9: v_subrev_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x36,0xd1,0x02,0x07,0x02,0x00]
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// ERR-SICIVI: :18: error: invalid operand for instruction
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v_subrev_u32 v1, v2, s1
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// GFX9: v_subrev_u32_e64 v1, v2, s1 ; encoding: [0x01,0x00,0x36,0xd1,0x02,0x03,0x00,0x00]
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// ERR-SICIVI: :18: error: invalid operand for instruction
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v_subrev_u32 v1, s1, v2
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// GFX9: v_subrev_u32_e64 v1, s1, v2 ; encoding: [0x01,0x00,0x36,0xd1,0x01,0x04,0x02,0x00]
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// ERR-SICIVI: :18: error: invalid operand for instruction
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v_subrev_u32 v1, 4.0, v2
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// GFX9: v_subrev_u32_e64 v1, 4.0, v2 ; encoding: [0x01,0x00,0x36,0xd1,0xf6,0x04,0x02,0x00]
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// ERR-SICIVI: :18: error: invalid operand for instruction
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v_subrev_u32 v1, v2, 4.0
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// GFX9: v_subrev_u32_e64 v1, v2, 4.0 ; encoding: [0x01,0x00,0x36,0xd1,0x02,0xed,0x01,0x00]
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// ERR-SICIVI: :18: error: invalid operand for instruction
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v_subrev_u32_e32 v1, v2, v3
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// GFX9: v_subrev_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x6c]
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// ERR-SICIVI: :22: error: invalid operand for instruction
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v_subrev_u32_e32 v1, s1, v3
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// GFX9: v_subrev_u32_e32 v1, s1, v3 ; encoding: [0x01,0x06,0x02,0x6c]
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// ERR-SICIVI: :22: error: invalid operand for instruction
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v_add_u32 v1, vcc, v2, v3
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// GCN: v_add_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x32]
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v_add_u32 v1, s[0:1], v2, v3
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// GCN: v_add_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x19,0xd1,0x02,0x07,0x02,0x00]
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