forked from OSchip/llvm-project
245 lines
10 KiB
LLVM
245 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedldst -enable-arm-maskedgatscat %s -o - | FileCheck %s
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define arm_aapcs_vfpcc void @scatter_inc_minipred_4i32(<4 x i32> %data, i32* %dst, <4 x i32> %offs) {
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; CHECK-LABEL: scatter_inc_minipred_4i32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: movw r1, #3855
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; CHECK-NEXT: vmov.i32 q2, #0x4
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; CHECK-NEXT: vadd.i32 q1, q1, q2
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vstrwt.32 q0, [r0, q1, uxtw #2]
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; CHECK-NEXT: bx lr
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%1 = add <4 x i32> %offs, <i32 4, i32 4, i32 4, i32 4>
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%2 = getelementptr inbounds i32, i32* %dst, <4 x i32> %1
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call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %data, <4 x i32*> %2, i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 false>)
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ret void
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}
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define arm_aapcs_vfpcc void @scatter_inc_mini_8i16(<8 x i16> %data, i16* %dst, <8 x i32> %offs) {
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; CHECK-LABEL: scatter_inc_mini_8i16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .vsave {d8, d9}
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; CHECK-NEXT: vpush {d8, d9}
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; CHECK-NEXT: vshl.i32 q1, q1, #1
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; CHECK-NEXT: vmov.i32 q3, #0x10
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; CHECK-NEXT: vadd.i32 q1, q1, r0
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; CHECK-NEXT: vmov.u16 r2, q0[0]
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; CHECK-NEXT: vadd.i32 q4, q1, q3
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; CHECK-NEXT: vshl.i32 q1, q2, #1
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; CHECK-NEXT: vmov r1, s16
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; CHECK-NEXT: vadd.i32 q1, q1, r0
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; CHECK-NEXT: vmov r0, s17
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; CHECK-NEXT: vadd.i32 q1, q1, q3
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; CHECK-NEXT: strh r2, [r1]
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; CHECK-NEXT: vmov.u16 r1, q0[1]
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; CHECK-NEXT: strh r1, [r0]
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; CHECK-NEXT: vmov r0, s18
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; CHECK-NEXT: vmov.u16 r1, q0[2]
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; CHECK-NEXT: strh r1, [r0]
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; CHECK-NEXT: vmov r0, s19
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; CHECK-NEXT: vmov.u16 r1, q0[3]
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; CHECK-NEXT: strh r1, [r0]
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; CHECK-NEXT: vmov r0, s4
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; CHECK-NEXT: vmov.u16 r1, q0[4]
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; CHECK-NEXT: strh r1, [r0]
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; CHECK-NEXT: vmov r0, s5
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; CHECK-NEXT: vmov.u16 r1, q0[5]
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; CHECK-NEXT: strh r1, [r0]
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; CHECK-NEXT: vmov r0, s6
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; CHECK-NEXT: vmov.u16 r1, q0[6]
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; CHECK-NEXT: strh r1, [r0]
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; CHECK-NEXT: vmov r0, s7
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; CHECK-NEXT: vmov.u16 r1, q0[7]
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; CHECK-NEXT: strh r1, [r0]
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; CHECK-NEXT: vpop {d8, d9}
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; CHECK-NEXT: bx lr
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%1 = add <8 x i32> %offs, <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
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%2 = getelementptr inbounds i16, i16* %dst, <8 x i32> %1
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call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> %data, <8 x i16*> %2, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
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ret void
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}
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define arm_aapcs_vfpcc void @scatter_inc_mini_16i8(<16 x i8> %data, i8* %dst, <16 x i32> %offs) {
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; CHECK-LABEL: scatter_inc_mini_16i8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .vsave {d8, d9, d10, d11}
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; CHECK-NEXT: vpush {d8, d9, d10, d11}
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; CHECK-NEXT: vmov.i32 q5, #0x10
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; CHECK-NEXT: vadd.i32 q1, q1, r0
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; CHECK-NEXT: vadd.i32 q4, q1, q5
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; CHECK-NEXT: vmov.u8 r2, q0[0]
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; CHECK-NEXT: vmov r1, s16
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; CHECK-NEXT: vadd.i32 q3, q3, r0
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; CHECK-NEXT: vadd.i32 q2, q2, r0
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; CHECK-NEXT: vadd.i32 q3, q3, q5
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; CHECK-NEXT: vadd.i32 q2, q2, q5
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; CHECK-NEXT: strb r2, [r1]
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; CHECK-NEXT: add r1, sp, #32
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; CHECK-NEXT: vldrw.u32 q1, [r1]
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; CHECK-NEXT: vmov.u8 r1, q0[1]
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; CHECK-NEXT: vadd.i32 q1, q1, r0
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; CHECK-NEXT: vmov r0, s17
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; CHECK-NEXT: vadd.i32 q1, q1, q5
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; CHECK-NEXT: strb r1, [r0]
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; CHECK-NEXT: vmov r0, s18
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; CHECK-NEXT: vmov.u8 r1, q0[2]
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; CHECK-NEXT: strb r1, [r0]
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; CHECK-NEXT: vmov r0, s19
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; CHECK-NEXT: vmov.u8 r1, q0[3]
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; CHECK-NEXT: strb r1, [r0]
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; CHECK-NEXT: vmov r0, s8
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; CHECK-NEXT: vmov.u8 r1, q0[4]
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; CHECK-NEXT: strb r1, [r0]
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; CHECK-NEXT: vmov r0, s9
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; CHECK-NEXT: vmov.u8 r1, q0[5]
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; CHECK-NEXT: strb r1, [r0]
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; CHECK-NEXT: vmov r0, s10
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; CHECK-NEXT: vmov.u8 r1, q0[6]
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; CHECK-NEXT: strb r1, [r0]
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; CHECK-NEXT: vmov r0, s11
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; CHECK-NEXT: vmov.u8 r1, q0[7]
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; CHECK-NEXT: strb r1, [r0]
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; CHECK-NEXT: vmov r0, s12
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; CHECK-NEXT: vmov.u8 r1, q0[8]
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; CHECK-NEXT: strb r1, [r0]
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; CHECK-NEXT: vmov r0, s13
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; CHECK-NEXT: vmov.u8 r1, q0[9]
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; CHECK-NEXT: strb r1, [r0]
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; CHECK-NEXT: vmov r0, s14
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; CHECK-NEXT: vmov.u8 r1, q0[10]
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; CHECK-NEXT: strb r1, [r0]
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; CHECK-NEXT: vmov r0, s15
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; CHECK-NEXT: vmov.u8 r1, q0[11]
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; CHECK-NEXT: strb r1, [r0]
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; CHECK-NEXT: vmov r0, s4
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; CHECK-NEXT: vmov.u8 r1, q0[12]
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; CHECK-NEXT: strb r1, [r0]
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; CHECK-NEXT: vmov r0, s5
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; CHECK-NEXT: vmov.u8 r1, q0[13]
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; CHECK-NEXT: strb r1, [r0]
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; CHECK-NEXT: vmov r0, s6
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; CHECK-NEXT: vmov.u8 r1, q0[14]
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; CHECK-NEXT: strb r1, [r0]
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; CHECK-NEXT: vmov r0, s7
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; CHECK-NEXT: vmov.u8 r1, q0[15]
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; CHECK-NEXT: strb r1, [r0]
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; CHECK-NEXT: vpop {d8, d9, d10, d11}
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; CHECK-NEXT: bx lr
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%1 = add <16 x i32> %offs, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
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%2 = getelementptr inbounds i8, i8* %dst, <16 x i32> %1
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call void @llvm.masked.scatter.v16i8.v16p0i8(<16 x i8> %data, <16 x i8*> %2, i32 2, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
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ret void
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}
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define arm_aapcs_vfpcc void @scatter_inc_v4i32_complex(<4 x i32> %data1, <4 x i32> %data2, <4 x i32> %data3, i32* %dst, i32 %n) {
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; CHECK-LABEL: scatter_inc_v4i32_complex:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: .pad #24
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; CHECK-NEXT: sub sp, #24
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; CHECK-NEXT: cmp r1, #1
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; CHECK-NEXT: blt .LBB3_5
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; CHECK-NEXT: @ %bb.1: @ %vector.ph.preheader
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; CHECK-NEXT: adr r4, .LCPI3_2
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; CHECK-NEXT: bic r2, r1, #3
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; CHECK-NEXT: vldrw.u32 q3, [r4]
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; CHECK-NEXT: sub.w r12, r2, #4
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; CHECK-NEXT: adr.w lr, .LCPI3_1
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; CHECK-NEXT: movs r3, #1
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; CHECK-NEXT: vadd.i32 q3, q3, r0
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; CHECK-NEXT: add.w r3, r3, r12, lsr #2
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; CHECK-NEXT: vstrw.32 q3, [sp] @ 16-byte Spill
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; CHECK-NEXT: vldrw.u32 q3, [lr]
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; CHECK-NEXT: adr.w r12, .LCPI3_0
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; CHECK-NEXT: vadd.i32 q4, q3, r0
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; CHECK-NEXT: vldrw.u32 q3, [r12]
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; CHECK-NEXT: vadd.i32 q3, q3, r0
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; CHECK-NEXT: .LBB3_2: @ %vector.ph
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; CHECK-NEXT: @ =>This Loop Header: Depth=1
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; CHECK-NEXT: @ Child Loop BB3_3 Depth 2
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; CHECK-NEXT: vmov q6, q4
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; CHECK-NEXT: vldrw.u32 q7, [sp] @ 16-byte Reload
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; CHECK-NEXT: vmov q5, q3
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; CHECK-NEXT: dls lr, r3
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; CHECK-NEXT: .LBB3_3: @ %vector.body
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; CHECK-NEXT: @ Parent Loop BB3_2 Depth=1
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; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
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; CHECK-NEXT: vstrw.32 q0, [q5, #48]!
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; CHECK-NEXT: vstrw.32 q1, [q6, #48]!
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; CHECK-NEXT: vstrw.32 q2, [q7, #48]!
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; CHECK-NEXT: le lr, .LBB3_3
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; CHECK-NEXT: @ %bb.4: @ %middle.block
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; CHECK-NEXT: @ in Loop: Header=BB3_2 Depth=1
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: bne .LBB3_2
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; CHECK-NEXT: .LBB3_5: @ %for.cond.cleanup
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; CHECK-NEXT: add sp, #24
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; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: pop {r4, pc}
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.6:
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; CHECK-NEXT: .LCPI3_0:
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; CHECK-NEXT: .long 4294967248 @ 0xffffffd0
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; CHECK-NEXT: .long 4294967260 @ 0xffffffdc
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; CHECK-NEXT: .long 4294967272 @ 0xffffffe8
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; CHECK-NEXT: .long 4294967284 @ 0xfffffff4
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; CHECK-NEXT: .LCPI3_1:
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; CHECK-NEXT: .long 4294967252 @ 0xffffffd4
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; CHECK-NEXT: .long 4294967264 @ 0xffffffe0
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; CHECK-NEXT: .long 4294967276 @ 0xffffffec
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; CHECK-NEXT: .long 4294967288 @ 0xfffffff8
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; CHECK-NEXT: .LCPI3_2:
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; CHECK-NEXT: .long 4294967256 @ 0xffffffd8
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; CHECK-NEXT: .long 4294967268 @ 0xffffffe4
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; CHECK-NEXT: .long 4294967280 @ 0xfffffff0
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; CHECK-NEXT: .long 4294967292 @ 0xfffffffc
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entry:
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%cmp22 = icmp sgt i32 %n, 0
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br i1 %cmp22, label %vector.ph, label %for.cond.cleanup
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vector.ph: ; preds = %for.body.preheader
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%n.vec = and i32 %n, -4
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %vector.ph ], [ %vec.ind.next, %vector.body ]
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%0 = mul nuw nsw <4 x i32> %vec.ind, <i32 3, i32 3, i32 3, i32 3>
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%1 = getelementptr inbounds i32, i32* %dst, <4 x i32> %0
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call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %data1, <4 x i32*> %1, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
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%2 = add nuw nsw <4 x i32> %0, <i32 1, i32 1, i32 1, i32 1>
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%3 = getelementptr inbounds i32, i32* %dst, <4 x i32> %2
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call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %data2, <4 x i32*> %3, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
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%4 = add nuw nsw <4 x i32> %0, <i32 2, i32 2, i32 2, i32 2>
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%5 = getelementptr inbounds i32, i32* %dst, <4 x i32> %4
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call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %data3, <4 x i32*> %5, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
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%index.next = add i32 %index, 4
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%vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4>
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%6 = icmp eq i32 %index.next, %n.vec
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br i1 %6, label %middle.block, label %vector.body
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middle.block: ; preds = %vector.body
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%cmp.n = icmp eq i32 %n.vec, %n
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br i1 %cmp.n, label %for.cond.cleanup, label %vector.ph
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for.cond.cleanup: ; preds = %for.body, %middle.block, %entry
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ret void
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}
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declare void @llvm.masked.scatter.v8i8.v8p0i8(<8 x i8>, <8 x i8*>, i32, <8 x i1>)
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declare void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16>, <8 x i16*>, i32, <8 x i1>)
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declare void @llvm.masked.scatter.v8f16.v8p0f16(<8 x half>, <8 x half*>, i32, <8 x i1>)
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declare void @llvm.masked.scatter.v16i8.v16p0i8(<16 x i8>, <16 x i8*>, i32, <16 x i1>)
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declare void @llvm.masked.scatter.v4i8.v4p0i8(<4 x i8>, <4 x i8*>, i32, <4 x i1>)
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declare void @llvm.masked.scatter.v4i16.v4p0i16(<4 x i16>, <4 x i16*>, i32, <4 x i1>)
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declare void @llvm.masked.scatter.v4f16.v4p0f16(<4 x half>, <4 x half*>, i32, <4 x i1>)
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declare void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32>, <4 x i32*>, i32, <4 x i1>)
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declare void @llvm.masked.scatter.v4f32.v4p0f32(<4 x float>, <4 x float*>, i32, <4 x i1>)
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