forked from OSchip/llvm-project
129 lines
4.6 KiB
LLVM
129 lines
4.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
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; Same as vecreduce-fadd-legalization.ll, but without fmf.
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declare half @llvm.experimental.vector.reduce.v2.fadd.f16.v1f16(half, <1 x half>)
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declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v1f32(float, <1 x float>)
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declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v1f64(double, <1 x double>)
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declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v1f128(fp128, <1 x fp128>)
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declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float, <3 x float>)
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declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128, <2 x fp128>)
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declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v16f32(float, <16 x float>)
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define half @test_v1f16(<1 x half> %a) nounwind {
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; CHECK-LABEL: test_v1f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: fmov s1, wzr
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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%b = call half @llvm.experimental.vector.reduce.v2.fadd.f16.v1f16(half 0.0, <1 x half> %a)
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ret half %b
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}
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define float @test_v1f32(<1 x float> %a) nounwind {
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; CHECK-LABEL: test_v1f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: fmov s1, wzr
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: ret
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%b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v1f32(float 0.0, <1 x float> %a)
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ret float %b
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}
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define double @test_v1f64(<1 x double> %a) nounwind {
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; CHECK-LABEL: test_v1f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov d1, xzr
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; CHECK-NEXT: fadd d0, d0, d1
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; CHECK-NEXT: ret
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%b = call double @llvm.experimental.vector.reduce.v2.fadd.f64.v1f64(double 0.0, <1 x double> %a)
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ret double %b
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}
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define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v1f128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: adrp x8, .LCPI3_0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]
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; CHECK-NEXT: bl __addtf3
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; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%b = call fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v1f128(fp128 zeroinitializer, <1 x fp128> %a)
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ret fp128 %b
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}
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define float @test_v3f32(<3 x float> %a) nounwind {
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; CHECK-LABEL: test_v3f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s1, wzr
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; CHECK-NEXT: mov s2, v0.s[1]
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; CHECK-NEXT: fadd s1, s0, s1
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; CHECK-NEXT: fadd s1, s1, s2
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; CHECK-NEXT: mov s0, v0.s[2]
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; CHECK-NEXT: fadd s0, s1, s0
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; CHECK-NEXT: ret
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%b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float 0.0, <3 x float> %a)
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ret float %b
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}
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define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v2f128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #32 // =32
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; CHECK-NEXT: adrp x8, .LCPI5_0
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; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0]
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; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
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; CHECK-NEXT: bl __addtf3
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; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
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; CHECK-NEXT: bl __addtf3
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; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
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; CHECK-NEXT: add sp, sp, #32 // =32
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; CHECK-NEXT: ret
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%b = call fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a)
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ret fp128 %b
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}
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define float @test_v16f32(<16 x float> %a) nounwind {
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; CHECK-LABEL: test_v16f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s4, wzr
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; CHECK-NEXT: mov s5, v0.s[1]
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; CHECK-NEXT: fadd s4, s0, s4
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; CHECK-NEXT: fadd s4, s4, s5
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; CHECK-NEXT: mov s5, v0.s[2]
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; CHECK-NEXT: mov s0, v0.s[3]
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; CHECK-NEXT: fadd s4, s4, s5
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; CHECK-NEXT: fadd s0, s4, s0
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; CHECK-NEXT: mov s5, v1.s[1]
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: mov s4, v1.s[2]
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; CHECK-NEXT: fadd s0, s0, s5
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; CHECK-NEXT: mov s1, v1.s[3]
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; CHECK-NEXT: fadd s0, s0, s4
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: mov s5, v2.s[1]
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; CHECK-NEXT: fadd s0, s0, s2
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; CHECK-NEXT: mov s4, v2.s[2]
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; CHECK-NEXT: fadd s0, s0, s5
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; CHECK-NEXT: mov s1, v2.s[3]
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; CHECK-NEXT: fadd s0, s0, s4
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: mov s2, v3.s[1]
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; CHECK-NEXT: fadd s0, s0, s3
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; CHECK-NEXT: mov s5, v3.s[2]
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; CHECK-NEXT: fadd s0, s0, s2
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; CHECK-NEXT: fadd s0, s0, s5
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; CHECK-NEXT: mov s1, v3.s[3]
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: ret
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%b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v16f32(float 0.0, <16 x float> %a)
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ret float %b
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}
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