forked from OSchip/llvm-project
95 lines
2.7 KiB
LLVM
95 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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declare i4 @llvm.sadd.sat.i4(i4, i4)
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declare i8 @llvm.sadd.sat.i8(i8, i8)
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declare i16 @llvm.sadd.sat.i16(i16, i16)
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declare i32 @llvm.sadd.sat.i32(i32, i32)
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declare i64 @llvm.sadd.sat.i64(i64, i64)
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define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
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; CHECK-LABEL: func32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mul w8, w1, w2
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; CHECK-NEXT: adds w10, w0, w8
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; CHECK-NEXT: mov w9, #2147483647
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; CHECK-NEXT: cmp w10, #0 // =0
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; CHECK-NEXT: cinv w9, w9, ge
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; CHECK-NEXT: adds w8, w0, w8
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; CHECK-NEXT: csel w0, w9, w8, vs
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; CHECK-NEXT: ret
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%a = mul i32 %y, %z
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%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)
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ret i32 %tmp
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}
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define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
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; CHECK-LABEL: func64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adds x8, x0, x2
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; CHECK-NEXT: mov x9, #9223372036854775807
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; CHECK-NEXT: cmp x8, #0 // =0
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; CHECK-NEXT: cinv x8, x9, ge
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; CHECK-NEXT: adds x9, x0, x2
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; CHECK-NEXT: csel x0, x8, x9, vs
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; CHECK-NEXT: ret
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%a = mul i64 %y, %z
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%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
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ret i64 %tmp
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}
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define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
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; CHECK-LABEL: func16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxth w8, w0
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; CHECK-NEXT: mul w9, w1, w2
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; CHECK-NEXT: mov w10, #32767
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; CHECK-NEXT: add w8, w8, w9, sxth
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; CHECK-NEXT: cmp w8, w10
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; CHECK-NEXT: csel w8, w8, w10, lt
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; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768
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; CHECK-NEXT: mov w9, #-32768
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; CHECK-NEXT: csel w0, w8, w9, gt
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; CHECK-NEXT: ret
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%a = mul i16 %y, %z
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%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %a)
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ret i16 %tmp
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}
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define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
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; CHECK-LABEL: func8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxtb w8, w0
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; CHECK-NEXT: mul w9, w1, w2
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; CHECK-NEXT: add w8, w8, w9, sxtb
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; CHECK-NEXT: mov w10, #127
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; CHECK-NEXT: cmp w8, #127 // =127
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; CHECK-NEXT: csel w8, w8, w10, lt
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; CHECK-NEXT: cmn w8, #128 // =128
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; CHECK-NEXT: mov w9, #-128
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; CHECK-NEXT: csel w0, w8, w9, gt
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; CHECK-NEXT: ret
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%a = mul i8 %y, %z
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%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %a)
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ret i8 %tmp
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}
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define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
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; CHECK-LABEL: func4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mul w9, w1, w2
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; CHECK-NEXT: sbfx w8, w0, #0, #4
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; CHECK-NEXT: lsl w9, w9, #28
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; CHECK-NEXT: add w8, w8, w9, asr #28
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; CHECK-NEXT: mov w10, #7
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; CHECK-NEXT: cmp w8, #7 // =7
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; CHECK-NEXT: csel w8, w8, w10, lt
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; CHECK-NEXT: cmn w8, #8 // =8
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; CHECK-NEXT: mov w9, #-8
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; CHECK-NEXT: csel w0, w8, w9, gt
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; CHECK-NEXT: ret
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%a = mul i4 %y, %z
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%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %a)
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ret i4 %tmp
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}
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