forked from OSchip/llvm-project
271 lines
9.7 KiB
LLVM
271 lines
9.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
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; If the target's divss/divps instructions are substantially
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; slower than rcpss/rcpps with a Newton-Raphson refinement,
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; we should generate the estimate sequence.
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; See PR21385 ( http://llvm.org/bugs/show_bug.cgi?id=21385 )
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; for details about the accuracy, speed, and implementation
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; differences of x86 reciprocal estimates.
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define float @f32_no_estimate(float %x) #0 {
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; SSE-LABEL: f32_no_estimate:
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; SSE: # BB#0:
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; SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; SSE-NEXT: divss %xmm0, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: f32_no_estimate:
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; AVX: # BB#0:
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; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; AVX-NEXT: vdivss %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%div = fdiv fast float 1.0, %x
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ret float %div
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}
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define float @f32_one_step(float %x) #1 {
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; SSE-LABEL: f32_one_step:
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; SSE: # BB#0:
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; SSE-NEXT: rcpss %xmm0, %xmm2
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; SSE-NEXT: mulss %xmm2, %xmm0
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; SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; SSE-NEXT: subss %xmm0, %xmm1
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; SSE-NEXT: mulss %xmm2, %xmm1
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; SSE-NEXT: addss %xmm2, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: f32_one_step:
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; AVX: # BB#0:
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; AVX-NEXT: vrcpss %xmm0, %xmm0, %xmm1
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; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; AVX-NEXT: vsubss %xmm0, %xmm2, %xmm0
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; AVX-NEXT: vmulss %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vaddss %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%div = fdiv fast float 1.0, %x
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ret float %div
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}
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define float @f32_two_step(float %x) #2 {
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; SSE-LABEL: f32_two_step:
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; SSE: # BB#0:
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; SSE-NEXT: rcpss %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm0, %xmm3
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; SSE-NEXT: mulss %xmm2, %xmm3
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; SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; SSE-NEXT: movaps %xmm1, %xmm4
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; SSE-NEXT: subss %xmm3, %xmm4
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; SSE-NEXT: mulss %xmm2, %xmm4
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; SSE-NEXT: addss %xmm2, %xmm4
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; SSE-NEXT: mulss %xmm4, %xmm0
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; SSE-NEXT: subss %xmm0, %xmm1
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; SSE-NEXT: mulss %xmm4, %xmm1
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; SSE-NEXT: addss %xmm4, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: f32_two_step:
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; AVX: # BB#0:
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; AVX-NEXT: vrcpss %xmm0, %xmm0, %xmm1
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; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm2
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; AVX-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
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; AVX-NEXT: vsubss %xmm2, %xmm3, %xmm2
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; AVX-NEXT: vmulss %xmm2, %xmm1, %xmm2
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; AVX-NEXT: vaddss %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vsubss %xmm0, %xmm3, %xmm0
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; AVX-NEXT: vmulss %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vaddss %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%div = fdiv fast float 1.0, %x
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ret float %div
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}
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define <4 x float> @v4f32_no_estimate(<4 x float> %x) #0 {
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; SSE-LABEL: v4f32_no_estimate:
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; SSE: # BB#0:
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; SSE-NEXT: movaps {{.*#+}} xmm1 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00]
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; SSE-NEXT: divps %xmm0, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: v4f32_no_estimate:
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; AVX: # BB#0:
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; AVX-NEXT: vmovaps {{.*#+}} xmm1 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00]
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; AVX-NEXT: vdivps %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%div = fdiv fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %x
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ret <4 x float> %div
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}
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define <4 x float> @v4f32_one_step(<4 x float> %x) #1 {
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; SSE-LABEL: v4f32_one_step:
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; SSE: # BB#0:
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; SSE-NEXT: rcpps %xmm0, %xmm2
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; SSE-NEXT: mulps %xmm2, %xmm0
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; SSE-NEXT: movaps {{.*#+}} xmm1 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00]
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; SSE-NEXT: subps %xmm0, %xmm1
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; SSE-NEXT: mulps %xmm2, %xmm1
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; SSE-NEXT: addps %xmm2, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: v4f32_one_step:
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; AVX: # BB#0:
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; AVX-NEXT: vrcpps %xmm0, %xmm1
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; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vmovaps {{.*#+}} xmm2 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00]
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; AVX-NEXT: vsubps %xmm0, %xmm2, %xmm0
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; AVX-NEXT: vmulps %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vaddps %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%div = fdiv fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %x
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ret <4 x float> %div
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}
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define <4 x float> @v4f32_two_step(<4 x float> %x) #2 {
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; SSE-LABEL: v4f32_two_step:
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; SSE: # BB#0:
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; SSE-NEXT: rcpps %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm0, %xmm3
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; SSE-NEXT: mulps %xmm2, %xmm3
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; SSE-NEXT: movaps {{.*#+}} xmm1 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00]
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; SSE-NEXT: movaps %xmm1, %xmm4
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; SSE-NEXT: subps %xmm3, %xmm4
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; SSE-NEXT: mulps %xmm2, %xmm4
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; SSE-NEXT: addps %xmm2, %xmm4
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; SSE-NEXT: mulps %xmm4, %xmm0
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; SSE-NEXT: subps %xmm0, %xmm1
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; SSE-NEXT: mulps %xmm4, %xmm1
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; SSE-NEXT: addps %xmm4, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: v4f32_two_step:
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; AVX: # BB#0:
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; AVX-NEXT: vrcpps %xmm0, %xmm1
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; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm2
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; AVX-NEXT: vmovaps {{.*#+}} xmm3 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00]
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; AVX-NEXT: vsubps %xmm2, %xmm3, %xmm2
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; AVX-NEXT: vmulps %xmm2, %xmm1, %xmm2
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; AVX-NEXT: vaddps %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vsubps %xmm0, %xmm3, %xmm0
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; AVX-NEXT: vmulps %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vaddps %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%div = fdiv fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %x
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ret <4 x float> %div
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}
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define <8 x float> @v8f32_no_estimate(<8 x float> %x) #0 {
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; SSE-LABEL: v8f32_no_estimate:
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; SSE: # BB#0:
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; SSE-NEXT: movaps {{.*#+}} xmm2 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00]
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; SSE-NEXT: movaps %xmm2, %xmm3
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; SSE-NEXT: divps %xmm0, %xmm3
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; SSE-NEXT: divps %xmm1, %xmm2
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; SSE-NEXT: movaps %xmm3, %xmm0
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; SSE-NEXT: movaps %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: v8f32_no_estimate:
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; AVX: # BB#0:
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; AVX-NEXT: vmovaps {{.*#+}} ymm1 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00]
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; AVX-NEXT: vdivps %ymm0, %ymm1, %ymm0
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; AVX-NEXT: retq
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%div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %x
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ret <8 x float> %div
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}
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define <8 x float> @v8f32_one_step(<8 x float> %x) #1 {
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; SSE-LABEL: v8f32_one_step:
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; SSE: # BB#0:
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; SSE-NEXT: rcpps %xmm0, %xmm4
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; SSE-NEXT: mulps %xmm4, %xmm0
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; SSE-NEXT: movaps {{.*#+}} xmm2 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00]
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; SSE-NEXT: movaps %xmm2, %xmm3
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; SSE-NEXT: subps %xmm0, %xmm3
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; SSE-NEXT: mulps %xmm4, %xmm3
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; SSE-NEXT: addps %xmm4, %xmm3
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; SSE-NEXT: rcpps %xmm1, %xmm0
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; SSE-NEXT: mulps %xmm0, %xmm1
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; SSE-NEXT: subps %xmm1, %xmm2
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; SSE-NEXT: mulps %xmm0, %xmm2
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; SSE-NEXT: addps %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm3, %xmm0
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; SSE-NEXT: movaps %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: v8f32_one_step:
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; AVX: # BB#0:
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; AVX-NEXT: vrcpps %ymm0, %ymm1
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; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm0
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; AVX-NEXT: vmovaps {{.*#+}} ymm2 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00]
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; AVX-NEXT: vsubps %ymm0, %ymm2, %ymm0
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; AVX-NEXT: vmulps %ymm0, %ymm1, %ymm0
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; AVX-NEXT: vaddps %ymm0, %ymm1, %ymm0
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; AVX-NEXT: retq
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%div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %x
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ret <8 x float> %div
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}
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define <8 x float> @v8f32_two_step(<8 x float> %x) #2 {
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; SSE-LABEL: v8f32_two_step:
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; SSE: # BB#0:
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; SSE-NEXT: movaps %xmm1, %xmm2
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; SSE-NEXT: rcpps %xmm0, %xmm3
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; SSE-NEXT: movaps %xmm0, %xmm4
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; SSE-NEXT: mulps %xmm3, %xmm4
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; SSE-NEXT: movaps {{.*#+}} xmm1 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00]
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; SSE-NEXT: movaps %xmm1, %xmm5
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; SSE-NEXT: subps %xmm4, %xmm5
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; SSE-NEXT: mulps %xmm3, %xmm5
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; SSE-NEXT: addps %xmm3, %xmm5
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; SSE-NEXT: mulps %xmm5, %xmm0
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; SSE-NEXT: movaps %xmm1, %xmm3
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; SSE-NEXT: subps %xmm0, %xmm3
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; SSE-NEXT: mulps %xmm5, %xmm3
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; SSE-NEXT: addps %xmm5, %xmm3
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; SSE-NEXT: rcpps %xmm2, %xmm0
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; SSE-NEXT: movaps %xmm2, %xmm4
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; SSE-NEXT: mulps %xmm0, %xmm4
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; SSE-NEXT: movaps %xmm1, %xmm5
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; SSE-NEXT: subps %xmm4, %xmm5
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; SSE-NEXT: mulps %xmm0, %xmm5
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; SSE-NEXT: addps %xmm0, %xmm5
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; SSE-NEXT: mulps %xmm5, %xmm2
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; SSE-NEXT: subps %xmm2, %xmm1
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; SSE-NEXT: mulps %xmm5, %xmm1
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; SSE-NEXT: addps %xmm5, %xmm1
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; SSE-NEXT: movaps %xmm3, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: v8f32_two_step:
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; AVX: # BB#0:
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; AVX-NEXT: vrcpps %ymm0, %ymm1
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; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm2
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; AVX-NEXT: vmovaps {{.*#+}} ymm3 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00]
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; AVX-NEXT: vsubps %ymm2, %ymm3, %ymm2
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; AVX-NEXT: vmulps %ymm2, %ymm1, %ymm2
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; AVX-NEXT: vaddps %ymm2, %ymm1, %ymm1
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; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm0
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; AVX-NEXT: vsubps %ymm0, %ymm3, %ymm0
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; AVX-NEXT: vmulps %ymm0, %ymm1, %ymm0
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; AVX-NEXT: vaddps %ymm0, %ymm1, %ymm0
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; AVX-NEXT: retq
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%div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %x
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ret <8 x float> %div
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}
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attributes #0 = { "unsafe-fp-math"="true" "reciprocal-estimates"="!divf,!vec-divf" }
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attributes #1 = { "unsafe-fp-math"="true" "reciprocal-estimates"="divf,vec-divf" }
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attributes #2 = { "unsafe-fp-math"="true" "reciprocal-estimates"="divf:2,vec-divf:2" }
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