forked from OSchip/llvm-project
363 lines
10 KiB
LLVM
363 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefixes=CHECK,SSE2
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 < %s | FileCheck %s --check-prefixes=CHECK,SSE41
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define i32 @test_eq_1(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test_eq_1:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pcmpgtd %xmm0, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,2,3]
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; SSE2-NEXT: movd %xmm0, %eax
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; SSE2-NEXT: notl %eax
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test_eq_1:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pcmpgtd %xmm0, %xmm1
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; SSE41-NEXT: pextrd $1, %xmm1, %eax
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; SSE41-NEXT: notl %eax
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; SSE41-NEXT: retq
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%cmp = icmp slt <4 x i32> %A, %B
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp eq <4 x i32> %sext, zeroinitializer
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%t0 = extractelement <4 x i1> %cmp1, i32 1
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%t1 = sext i1 %t0 to i32
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ret i32 %t1
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}
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define i32 @test_ne_1(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test_ne_1:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pcmpgtd %xmm0, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,2,3]
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; SSE2-NEXT: movd %xmm0, %eax
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test_ne_1:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pcmpgtd %xmm0, %xmm1
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; SSE41-NEXT: pextrd $1, %xmm1, %eax
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; SSE41-NEXT: retq
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%cmp = icmp slt <4 x i32> %A, %B
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp ne <4 x i32> %sext, zeroinitializer
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%t0 = extractelement <4 x i1> %cmp1, i32 1
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%t1 = sext i1 %t0 to i32
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ret i32 %t1
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}
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define i32 @test_le_1(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test_le_1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: retq
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%cmp = icmp slt <4 x i32> %A, %B
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp sle <4 x i32> %sext, zeroinitializer
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%t0 = extractelement <4 x i1> %cmp1, i32 1
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%t1 = sext i1 %t0 to i32
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ret i32 %t1
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}
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define i32 @test_ge_1(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test_ge_1:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pcmpgtd %xmm0, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,2,3]
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; SSE2-NEXT: movd %xmm0, %eax
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; SSE2-NEXT: notl %eax
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test_ge_1:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pcmpgtd %xmm0, %xmm1
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; SSE41-NEXT: pextrd $1, %xmm1, %eax
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; SSE41-NEXT: notl %eax
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; SSE41-NEXT: retq
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%cmp = icmp slt <4 x i32> %A, %B
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp sge <4 x i32> %sext, zeroinitializer
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%t0 = extractelement <4 x i1> %cmp1, i32 1
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%t1 = sext i1 %t0 to i32
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ret i32 %t1
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}
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define i32 @test_lt_1(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test_lt_1:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pcmpgtd %xmm0, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,2,3]
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; SSE2-NEXT: movd %xmm0, %eax
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test_lt_1:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pcmpgtd %xmm0, %xmm1
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; SSE41-NEXT: pextrd $1, %xmm1, %eax
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; SSE41-NEXT: retq
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%cmp = icmp slt <4 x i32> %A, %B
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp slt <4 x i32> %sext, zeroinitializer
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%t0 = extractelement <4 x i1> %cmp, i32 1
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%t1 = sext i1 %t0 to i32
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ret i32 %t1
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}
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define i32 @test_gt_1(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test_gt_1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%cmp = icmp slt <4 x i32> %A, %B
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp sgt <4 x i32> %sext, zeroinitializer
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%t0 = extractelement <4 x i1> %cmp1, i32 1
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%t1 = sext i1 %t0 to i32
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ret i32 %t1
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}
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define i32 @test_eq_2(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test_eq_2:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; SSE2-NEXT: movd %xmm0, %eax
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; SSE2-NEXT: notl %eax
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test_eq_2:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pcmpgtd %xmm1, %xmm0
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; SSE41-NEXT: pextrd $1, %xmm0, %eax
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; SSE41-NEXT: notl %eax
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; SSE41-NEXT: retq
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%cmp = icmp slt <4 x i32> %B, %A
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp eq <4 x i32> %sext, zeroinitializer
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%t0 = extractelement <4 x i1> %cmp1, i32 1
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%t1 = sext i1 %t0 to i32
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ret i32 %t1
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}
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define i32 @test_ne_2(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test_ne_2:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; SSE2-NEXT: movd %xmm0, %eax
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test_ne_2:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pcmpgtd %xmm1, %xmm0
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; SSE41-NEXT: pextrd $1, %xmm0, %eax
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; SSE41-NEXT: retq
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%cmp = icmp slt <4 x i32> %B, %A
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp ne <4 x i32> %sext, zeroinitializer
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%t0 = extractelement <4 x i1> %cmp1, i32 1
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%t1 = sext i1 %t0 to i32
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ret i32 %t1
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}
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define i32 @test_le_2(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test_le_2:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; SSE2-NEXT: movd %xmm0, %eax
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; SSE2-NEXT: notl %eax
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test_le_2:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pcmpgtd %xmm1, %xmm0
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; SSE41-NEXT: pextrd $1, %xmm0, %eax
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; SSE41-NEXT: notl %eax
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; SSE41-NEXT: retq
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%cmp = icmp slt <4 x i32> %B, %A
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp sle <4 x i32> zeroinitializer, %sext
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%t0 = extractelement <4 x i1> %cmp1, i32 1
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%t1 = sext i1 %t0 to i32
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ret i32 %t1
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}
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define i32 @test_ge_2(<4 x i32> %A, <4 x i32> %B) {
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; CHECK-LABEL: test_ge_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: retq
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%cmp = icmp slt <4 x i32> %B, %A
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp sge <4 x i32> zeroinitializer, %sext
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%t0 = extractelement <4 x i1> %cmp1, i32 1
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%t1 = sext i1 %t0 to i32
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ret i32 %t1
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}
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define i32 @test_lt_2(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test_lt_2:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; SSE2-NEXT: movd %xmm0, %eax
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test_lt_2:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pcmpgtd %xmm1, %xmm0
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; SSE41-NEXT: pextrd $1, %xmm0, %eax
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; SSE41-NEXT: retq
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%cmp = icmp slt <4 x i32> %B, %A
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp slt <4 x i32> zeroinitializer, %sext
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%t0 = extractelement <4 x i1> %cmp, i32 1
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%t1 = sext i1 %t0 to i32
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ret i32 %t1
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}
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define i32 @test_gt_2(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test_gt_2:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; SSE2-NEXT: movd %xmm0, %eax
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test_gt_2:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pcmpgtd %xmm1, %xmm0
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; SSE41-NEXT: pextrd $1, %xmm0, %eax
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; SSE41-NEXT: retq
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%cmp = icmp slt <4 x i32> %B, %A
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%cmp1 = icmp sgt <4 x i32> zeroinitializer, %sext
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%t0 = extractelement <4 x i1> %cmp1, i32 1
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%t1 = sext i1 %t0 to i32
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ret i32 %t1
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}
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; (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2)
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; Don't combine with i1 - out of range constant
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define void @test_i1_uge(i1 *%A2) {
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; CHECK-LABEL: test_i1_uge:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movb (%rdi), %al
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: xorb $1, %cl
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; CHECK-NEXT: andb %cl, %al
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: andl $1, %eax
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; CHECK-NEXT: negq %rax
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; CHECK-NEXT: andb $1, %cl
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; CHECK-NEXT: movb %cl, (%rdi,%rax)
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; CHECK-NEXT: retq
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%L5 = load i1, i1* %A2
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%C3 = icmp ne i1 %L5, true
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%C8 = icmp eq i1 %L5, false
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%C9 = icmp ugt i1 %C3, %C8
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%G3 = getelementptr i1, i1* %A2, i1 %C9
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store i1 %C3, i1* %G3
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ret void
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}
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; This should not get folded to 0.
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define i64 @PR40657(i8 %var2, i8 %var9) {
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; CHECK-LABEL: PR40657:
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; CHECK: # %bb.0:
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; CHECK-NEXT: notb %sil
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; CHECK-NEXT: addb %dil, %sil
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; CHECK-NEXT: movzbl %sil, %eax
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; CHECK-NEXT: andl $1, %eax
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; CHECK-NEXT: retq
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%var6 = trunc i8 %var9 to i1
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%var7 = trunc i8 175 to i1
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%var3 = sub nsw i1 %var6, %var7
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%var4 = icmp eq i64 1114591064, 1114591064
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%var1 = udiv i1 %var3, %var4
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%var0 = trunc i8 %var2 to i1
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%res = sub nsw nuw i1 %var0, %var1
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%res.cast = zext i1 %res to i64
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ret i64 %res.cast
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}
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; This should not get folded to 0.
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define i64 @PR40657_commute(i8 %var7, i8 %var8, i8 %var9) {
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; CHECK-LABEL: PR40657_commute:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subb %dil, %sil
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; CHECK-NEXT: subb %sil, %dl
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; CHECK-NEXT: subb %dl, %sil
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; CHECK-NEXT: xorb %dl, %sil
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; CHECK-NEXT: subb %sil, %dl
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; CHECK-NEXT: movzbl %dl, %eax
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; CHECK-NEXT: andl $1, %eax
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; CHECK-NEXT: retq
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%var4 = trunc i8 %var9 to i1
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%var5 = trunc i8 %var8 to i1
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%var6 = trunc i8 %var7 to i1
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%var3 = sub nsw nuw i1 %var5, %var6
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%var0 = sub nuw i1 %var4, %var3
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%var2 = sub i1 %var3, %var0
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%var1 = icmp ne i1 %var0, %var2
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%res = sub nsw nuw i1 %var0, %var1
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%res.cast = zext i1 %res to i64
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ret i64 %res.cast
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}
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define i64 @sub_to_shift_to_add(i32 %x, i32 %y, i64 %s1, i64 %s2) {
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; CHECK-LABEL: sub_to_shift_to_add:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdx, %rax
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; CHECK-NEXT: addl %esi, %esi
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; CHECK-NEXT: cmpl %esi, %edi
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; CHECK-NEXT: cmovneq %rcx, %rax
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; CHECK-NEXT: retq
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%sub = sub i32 %x, %y
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%cmp = icmp eq i32 %sub, %y
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%r = select i1 %cmp, i64 %s1, i64 %s2
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ret i64 %r
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}
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define <4 x float> @sub_to_shift_to_add_vec(<4 x i32> %x, <4 x i32> %y, <4 x float> %s1, <4 x float> %s2) {
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; SSE2-LABEL: sub_to_shift_to_add_vec:
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; SSE2: # %bb.0:
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; SSE2-NEXT: paddd %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
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; SSE2-NEXT: pand %xmm1, %xmm2
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; SSE2-NEXT: pandn %xmm3, %xmm1
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; SSE2-NEXT: por %xmm2, %xmm1
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; SSE2-NEXT: movdqa %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: sub_to_shift_to_add_vec:
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; SSE41: # %bb.0:
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; SSE41-NEXT: paddd %xmm1, %xmm1
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; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
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; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm3
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; SSE41-NEXT: movaps %xmm3, %xmm0
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; SSE41-NEXT: retq
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%sub = sub <4 x i32> %x, %y
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%cmp = icmp eq <4 x i32> %sub, %y
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%r = select <4 x i1> %cmp, <4 x float> %s1, <4 x float> %s2
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ret <4 x float> %r
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}
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define i64 @sub_constant_to_shift_to_add(i32 %x, i64 %s1, i64 %s2) {
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; CHECK-LABEL: sub_constant_to_shift_to_add:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: addl %edi, %edi
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; CHECK-NEXT: cmpl $42, %edi
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; CHECK-NEXT: cmovneq %rdx, %rax
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; CHECK-NEXT: retq
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%sub = sub i32 42, %x
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%cmp = icmp eq i32 %sub, %x
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%r = select i1 %cmp, i64 %s1, i64 %s2
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ret i64 %r
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}
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