forked from OSchip/llvm-project
57 lines
2.0 KiB
LLVM
57 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -verify-coalescing -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -verify-coalescing -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -verify-coalescing -mattr=+avx | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -verify-coalescing -mattr=+avx512f | FileCheck %s --check-prefix=AVX512
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; PR30607
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define <2 x double> @insert_f64(double %a0, <2 x double> %a1) {
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; SSE2-LABEL: insert_f64:
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; SSE2: # %bb.0:
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: insert_f64:
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; SSE41: # %bb.0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: insert_f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX-NEXT: retq
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;
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; AVX512-LABEL: insert_f64:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX512-NEXT: retq
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%1 = insertelement <2 x double> %a1, double %a0, i32 0
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ret <2 x double> %1
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}
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define <4 x float> @insert_f32(float %a0, <4 x float> %a1) {
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; SSE2-LABEL: insert_f32:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: insert_f32:
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; SSE41: # %bb.0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: insert_f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; AVX-NEXT: retq
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;
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; AVX512-LABEL: insert_f32:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; AVX512-NEXT: retq
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%1 = insertelement <4 x float> %a1, float %a0, i32 0
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ret <4 x float> %1
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}
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