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GC
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[lit] Delete empty lines at the end of lit.local.cfg NFC
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2019-06-17 09:51:07 +00:00 |
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GlobalISel
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[GlobalISel] Import patterns containing SUBREG_TO_REG
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2019-08-28 20:12:31 +00:00 |
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avx512-shuffles
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[X86] Teach lowerV4I32Shuffle to only use broadcasts if the mask has more than one undef element. Prioritize shifts over broadcast in lowerV8I16Shuffle.
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2019-08-19 18:15:50 +00:00 |
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3addr-16bit.ll
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3addr-or.ll
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3dnow-intrinsics.ll
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[X86] Add custom type legalization for bitcasting mmx to v2i32/v4i16/v8i8 to use movq2dq instead of going through memory.
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2019-08-15 18:23:37 +00:00 |
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4char-promote.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
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2019-08-07 16:24:26 +00:00 |
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8bit_cmov_of_trunc_promotion.ll
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2003-08-03-CallArgLiveRanges.ll
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2003-08-23-DeadBlockTest.ll
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2003-11-03-GlobalBool.ll
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2004-02-13-FrameReturnAddress.ll
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2004-02-14-InefficientStackPointer.ll
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2004-02-22-Casts.ll
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2004-03-30-Select-Max.ll
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2004-04-13-FPCMOV-Crash.ll
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2004-06-10-StackifierCrash.ll
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2004-10-08-SelectSetCCFold.ll
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2005-01-17-CycleInDAG.ll
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2005-02-14-IllegalAssembler.ll
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2005-05-08-FPStackifierPHI.ll
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2006-01-19-ISelFoldingBug.ll
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2006-03-01-InstrSchedBug.ll
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2006-03-02-InstrSchedBug.ll
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2006-04-04-CrossBlockCrash.ll
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2006-04-27-ISelFoldingBug.ll
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2006-05-01-SchedCausingSpills.ll
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2006-05-02-InstrSched1.ll
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2006-05-02-InstrSched2.ll
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2006-05-08-CoalesceSubRegClass.ll
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2006-05-08-InstrSched.ll
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2006-05-11-InstrSched.ll
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2006-05-17-VectorArg.ll
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2006-05-22-FPSetEQ.ll
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2006-05-25-CycleInDAG.ll
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2006-07-10-InlineAsmAConstraint.ll
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2006-07-12-InlineAsmQConstraint.ll
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2006-07-20-InlineAsm.ll
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2006-07-28-AsmPrint-Long-As-Pointer.ll
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2006-07-31-SingleRegClass.ll
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2006-08-07-CycleInDAG.ll
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2006-08-16-CycleInDAG.ll
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2006-08-21-ExtraMovInst.ll
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2006-09-01-CycleInDAG.ll
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2006-10-02-BoolRetCrash.ll
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2006-10-09-CycleInDAG.ll
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2006-10-10-FindModifiedNodeSlotBug.ll
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2006-10-12-CycleInDAG.ll
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2006-10-13-CycleInDAG.ll
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2006-10-19-SwitchUnnecessaryBranching.ll
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2006-11-12-CSRetCC.ll
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2006-11-17-IllegalMove.ll
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2006-11-27-SelectLegalize.ll
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2006-12-16-InlineAsmCrash.ll
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2006-12-19-IntelSyntax.ll
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2007-01-08-InstrSched.ll
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2007-01-08-X86-64-Pointer.ll
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2007-01-13-StackPtrIndex.ll
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2007-01-29-InlineAsm-ir.ll
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2007-02-04-OrAddrMode.ll
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2007-02-16-BranchFold.ll
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2007-02-19-LiveIntervalAssert.ll
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2007-02-23-DAGCombine-Miscompile.ll
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2007-02-25-FastCCStack.ll
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2007-03-01-SpillerCrash.ll
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2007-03-15-GEP-Idx-Sink.ll
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2007-03-16-InlineAsm.ll
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2007-03-18-LiveIntervalAssert.ll
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2007-03-24-InlineAsmMultiRegConstraint.ll
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2007-03-24-InlineAsmPModifier.ll
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2007-03-24-InlineAsmVectorOp.ll
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2007-03-24-InlineAsmXConstraint.ll
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2007-03-26-CoalescerBug.ll
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2007-04-08-InlineAsmCrash.ll
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2007-04-11-InlineAsmVectorResult.ll
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2007-04-17-LiveIntervalAssert.ll
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2007-04-24-Huge-Stack.ll
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2007-04-24-VectorCrash.ll
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2007-04-27-InlineAsm-IntMemInput.ll
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2007-05-05-Personality.ll
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2007-05-05-VecCastExpand.ll
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2007-05-14-LiveIntervalAssert.ll
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2007-05-15-maskmovq.ll
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2007-05-17-ShuffleISelBug.ll
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2007-06-04-X86-64-CtorAsmBugs.ll
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[IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format
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2019-05-15 02:35:32 +00:00 |
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2007-06-28-X86-64-isel.ll
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2007-06-29-DAGCombinerBug.ll
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2007-06-29-VecFPConstantCSEBug.ll
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2007-07-03-GR64ToVR64.ll
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2007-07-10-StackerAssert.ll
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2007-07-18-Vector-Extract.ll
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2007-08-01-LiveVariablesBug.ll
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2007-08-09-IllegalX86-64Asm.ll
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2007-08-10-SignExtSubreg.ll
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2007-09-05-InvalidAsm.ll
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2007-09-06-ExtWeakAliasee.ll
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2007-09-27-LDIntrinsics.ll
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2007-10-04-AvoidEFLAGSCopy.ll
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2007-10-12-CoalesceExtSubReg.ll
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2007-10-12-SpillerUnfold1.ll
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2007-10-12-SpillerUnfold2.ll
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2007-10-14-CoalescerCrash.ll
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2007-10-15-CoalescerCrash.ll
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2007-10-16-CoalescerCrash.ll
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2007-10-19-SpillerUnfold.ll
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2007-10-28-inlineasm-q-modifier.ll
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2007-10-29-ExtendSetCC.ll
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2007-10-30-LSRCrash.ll
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2007-10-31-extractelement-i64.ll
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2007-11-01-ISelCrash.ll
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2007-11-03-x86-64-q-constraint.ll
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2007-11-04-LiveIntervalCrash.ll
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2007-11-04-LiveVariablesBug.ll
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2007-11-04-rip-immediate-constant.ll
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2007-11-06-InstrSched.ll
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2007-11-07-MulBy4.ll
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2007-11-30-LoadFolding-Bug.ll
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2007-12-16-BURRSchedCrash.ll
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2007-12-18-LoadCSEBug.ll
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2008-01-08-IllegalCMP.ll
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2008-01-08-SchedulerCrash.ll
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2008-01-09-LongDoubleSin.ll
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2008-01-16-FPStackifierAssert.ll
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2008-01-16-InvalidDAGCombineXform.ll
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2008-02-05-ISelCrash.ll
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2008-02-06-LoadFoldingBug.ll
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2008-02-14-BitMiscompile.ll
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2008-02-18-TailMergingBug.ll
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2008-02-20-InlineAsmClobber.ll
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2008-02-22-LocalRegAllocBug.ll
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2008-02-25-InlineAsmBug.ll
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2008-02-25-X86-64-CoalescerBug.ll
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2008-02-26-AsmDirectMemOp.ll
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2008-02-27-DeadSlotElimBug.ll
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2008-02-27-PEICrash.ll
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2008-03-06-frem-fpstack.ll
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2008-03-07-APIntBug.ll
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2008-03-10-RegAllocInfLoop.ll
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2008-03-12-ThreadLocalAlias.ll
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2008-03-13-TwoAddrPassCrash.ll
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2008-03-14-SpillerCrash.ll
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2008-03-19-DAGCombinerBug.ll
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2008-03-23-DarwinAsmComments.ll
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2008-03-25-TwoAddrPassBug.ll
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2008-03-31-SpillerFoldingBug.ll
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2008-04-02-unnamedEH.ll
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2008-04-08-CoalescerCrash.ll
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2008-04-09-BranchFolding.ll
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2008-04-15-LiveVariableBug.ll
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2008-04-16-CoalescerBug.ll
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2008-04-16-ReMatBug.ll
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2008-04-17-CoalescerBug.ll
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2008-04-24-MemCpyBug.ll
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2008-04-24-pblendw-fold-crash.ll
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2008-04-26-Asm-Optimize-Imm.ll
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2008-04-28-CoalescerBug.ll
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2008-04-28-CyclicSchedUnit.ll
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2008-05-01-InvalidOrdCompare.ll
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2008-05-09-PHIElimBug.ll
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2008-05-09-ShuffleLoweringBug.ll
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2008-05-12-tailmerge-5.ll
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2008-05-21-CoalescerBug.ll
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2008-05-22-FoldUnalignedLoad.ll
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2008-05-28-CoalescerBug.ll
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2008-05-28-LocalRegAllocBug.ll
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2008-06-13-NotVolatileLoadStore.ll
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2008-06-13-VolatileLoadStore.ll
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2008-06-16-SubregsBug.ll
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2008-06-25-VecISelBug.ll
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2008-07-07-DanglingDeadInsts.ll
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2008-07-09-ELFSectionAttributes.ll
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2008-07-11-SHLBy1.ll
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2008-07-16-CoalescerCrash.ll
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2008-07-19-movups-spills.ll
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2008-07-22-CombinerCrash.ll
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2008-07-23-VSetCC.ll
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2008-08-06-CmpStride.ll
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2008-08-06-RewriterBug.ll
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2008-08-17-UComiCodeGenBug.ll
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2008-08-23-64Bit-maskmovq.ll
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2008-08-31-EH_RETURN32.ll
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2008-08-31-EH_RETURN64.ll
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2008-09-05-sinttofp-2xi32.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
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2019-08-07 16:24:26 +00:00 |
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2008-09-09-LinearScanBug.ll
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2008-09-11-CoalescerBug.ll
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2008-09-11-CoalescerBug2.ll
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2008-09-17-inline-asm-1.ll
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2008-09-18-inline-asm-2.ll
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2008-09-19-RegAllocBug.ll
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2008-09-25-sseregparm-1.ll
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2008-09-26-FrameAddrBug.ll
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2008-09-29-ReMatBug.ll
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2008-09-29-VolatileBug.ll
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[X86] Prevent folding a load into an AND if that AND is really a ZEXT_INREG that should use movzx.
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2019-04-24 19:28:38 +00:00 |
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2008-10-06-x87ld-nan-1.ll
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2008-10-06-x87ld-nan-2.ll
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2008-10-07-SSEISelBug.ll
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2008-10-11-CallCrash.ll
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2008-10-13-CoalescerBug.ll
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2008-10-16-VecUnaryOp.ll
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2008-10-17-Asm64bitRConstraint.ll
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2008-10-20-AsmDoubleInI32.ll
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2008-10-24-FlippedCompare.ll
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2008-10-27-CoalescerBug.ll
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2008-10-29-ExpandVAARG.ll
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2008-11-03-F80VAARG.ll
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2008-11-06-testb.ll
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2008-11-13-inlineasm-3.ll
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2008-11-29-ULT-Sign.ll
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2008-12-01-SpillerAssert.ll
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2008-12-01-loop-iv-used-outside-loop.ll
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2008-12-02-IllegalResultType.ll
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2008-12-02-dagcombine-1.ll
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2008-12-02-dagcombine-2.ll
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2008-12-02-dagcombine-3.ll
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2008-12-16-dagcombine-4.ll
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2008-12-19-EarlyClobberBug.ll
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2008-12-22-dagcombine-5.ll
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2008-12-23-crazy-address.ll
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2008-12-23-dagcombine-6.ll
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2009-01-13-DoubleUpdate.ll
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2009-01-16-SchedulerBug.ll
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2009-01-16-UIntToFP.ll
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2009-01-18-ConstantExprCrash.ll
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2009-01-25-NoSSE.ll
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2009-01-26-WrongCheck.ll
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2009-01-27-NullStrings.ll
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2009-01-31-BigShift.ll
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2009-01-31-BigShift2.ll
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2009-01-31-BigShift3.ll
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2009-02-01-LargeMask.ll
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2009-02-03-AnalyzedTwice.ll
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2009-02-04-sext-i64-gep.ll
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2009-02-08-CoalescerBug.ll
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2009-02-09-ivs-different-sizes.ll
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2009-02-11-codegenprepare-reuse.ll
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2009-02-12-DebugInfoVLA.ll
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2009-02-12-InlineAsm-nieZ-constraints.ll
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2009-02-12-SpillerBug.ll
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2009-02-21-ExtWeakInitializer.ll
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2009-02-25-CommuteBug.ll
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2009-02-26-MachineLICMBug.ll
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[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
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2019-05-06 21:39:51 +00:00 |
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2009-03-03-BTHang.ll
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2009-03-03-BitcastLongDouble.ll
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2009-03-05-burr-list-crash.ll
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2009-03-09-APIntCrash.ll
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2009-03-09-SpillerBug.ll
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2009-03-10-CoalescerBug.ll
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2009-03-12-CPAlignBug.ll
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2009-03-13-PHIElimBug.ll
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2009-03-16-PHIElimInLPad.ll
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2009-03-23-LinearScanBug.ll
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2009-03-23-MultiUseSched.ll
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2009-03-23-i80-fp80.ll
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2009-03-25-TestBug.ll
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2009-03-26-NoImplicitFPBug.ll
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2009-04-12-FastIselOverflowCrash.ll
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2009-04-12-picrel.ll
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2009-04-13-2AddrAssert-2.ll
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2009-04-13-2AddrAssert.ll
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2009-04-14-IllegalRegs.ll
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2009-04-16-SpillerUnfold.ll
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2009-04-24.ll
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2009-04-25-CoalescerBug.ll
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2009-04-27-CoalescerAssert.ll
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2009-04-27-LiveIntervalsAssert.ll
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2009-04-27-LiveIntervalsAssert2.ll
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2009-04-29-IndirectDestOperands.ll
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2009-04-29-LinearScanBug.ll
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2009-04-29-RegAllocAssert.ll
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2009-05-23-available_externally.ll
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2009-05-28-DAGCombineCrash.ll
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2009-05-30-ISelBug.ll
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2009-06-02-RewriterBug.ll
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2009-06-03-Win64DisableRedZone.ll
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2009-06-04-VirtualLiveIn.ll
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2009-06-05-VZextByteShort.ll
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2009-06-05-VariableIndexInsert.ll
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2009-06-05-sitofpCrash.ll
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2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll
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2009-06-15-not-a-tail-call.ll
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2009-06-18-movlp-shuffle-register.ll
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2009-07-06-TwoAddrAssert.ll
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2009-07-07-SplitICmp.ll
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2009-07-09-ExtractBoolFromVector.ll
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2009-07-15-CoalescerBug.ll
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2009-07-16-CoalescerBug.ll
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2009-07-19-AsmExtraOperands.ll
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2009-07-20-CoalescerBug.ll
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2009-07-20-DAGCombineBug.ll
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2009-08-06-branchfolder-crash.ll
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2009-08-06-inlineasm.ll
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2009-08-08-CastError.ll
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2009-08-12-badswitch.ll
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2009-08-14-Win64MemoryIndirectArg.ll
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2009-08-19-LoadNarrowingMiscompile.ll
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2009-08-23-SubRegReuseUndo.ll
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2009-09-10-LoadFoldingBug.ll
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2009-09-10-SpillComments.ll
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2009-09-16-CoalescerBug.ll
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2009-09-19-earlyclobber.ll
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2009-09-21-NoSpillLoopCount.ll
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2009-09-22-CoalescerBug.ll
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2009-09-23-LiveVariablesBug.ll
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2009-10-14-LiveVariablesBug.ll
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2009-10-16-Scope.ll
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2009-10-19-EmergencySpill.ll
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2009-10-19-atomic-cmp-eflags.ll
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2009-10-25-RewriterBug.ll
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2009-11-04-SubregCoalescingBug.ll
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2009-11-13-VirtRegRewriterBug.ll
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2009-11-16-MachineLICM.ll
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2009-11-16-UnfoldMemOpBug.ll
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2009-11-17-UpdateTerminator.ll
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2009-11-18-TwoAddrKill.ll
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2009-11-25-ImpDefBug.ll
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2009-12-01-EarlyClobberBug.ll
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2009-12-11-TLSNoRedZone.ll
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2010-01-05-ZExt-Shl.ll
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2010-01-07-ISelBug.ll
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2010-01-08-Atomic64Bug.ll
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2010-01-11-ExtraPHIArg.ll
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2010-01-13-OptExtBug.ll
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2010-01-15-SelectionDAGCycle.ll
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2010-01-18-DbgValue.ll
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2010-01-19-OptExtBug.ll
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2010-02-01-DbgValueCrash.ll
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2010-02-01-TaillCallCrash.ll
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2010-02-03-DualUndef.ll
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2010-02-04-SchedulerBug.ll
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2010-02-11-NonTemporal.ll
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2010-02-12-CoalescerBug-Impdef.ll
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2010-02-15-ImplicitDefBug.ll
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2010-02-19-TailCallRetAddrBug.ll
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2010-02-23-DAGCombineBug.ll
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2010-02-23-DIV8rDefinesAX.ll
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2010-02-23-RematImplicitSubreg.ll
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2010-02-23-SingleDefPhiJoin.ll
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2010-03-04-Mul8Bug.ll
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2010-03-05-ConstantFoldCFG.ll
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2010-03-05-EFLAGS-Redef.ll
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2010-03-17-ISelBug.ll
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2010-04-06-SSEDomainFixCrash.ll
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2010-04-08-CoalescerBug.ll
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2010-04-13-AnalyzeBranchCrash.ll
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2010-04-21-CoalescerBug.ll
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2010-04-29-CoalescerCrash.ll
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2010-04-30-LocalAlloc-LandingPad.ll
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2010-05-03-CoalescerSubRegClobber.ll
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2010-05-05-LocalAllocEarlyClobber.ll
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2010-05-06-LocalInlineAsmClobber.ll
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2010-05-07-ldconvert.ll
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2010-05-10-DAGCombinerBug.ll
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2010-05-12-FastAllocKills.ll
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2010-05-16-nosseconversion.ll
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2010-05-25-DotDebugLoc.ll
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2010-05-26-DotDebugLoc.ll
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2010-05-26-FP_TO_INT-crash.ll
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2010-05-28-Crash.ll
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2010-06-01-DeadArg-DbgInfo.ll
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2010-06-09-FastAllocRegisters.ll
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2010-06-14-fast-isel-fs-load.ll
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2010-06-15-FastAllocEarlyCLobber.ll
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2010-06-24-g-constraint-crash.ll
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2010-06-25-CoalescerSubRegDefDead.ll
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2010-06-25-asm-RA-crash.ll
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2010-06-28-FastAllocTiedOperand.ll
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2010-06-28-matched-g-constraint.ll
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2010-07-02-UnfoldBug.ll
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2010-07-02-asm-alignstack.ll
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2010-07-06-DbgCrash.ll
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2010-07-06-asm-RIP.ll
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2010-07-11-FPStackLoneUse.ll
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2010-07-13-indirectXconstraint.ll
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2010-07-15-Crash.ll
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2010-07-29-SetccSimplify.ll
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2010-08-04-MaskedSignedCompare.ll
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2010-08-04-MingWCrash.ll
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2010-08-04-StackVariable.ll
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2010-09-01-RemoveCopyByCommutingDef.ll
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2010-09-16-EmptyFilename.ll
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2010-09-16-asmcrash.ll
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2010-09-17-SideEffectsInChain.ll
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2010-09-30-CMOV-JumpTable-PHI.ll
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2010-10-08-cmpxchg8b.ll
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2010-11-02-DbgParameter.ll
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2010-11-09-MOVLPS.ll
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2010-11-18-SelectOfExtload.ll
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2011-01-07-LegalizeTypesCrash.ll
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2011-01-10-DagCombineHang.ll
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2011-01-24-DbgValue-Before-Use.ll
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2011-02-04-FastRegallocNoFP.ll
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2011-02-12-shuffle.ll
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2011-02-21-VirtRegRewriter-KillSubReg.ll
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2011-02-23-UnfoldBug.ll
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2011-02-27-Fpextend.ll
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2011-03-02-DAGCombiner.ll
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2011-03-08-Sched-crash.ll
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2011-03-09-Physreg-Coalescing.ll
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2011-03-30-CreateFixedObjCrash.ll
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2011-04-13-SchedCmpJmp.ll
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2011-04-19-sclr-bb.ll
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2011-05-09-loaduse.ll
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[X86][SSE] Add x64 load use test case
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2011-05-26-UnreachableBlockElim.ll
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2011-05-27-CrossClassCoalescing.ll
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2011-06-01-fildll.ll
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2011-06-03-x87chain.ll
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2011-06-06-fgetsign80bit.ll
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2011-06-12-FastAllocSpill.ll
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2011-06-14-PreschedRegalias.ll
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2011-06-14-mmx-inlineasm.ll
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2011-06-19-QuicksortCoalescerBug.ll
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2011-07-13-BadFrameIndexDisplacement.ll
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2011-08-23-PerformSubCombine128.ll
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2011-08-23-Trampoline.ll
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2011-08-29-BlockConstant.ll
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2011-08-29-InitOrder.ll
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[IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format
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2011-09-14-valcoalesce.ll
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2011-09-18-sse2cmp.ll
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2011-09-21-setcc-bug.ll
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2011-10-11-SpillDead.ll
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2011-10-11-srl.ll
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2011-10-12-MachineCSE.ll
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2011-10-18-FastISel-VectorParams.ll
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2011-10-19-LegelizeLoad.ll
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2011-10-19-widen_vselect.ll
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2011-10-21-widen-cmp.ll
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2011-10-30-padd.ll
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2011-11-07-LegalizeBuildVector.ll
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2011-11-22-AVX2-Domains.ll
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2011-11-30-or.ll
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2011-12-06-AVXVectorExtractCombine.ll
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2011-12-06-BitcastVectorGlobal.ll
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2011-12-08-AVXISelBugs.ll
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2011-12-8-bitcastintprom.ll
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2011-12-15-vec_shift.ll
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2011-12-28-vselecti8.ll
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2011-20-21-zext-ui2fp.ll
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2012-01-10-UndefExceptionEdge.ll
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2012-1-10-buildvector.ll
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2012-01-11-split-cv.ll
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2012-01-12-extract-sv.ll
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2012-01-18-vbitcast.ll
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2012-02-12-dagco.ll
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2012-02-14-scalar.ll
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2012-03-15-build_vector_wl.ll
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2012-03-20-LargeConstantExpr.ll
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2012-03-26-PostRALICMBug.ll
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2012-04-09-TwoAddrPassBug.ll
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2012-04-26-sdglue.ll
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2012-05-17-TwoAddressBug.ll
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2012-07-10-extload64.ll
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2012-07-10-shufnorm.ll
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2012-07-15-BuildVectorPromote.ll
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2012-07-15-broadcastfold.ll
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2012-07-15-tconst_shl.ll
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2012-07-15-vshl.ll
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2012-07-16-LeaUndef.ll
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2012-07-17-vtrunc.ll
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2012-07-23-select_cc.ll
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2012-08-07-CmpISelBug.ll
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2012-08-16-setcc.ll
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2012-08-28-UnsafeMathCrash.ll
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2012-09-13-dagco-fneg.ll
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2012-09-28-CGPBug.ll
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2012-10-02-DAGCycle.ll
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2012-10-03-DAGCycle.ll
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2012-10-18-crash-dagco.ll
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2012-11-28-merge-store-alias.ll
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2012-12-1-merge-multiple.ll
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2012-12-12-DAGCombineCrash.ll
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2012-12-14-v8fp80-crash.ll
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2012-12-19-NoImplicitFloat.ll
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2013-01-09-DAGCombineBug.ll
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2013-03-13-VEX-DestReg.ll
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2013-05-06-ConactVectorCrash.ll
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2013-10-14-FastISel-incorrect-vreg.ll
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2014-05-29-factorial.ll
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2014-08-29-CompactUnwind.ll
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9601.ll
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20090313-signext.ll
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AppendingLinkage.ll
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Atomics-64.ll
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DbgValueOtherTargets.test
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DynamicCalleeSavedRegisters.ll
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[X86] Regenerate callee-saved test checks to make D65354 diff easier
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MachineBranchProb.ll
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Rename ExpandISelPseudo->FinalizeISel, delay register reservation
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[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
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MergeConsecutiveStores.ll
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[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
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2019-05-25 06:17:47 +00:00 |
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O0-pipeline.ll
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Rename ExpandISelPseudo->FinalizeISel, delay register reservation
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2019-06-19 00:25:39 +00:00 |
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O3-pipeline.ll
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[MachineCSE][MachinePRE] Avoid hoisting code from code regions into hot BBs.
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2019-07-19 12:58:16 +00:00 |
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PR34565.ll
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PR37310.mir
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Describe stack-id as an enum
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2019-06-17 09:13:29 +00:00 |
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PR40322.ll
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[X86] Run CFIInstrInserter on Windows if Dwarf is used
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2019-04-29 20:25:51 +00:00 |
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StackColoring-dbg.ll
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StackColoring.ll
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SwitchLowering.ll
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SwizzleShuff.ll
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Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
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TruncAssertSext.ll
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TruncAssertZext.ll
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WidenArith.ll
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abi-isel.ll
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absolute-bit-mask-fastisel.ll
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absolute-bit-mask.ll
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absolute-bt.ll
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absolute-cmp.ll
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absolute-constant.ll
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[X86] Automatically generate various tests. NFC
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absolute-rotate.ll
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add-ext.ll
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[DAG] Refactor DAGCombiner::ReassociateOps
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2019-04-29 17:50:10 +00:00 |
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add-i64.ll
|
…
|
|
|
add-of-carry.ll
|
[DAGCombiner] Don't combine (addcarry (uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry) if the Carry comes from the uaddo.
|
2019-07-04 18:18:46 +00:00 |
|
add-sub-nsw-nuw.ll
|
…
|
|
|
add.ll
|
[X86] Teach convertToThreeAddress to handle SUB with immediate
|
2019-07-15 23:07:56 +00:00 |
|
add32ri8.ll
|
…
|
|
|
add_shl_constant.ll
|
…
|
|
|
addcarry.ll
|
[DAGCombiner] fold (addcarry (xor a, -1), b, c) -> (subcarry b, a, !c) and flip carry.
|
2019-07-16 15:17:00 +00:00 |
|
addcarry2.ll
|
…
|
|
|
addr-label-difference.ll
|
…
|
|
|
addr-mode-matcher-2.ll
|
[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
|
2019-06-25 17:29:18 +00:00 |
|
addr-mode-matcher.ll
|
…
|
|
|
addr-of-ret-addr.ll
|
…
|
|
|
address-type-promotion-constantexpr.ll
|
…
|
|
|
addrsig.ll
|
…
|
|
|
addsub-constant-folding.ll
|
[NFC][Codegen] Add/sub constant-folding: add scalar tests too
|
2019-05-31 08:23:48 +00:00 |
|
adx-commute.mir
|
…
|
|
|
adx-intrinsics-upgrade.ll
|
…
|
|
|
adx-intrinsics.ll
|
…
|
|
|
aes_intrinsics.ll
|
…
|
|
|
alias-gep.ll
|
…
|
|
|
alias-static-alloca.ll
|
[X86] Regenerate alias-static-alloca test checks to make D65354 diff easier
|
2019-07-31 12:27:47 +00:00 |
|
aliases.ll
|
…
|
|
|
aligned-comm.ll
|
…
|
|
|
aligned-variadic.ll
|
…
|
|
|
alignment-2.ll
|
…
|
|
|
alignment.ll
|
…
|
|
|
all-ones-vector.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
alldiv-divdi3.ll
|
…
|
|
|
alloca-align-rounding-32.ll
|
…
|
|
|
alloca-align-rounding.ll
|
…
|
|
|
alloca-overaligned.ll
|
[Tests] Add a test showing how we handle overaligned allocas w/ no-realign-stack
|
2019-07-18 00:26:03 +00:00 |
|
allrem-moddi3.ll
|
…
|
|
|
and-encoding.ll
|
…
|
|
|
and-load-fold.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
and-or-fold.ll
|
…
|
|
|
and-sink.ll
|
…
|
|
|
and-su.ll
|
…
|
|
|
andimm8.ll
|
…
|
|
|
anyext.ll
|
…
|
|
|
anyregcc-crash.ll
|
RegAlloc: try to fail more gracefully when out of registers
|
2019-05-15 17:29:58 +00:00 |
|
anyregcc.ll
|
…
|
|
|
apm.ll
|
…
|
|
|
arg-cast.ll
|
…
|
|
|
arg-copy-elide-win64.ll
|
[X86] Disable argument copy elision for arguments passed via pointers
|
2019-04-20 15:26:44 +00:00 |
|
arg-copy-elide.ll
|
…
|
|
|
arg_returned_bitcast.ll
|
[SelectionDAG][FIX] Allow "returned" arguments to be bit-casted
|
2019-06-04 20:34:43 +00:00 |
|
asm-block-labels.ll
|
…
|
|
|
asm-global-imm.ll
|
…
|
|
|
asm-indirect-mem.ll
|
…
|
|
|
asm-invalid-register-class-crasher.ll
|
…
|
|
|
asm-label.ll
|
…
|
|
|
asm-label2.ll
|
…
|
|
|
asm-mismatched-types.ll
|
…
|
|
|
asm-modifier-P.ll
|
…
|
|
|
asm-modifier.ll
|
…
|
|
|
asm-reg-type-mismatch-avx512.ll
|
[X86] Add test case that was supposed to go with r360102.
|
2019-05-24 04:46:56 +00:00 |
|
asm-reg-type-mismatch.ll
|
…
|
|
|
asm-reject-reg-type-mismatch.ll
|
…
|
|
|
asm-reject-rex.ll
|
…
|
|
|
asm-reject-vk32-vk64.ll
|
[X86] Block i32/i64 for 'k' and 'Yk' in getRegForInlineAsmConstraint without avx512bw.
|
2019-04-15 18:39:45 +00:00 |
|
asm-reject-xmm16.ll
|
…
|
|
|
atom-call-reg-indirect-foldedreload32.ll
|
…
|
|
|
atom-call-reg-indirect-foldedreload64.ll
|
…
|
|
|
atom-call-reg-indirect.ll
|
…
|
|
|
atom-cmpb.ll
|
…
|
|
|
atom-fixup-lea1.ll
|
…
|
|
|
atom-fixup-lea2.ll
|
…
|
|
|
atom-fixup-lea3.ll
|
…
|
|
|
atom-fixup-lea4.ll
|
…
|
|
|
atom-lea-addw-bug.ll
|
…
|
|
|
atom-lea-sp.ll
|
…
|
|
|
atom-pad-short-functions.ll
|
…
|
|
|
atom-sched.ll
|
…
|
|
|
atom-shuf.ll
|
…
|
|
|
atomic-add.ll
|
…
|
|
|
atomic-dagsched.ll
|
…
|
|
|
atomic-eflags-reuse.ll
|
…
|
|
|
atomic-flags.ll
|
…
|
|
|
atomic-fp.ll
|
[X86] Use MOVQ for i64 atomic_stores when SSE2 is enabled
|
2019-04-27 03:38:15 +00:00 |
|
atomic-idempotent.ll
|
Use an offset from TOS for idempotent rmw locked op lowering
|
2019-05-14 22:32:42 +00:00 |
|
atomic-load-store-wide.ll
|
[X86] Prefer locked stack op over mfence for seq_cst 64-bit stores on 32-bit targets
|
2019-05-14 04:43:37 +00:00 |
|
atomic-load-store.ll
|
…
|
|
|
atomic-mi.ll
|
Recommit r358211 "[X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87, but no SSE2"
|
2019-04-11 19:19:42 +00:00 |
|
atomic-minmax-i6432.ll
|
…
|
|
|
atomic-monotonic.ll
|
Use the handle --check-prefixes mechanism to de-verbosify a couple atomics tests [NFC]
|
2019-08-28 20:27:39 +00:00 |
|
atomic-non-integer-fp128.ll
|
[X86] Enable fp128 as a legal type with SSE1 rather than with MMX.
|
2019-09-02 20:16:30 +00:00 |
|
atomic-non-integer.ll
|
[X86] Enable fp128 as a legal type with SSE1 rather than with MMX.
|
2019-09-02 20:16:30 +00:00 |
|
atomic-op.ll
|
…
|
|
|
atomic-ops-ancient-64.ll
|
…
|
|
|
atomic-or.ll
|
…
|
|
|
atomic-pointer.ll
|
…
|
|
|
atomic-unordered.ll
|
Use the handle --check-prefixes mechanism to de-verbosify a couple atomics tests [NFC]
|
2019-08-28 20:27:39 +00:00 |
|
atomic8.ll
|
…
|
|
|
atomic16.ll
|
…
|
|
|
atomic32.ll
|
Reapply r359906, "RegAllocFast: Add heuristic to detect values not live-out of a block"
|
2019-05-03 19:06:57 +00:00 |
|
atomic64.ll
|
Reapply r359906, "RegAllocFast: Add heuristic to detect values not live-out of a block"
|
2019-05-03 19:06:57 +00:00 |
|
atomic128.ll
|
…
|
|
|
atomic6432.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
atomicf128.ll
|
[X86] Enable fp128 as a legal type with SSE1 rather than with MMX.
|
2019-09-02 20:16:30 +00:00 |
|
attribute-sections.ll
|
…
|
|
|
avg-mask.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
avg.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
avoid-lea-scale2.ll
|
…
|
|
|
avoid-loop-align-2.ll
|
…
|
|
|
avoid-loop-align.ll
|
…
|
|
|
avoid-sfb-g-no-change.mir
|
Resubmit r360436 "[X86] Avoid SFB - Fix inconsistent codegen with/without debug info"
|
2019-05-23 18:15:12 +00:00 |
|
avoid-sfb-g-no-change2.mir
|
[X86] Avoid SFB - Fix inconsistent codegen with/without debug info(2)
|
2019-07-01 18:28:21 +00:00 |
|
avoid-sfb-g-no-change3.mir
|
[X86] Avoid SFB - Fix inconsistent codegen with/without debug info(2)
|
2019-07-01 18:28:21 +00:00 |
|
avoid-sfb-kill-flags.mir
|
…
|
|
|
avoid-sfb-offset.mir
|
Describe stack-id as an enum
|
2019-06-17 09:13:29 +00:00 |
|
avoid-sfb-overlaps.ll
|
…
|
|
|
avoid-sfb.ll
|
…
|
|
|
avoid_complex_am.ll
|
…
|
|
|
avx-arith.ll
|
…
|
|
|
avx-basic.ll
|
…
|
|
|
avx-bitcast.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
avx-brcond.ll
|
…
|
|
|
avx-cast.ll
|
…
|
|
|
avx-cmp.ll
|
…
|
|
|
avx-cvt-2.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
avx-cvt-3.ll
|
…
|
|
|
avx-cvt.ll
|
…
|
|
|
avx-cvttp2si.ll
|
…
|
|
|
avx-fp2int.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
avx-gfni-intrinsics.ll
|
…
|
|
|
avx-insertelt.ll
|
…
|
|
|
avx-intel-ocl.ll
|
…
|
|
|
avx-intrinsics-fast-isel.ll
|
…
|
|
|
avx-intrinsics-x86-upgrade.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
avx-intrinsics-x86.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
avx-intrinsics-x86_64.ll
|
…
|
|
|
avx-isa-check.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
avx-load-store.ll
|
[X86] Add DAG combine to turn (vzmovl (insert_subvector undef, X, 0)) into (insert_subvector allzeros, (vzmovl X), 0)
|
2019-06-21 19:10:21 +00:00 |
|
avx-logic.ll
|
…
|
|
|
avx-minmax.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
avx-select.ll
|
…
|
|
|
avx-shift.ll
|
…
|
|
|
avx-shuffle-x86_32.ll
|
…
|
|
|
avx-splat.ll
|
…
|
|
|
avx-trunc.ll
|
…
|
|
|
avx-unpack.ll
|
…
|
|
|
avx-varargs-x86_64.ll
|
…
|
|
|
avx-vbroadcast.ll
|
…
|
|
|
avx-vbroadcastf128.ll
|
…
|
|
|
avx-vextractf128.ll
|
…
|
|
|
avx-vinsertf128.ll
|
…
|
|
|
avx-vpclmulqdq.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
avx-vperm2x128.ll
|
…
|
|
|
avx-vzeroupper.ll
|
…
|
|
|
avx-win64-args.ll
|
…
|
|
|
avx-win64.ll
|
…
|
|
|
avx.ll
|
…
|
|
|
avx1-logical-load-folding.ll
|
…
|
|
|
avx2-arith.ll
|
…
|
|
|
avx2-cmp.ll
|
…
|
|
|
avx2-conversions.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
avx2-fma-fneg-combine.ll
|
…
|
|
|
avx2-gather.ll
|
…
|
|
|
avx2-intrinsics-canonical.ll
|
[X86] Regenerate tests. NFCI.
|
2019-07-10 17:22:31 +00:00 |
|
avx2-intrinsics-fast-isel.ll
|
[X86] Restore the pavg intrinsics.
|
2019-04-15 17:17:35 +00:00 |
|
avx2-intrinsics-x86-upgrade.ll
|
[X86] Restore the pavg intrinsics.
|
2019-04-15 17:17:35 +00:00 |
|
avx2-intrinsics-x86.ll
|
[X86] Restore the pavg intrinsics.
|
2019-04-15 17:17:35 +00:00 |
|
avx2-logic.ll
|
…
|
|
|
avx2-masked-gather.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
avx2-nontemporal.ll
|
…
|
|
|
avx2-phaddsub.ll
|
[X86][SSE] Fold add(shuffle(),shuffle()) to hadd on 'slow' targets (PR39920)
|
2019-05-09 17:45:01 +00:00 |
|
avx2-pmovxrm.ll
|
…
|
|
|
avx2-shift.ll
|
…
|
|
|
avx2-vbroadcast.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
avx2-vbroadcasti128.ll
|
…
|
|
|
avx2-vector-shifts.ll
|
…
|
|
|
avx2-vperm.ll
|
…
|
|
|
avx512-adc-sbb.ll
|
…
|
|
|
avx512-any_extend_load.ll
|
[X86] Remove some code from combineShuffle that seems largely unnecessary with widening legalization.
|
2019-08-11 02:08:38 +00:00 |
|
avx512-arith.ll
|
…
|
|
|
avx512-broadcast-unfold.ll
|
[X86] Add initial support for unfolding broadcast loads from arithmetic instructions to enable LICM hoisting of the load
|
2019-09-01 22:14:36 +00:00 |
|
avx512-bugfix-23634.ll
|
…
|
|
|
avx512-bugfix-25270.ll
|
Automatically generate AVX512 test cases. NFC
|
2019-08-19 14:34:08 +00:00 |
|
avx512-bugfix-26264.ll
|
…
|
|
|
avx512-build-vector.ll
|
…
|
|
|
avx512-calling-conv.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
avx512-cmp-kor-sequence.ll
|
…
|
|
|
avx512-cmp.ll
|
…
|
|
|
avx512-cvt.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
avx512-cvttp2i.ll
|
…
|
|
|
avx512-ext.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
avx512-extract-subvector-load-store.ll
|
…
|
|
|
avx512-extract-subvector.ll
|
…
|
|
|
avx512-fma-commute.ll
|
Automatically generate AVX512 test cases. NFC
|
2019-08-19 14:34:08 +00:00 |
|
avx512-fma-intrinsics-upgrade.ll
|
…
|
|
|
avx512-fma-intrinsics.ll
|
[X86] Add the rounding control operand to the printing for some scalar FMA instructions.
|
2019-04-21 07:12:56 +00:00 |
|
avx512-fma.ll
|
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
|
2019-06-25 10:51:15 +00:00 |
|
avx512-fsel.ll
|
…
|
|
|
avx512-gather-scatter-intrin-deprecated.ll
|
…
|
|
|
avx512-gather-scatter-intrin.ll
|
…
|
|
|
avx512-gfni-intrinsics.ll
|
…
|
|
|
avx512-hadd-hsub.ll
|
[X86][AVX] Fold extract_subvector(broadcast(x)) -> broadcast(x) iff x has one use
|
2019-04-26 18:02:14 +00:00 |
|
avx512-i1test.ll
|
…
|
|
|
avx512-inc-dec.ll
|
Automatically generate AVX512 test cases. NFC
|
2019-08-19 14:34:08 +00:00 |
|
avx512-insert-extract.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
avx512-insert-extract_i1.ll
|
…
|
|
|
avx512-intel-ocl.ll
|
[WinEH] Allocate space in funclets stack to save XMM CSRs
|
2019-08-27 01:53:24 +00:00 |
|
avx512-intrinsics-canonical.ll
|
…
|
|
|
avx512-intrinsics-fast-isel.ll
|
Revert [X86] SimplifyDemandedVectorElts - attempt to recombine target shuffle using DemandedElts mask (reapplied)
|
2019-08-16 23:08:56 +00:00 |
|
avx512-intrinsics-upgrade.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
avx512-intrinsics-x86_64.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
avx512-intrinsics.ll
|
[X86] Add a DAG combine to transform (i8 (bitcast (v8i1 (extract_subvector (v16i1 X), 0)))) -> (i8 (trunc (i16 (bitcast (v16i1 X))))) on KNL target
|
2019-08-20 20:20:04 +00:00 |
|
avx512-load-store.ll
|
…
|
|
|
avx512-load-trunc-store-i1.ll
|
…
|
|
|
avx512-logic.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
avx512-mask-op.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
avx512-mask-spills.ll
|
Automatically generate AVX512 test cases. NFC
|
2019-08-19 14:34:08 +00:00 |
|
avx512-mask-zext-bugfix.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
avx512-masked-memop-64-32.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
avx512-masked_memop-16-8.ll
|
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches.
|
2019-07-31 22:58:15 +00:00 |
|
avx512-memfold.ll
|
Automatically generate AVX512 test cases. NFC
|
2019-08-19 14:34:08 +00:00 |
|
avx512-mov.ll
|
…
|
|
|
avx512-nontemporal.ll
|
Automatically generate AVX512 test cases. NFC
|
2019-08-19 14:34:08 +00:00 |
|
avx512-pmovxrm.ll
|
…
|
|
|
avx512-regcall-Mask.ll
|
[X86] Print register names in .seh_* directives
|
2019-08-30 21:23:05 +00:00 |
|
avx512-regcall-NoMask.ll
|
[X86] Print register names in .seh_* directives
|
2019-08-30 21:23:05 +00:00 |
|
avx512-rndscale.ll
|
…
|
|
|
avx512-rotate.ll
|
…
|
|
|
avx512-scalar.ll
|
…
|
|
|
avx512-scalarIntrinsics.ll
|
…
|
|
|
avx512-scalar_mask.ll
|
Automatically generate AVX512 test cases. NFC
|
2019-08-19 14:34:08 +00:00 |
|
avx512-select.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
avx512-shift.ll
|
…
|
|
|
avx512-skx-insert-subvec.ll
|
[X86] Teach lower1BitShuffle to recognize padding a subvector with zeros with V2 as the source and V1 as the zero vector.
|
2019-08-19 00:39:22 +00:00 |
|
avx512-trunc.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
avx512-unsafe-fp-math.ll
|
…
|
|
|
avx512-vbroadcast.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
avx512-vbroadcasti128.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
avx512-vbroadcasti256.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
avx512-vec-cmp.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
avx512-vec3-crash.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
avx512-vpclmulqdq.ll
|
…
|
|
|
avx512-vpermv3-commute.ll
|
…
|
|
|
avx512-vpternlog-commute.ll
|
…
|
|
|
avx512-vselect-crash.ll
|
…
|
|
|
avx512-vselect.ll
|
…
|
|
|
avx512bf16-intrinsics.ll
|
[X86] Regenerate intrinsics tests. NFCI.
|
2019-07-11 10:40:23 +00:00 |
|
avx512bf16-vl-intrinsics.ll
|
[CodeGen] Move X86 tests under the X86 directory
|
2019-05-06 10:21:17 +00:00 |
|
avx512bw-arith.ll
|
…
|
|
|
avx512bw-intrinsics-canonical.ll
|
…
|
|
|
avx512bw-intrinsics-fast-isel.ll
|
…
|
|
|
avx512bw-intrinsics-upgrade.ll
|
…
|
|
|
avx512bw-intrinsics.ll
|
[X86] Restore the pavg intrinsics.
|
2019-04-15 17:17:35 +00:00 |
|
avx512bw-mask-op.ll
|
…
|
|
|
avx512bw-mov.ll
|
…
|
|
|
avx512bw-vec-cmp.ll
|
…
|
|
|
avx512bw-vec-test-testn.ll
|
…
|
|
|
avx512bwvl-arith.ll
|
…
|
|
|
avx512bwvl-intrinsics-canonical.ll
|
…
|
|
|
avx512bwvl-intrinsics-fast-isel.ll
|
…
|
|
|
avx512bwvl-intrinsics-upgrade.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
avx512bwvl-intrinsics.ll
|
[X86] Restore the pavg intrinsics.
|
2019-04-15 17:17:35 +00:00 |
|
avx512bwvl-mov.ll
|
…
|
|
|
avx512bwvl-vec-cmp.ll
|
…
|
|
|
avx512bwvl-vec-test-testn.ll
|
…
|
|
|
avx512cd-intrinsics-fast-isel.ll
|
…
|
|
|
avx512cd-intrinsics-upgrade.ll
|
…
|
|
|
avx512cd-intrinsics.ll
|
…
|
|
|
avx512cdvl-intrinsics-upgrade.ll
|
…
|
|
|
avx512cdvl-intrinsics.ll
|
…
|
|
|
avx512dq-intrinsics-fast-isel.ll
|
…
|
|
|
avx512dq-intrinsics-upgrade.ll
|
…
|
|
|
avx512dq-intrinsics.ll
|
…
|
|
|
avx512dq-mask-op.ll
|
…
|
|
|
avx512dqvl-intrinsics-fast-isel.ll
|
…
|
|
|
avx512dqvl-intrinsics-upgrade.ll
|
…
|
|
|
avx512dqvl-intrinsics.ll
|
[X86] Correct v4f32->v2i64 cvt(t)ps2(u)qq memory isel patterns
|
2019-07-01 19:01:37 +00:00 |
|
avx512er-intrinsics.ll
|
…
|
|
|
avx512f-256-set0.mir
|
[X86] Fix machineverifier error on avx512f-256-set0.mir
|
2019-05-29 17:02:27 +00:00 |
|
avx512f-vec-test-testn.ll
|
…
|
|
|
avx512ifma-intrinsics-fast-isel.ll
|
…
|
|
|
avx512ifma-intrinsics-upgrade.ll
|
…
|
|
|
avx512ifma-intrinsics.ll
|
…
|
|
|
avx512ifmavl-intrinsics-fast-isel.ll
|
…
|
|
|
avx512ifmavl-intrinsics-upgrade.ll
|
…
|
|
|
avx512ifmavl-intrinsics.ll
|
…
|
|
|
avx512vbmi-intrinsics-fast-isel.ll
|
…
|
|
|
avx512vbmi-intrinsics-upgrade.ll
|
…
|
|
|
avx512vbmi-intrinsics.ll
|
…
|
|
|
avx512vbmi2-intrinsics-fast-isel.ll
|
…
|
|
|
avx512vbmi2-intrinsics-upgrade.ll
|
…
|
|
|
avx512vbmi2-intrinsics.ll
|
…
|
|
|
avx512vbmi2vl-intrinsics-fast-isel.ll
|
…
|
|
|
avx512vbmi2vl-intrinsics-upgrade.ll
|
…
|
|
|
avx512vbmi2vl-intrinsics.ll
|
…
|
|
|
avx512vbmivl-intrinsics-fast-isel.ll
|
…
|
|
|
avx512vbmivl-intrinsics-upgrade.ll
|
…
|
|
|
avx512vbmivl-intrinsics.ll
|
…
|
|
|
avx512vl-arith.ll
|
…
|
|
|
avx512vl-intrinsics-canonical.ll
|
…
|
|
|
avx512vl-intrinsics-fast-isel.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
avx512vl-intrinsics-upgrade.ll
|
[X86] Add a DAG combine to transform (i8 (bitcast (v8i1 (extract_subvector (v16i1 X), 0)))) -> (i8 (trunc (i16 (bitcast (v16i1 X))))) on KNL target
|
2019-08-20 20:20:04 +00:00 |
|
avx512vl-intrinsics.ll
|
…
|
|
|
avx512vl-logic.ll
|
…
|
|
|
avx512vl-mov.ll
|
…
|
|
|
avx512vl-nontemporal.ll
|
Automatically generate AVX512 test cases. NFC
|
2019-08-19 14:34:08 +00:00 |
|
avx512vl-vbroadcast.ll
|
…
|
|
|
avx512vl-vec-cmp.ll
|
…
|
|
|
avx512vl-vec-masked-cmp.ll
|
[DAGCombiner][X86] Teach visitCONCAT_VECTORS to combine (concat_vectors (concat_vectors X, Y), undef)) -> (concat_vectors X, Y, undef, undef)
|
2019-08-20 22:12:50 +00:00 |
|
avx512vl-vec-test-testn.ll
|
…
|
|
|
avx512vl-vpclmulqdq.ll
|
…
|
|
|
avx512vl_vnni-intrinsics-upgrade.ll
|
…
|
|
|
avx512vl_vnni-intrinsics.ll
|
…
|
|
|
avx512vlcd-intrinsics-fast-isel.ll
|
[X86] Add a DAG combine to transform (i8 (bitcast (v8i1 (extract_subvector (v16i1 X), 0)))) -> (i8 (trunc (i16 (bitcast (v16i1 X))))) on KNL target
|
2019-08-20 20:20:04 +00:00 |
|
avx512vlvp2intersect-intrinsics.ll
|
[X86] Regenerate intrinsics tests. NFCI.
|
2019-07-11 10:40:23 +00:00 |
|
avx512vnni-intrinsics-upgrade.ll
|
…
|
|
|
avx512vnni-intrinsics.ll
|
…
|
|
|
avx512vnni.ll
|
[X86] Add isel patterns to match vpdpwssd avx512vnni instruction from add+pmaddwd nodes.
|
2019-08-24 23:14:57 +00:00 |
|
avx512vp2intersect-intrinsics.ll
|
[X86] Regenerate intrinsics tests. NFCI.
|
2019-07-11 10:40:23 +00:00 |
|
avx512vpopcntdq-intrinsics.ll
|
…
|
|
|
backpropmask.ll
|
…
|
|
|
bad-tls-fold.mir
|
…
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|
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barrier-sse.ll
|
…
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|
|
barrier.ll
|
…
|
|
|
base-pointer-and-cmpxchg.ll
|
…
|
|
|
basic-promote-integers.ll
|
…
|
|
|
bb_rotate.ll
|
…
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|
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bc-extract.ll
|
…
|
|
|
bigstructret.ll
|
…
|
|
|
bigstructret2.ll
|
…
|
|
|
bit-piece-comment.ll
|
…
|
|
|
bit-test-shift.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
bitcast-and-setcc-128.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
bitcast-and-setcc-256.ll
|
[X86][AVX] combineBitcastvxi1 - peek through bitops to determine size of original vector
|
2019-05-26 10:54:23 +00:00 |
|
bitcast-and-setcc-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
bitcast-i256.ll
|
…
|
|
|
bitcast-int-to-vector-bool-sext.ll
|
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
|
2019-07-04 10:17:10 +00:00 |
|
bitcast-int-to-vector-bool-zext.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
bitcast-int-to-vector-bool.ll
|
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
|
2019-07-04 10:17:10 +00:00 |
|
bitcast-int-to-vector.ll
|
…
|
|
|
bitcast-mmx.ll
|
…
|
|
|
bitcast-setcc-128.ll
|
[X86] Add isel patterns for (i64 (zext (i8 (bitcast (v16i1 X))))) to use a KMOVW and a SUBREG_TO_REG. Similar for i8 and anyextend.
|
2019-08-20 19:43:48 +00:00 |
|
bitcast-setcc-256.ll
|
Recommit r358887 "[TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handling"
|
2019-05-13 04:03:35 +00:00 |
|
bitcast-setcc-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
bitcast-vector-bool.ll
|
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::TRUNCATE
|
2019-08-12 10:56:05 +00:00 |
|
bitcast.ll
|
…
|
|
|
bitcast2.ll
|
…
|
|
|
bitcnt-false-dep.ll
|
…
|
|
|
bitreverse.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
block-placement.ll
|
Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
|
block-placement.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
bmi-intrinsics-fast-isel-x86_64.ll
|
[X86] Teach convertToThreeAddress to handle SUB with immediate
|
2019-07-15 23:07:56 +00:00 |
|
bmi-intrinsics-fast-isel.ll
|
[X86] Teach convertToThreeAddress to handle SUB with immediate
|
2019-07-15 23:07:56 +00:00 |
|
bmi-x86_64.ll
|
…
|
|
|
bmi.ll
|
[X86] Add patterns with and_flag_nocf for BLSI and TBM instructions.
|
2019-07-10 22:44:32 +00:00 |
|
bmi2-x86_64.ll
|
…
|
|
|
bmi2.ll
|
…
|
|
|
bool-ext-inc.ll
|
…
|
|
|
bool-math.ll
|
…
|
|
|
bool-simplify.ll
|
…
|
|
|
bool-vector.ll
|
[X86][SSE] Extract i1 elements from vXi1 bool vectors
|
2019-05-01 10:02:22 +00:00 |
|
bool-zext.ll
|
…
|
|
|
br-fold.ll
|
Revert [Windows] Disable TrapUnreachable for Win64, add SEH_NoReturn
|
2019-09-03 22:27:27 +00:00 |
|
branchfolding-catchpads.ll
|
…
|
|
|
branchfolding-debugloc.ll
|
…
|
|
|
branchfolding-landingpads.ll
|
…
|
|
|
branchfolding-undef.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
brcond.ll
|
…
|
|
|
break-anti-dependencies.ll
|
…
|
|
|
break-false-dep.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
broadcast-elm-cross-splat-vec.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
broadcastm-lowering.ll
|
…
|
|
|
bss_pagealigned.ll
|
…
|
|
|
bswap-inline-asm.ll
|
…
|
|
|
bswap-rotate.ll
|
…
|
|
|
bswap-vector.ll
|
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
|
2019-08-07 16:33:37 +00:00 |
|
bswap-wide-int.ll
|
…
|
|
|
bswap.ll
|
…
|
|
|
bswap_tree.ll
|
…
|
|
|
bswap_tree2.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
bt.ll
|
[x86] make 8-bit shl undesirable
|
2019-04-08 13:58:50 +00:00 |
|
btc_bts_btr.ll
|
[TargetLowering][X86] Teach SimplifyDemandedBits to use ShrinkDemandedOp on ISD::SHL nodes.
|
2019-04-12 06:49:28 +00:00 |
|
btq.ll
|
…
|
|
|
bug26810.ll
|
…
|
|
|
bug37521.ll
|
…
|
|
|
build-vector-128.ll
|
…
|
|
|
build-vector-256.ll
|
…
|
|
|
build-vector-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
buildvec-extract.ll
|
…
|
|
|
buildvec-insertvec.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
bypass-slow-division-32.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
bypass-slow-division-64.ll
|
…
|
|
|
bypass-slow-division-tune.ll
|
…
|
|
|
byval-align.ll
|
…
|
|
|
byval-callee-cleanup.ll
|
…
|
|
|
byval.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
byval2.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
byval3.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
byval4.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
byval5.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
byval6.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
byval7.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
cache-intrinsic.ll
|
…
|
|
|
call-imm.ll
|
…
|
|
|
call-push.ll
|
…
|
|
|
call-site-info-output.ll
|
[ISEL][X86] Tracking of registers that forward call arguments
|
2019-06-27 10:51:15 +00:00 |
|
callbr-asm-bb-exports.ll
|
[X86] Add test case for r361177.
|
2019-05-20 17:37:52 +00:00 |
|
callbr-asm-blockplacement.ll
|
…
|
|
|
callbr-asm-branch-folding.ll
|
…
|
|
|
callbr-asm-destinations.ll
|
…
|
|
|
callbr-asm-errors.ll
|
…
|
|
|
callbr-asm-label-addr.ll
|
[MC] Don't recreate a label if it's already used
|
2019-08-09 20:16:31 +00:00 |
|
callbr-asm-obj-file.ll
|
[CodeGen] Require a name for a block addr target
|
2019-08-09 20:18:30 +00:00 |
|
callbr-asm-outputs.ll
|
…
|
|
|
callbr-asm.ll
|
[MC] Don't recreate a label if it's already used
|
2019-08-09 20:16:31 +00:00 |
|
cas.ll
|
…
|
|
|
cast-vsel.ll
|
[x86] split 256-bit vector selects if operands are vector concats
|
2019-06-16 14:04:49 +00:00 |
|
catch.ll
|
…
|
|
|
catchpad-dynamic-alloca.ll
|
…
|
|
|
catchpad-lifetime.ll
|
Revert [Windows] Disable TrapUnreachable for Win64, add SEH_NoReturn
|
2019-09-03 22:27:27 +00:00 |
|
catchpad-realign-savexmm.ll
|
[X86] Print register names in .seh_* directives
|
2019-08-30 21:23:05 +00:00 |
|
catchpad-regmask.ll
|
Revert [Windows] Disable TrapUnreachable for Win64, add SEH_NoReturn
|
2019-09-03 22:27:27 +00:00 |
|
catchpad-reuse.ll
|
…
|
|
|
catchpad-weight.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
catchret-empty-fallthrough.ll
|
…
|
|
|
catchret-fallthrough.ll
|
…
|
|
|
catchret-regmask.ll
|
Revert [Windows] Disable TrapUnreachable for Win64, add SEH_NoReturn
|
2019-09-03 22:27:27 +00:00 |
|
cfi-inserter-cfg-with-merge.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
cfi-inserter-check-order.ll
|
…
|
|
|
cfi-inserter-noreturnblock.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
cfi-inserter-verify-inconsistent-offset.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
cfi-inserter-verify-inconsistent-register.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
cfi-xmm.ll
|
…
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|
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cfi.ll
|
…
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cfstring.ll
|
…
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|
|
cgp-usubo.ll
|
[X86] Teach convertToThreeAddress to handle SUB with immediate
|
2019-07-15 23:07:56 +00:00 |
|
chain_order.ll
|
…
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change-compare-stride-1.ll
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…
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change-compare-stride-trickiness-0.ll
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…
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change-compare-stride-trickiness-1.ll
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…
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change-compare-stride-trickiness-2.ll
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…
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change-unsafe-fp-math.ll
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…
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cldemote-intrinsic.ll
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…
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cleanuppad-inalloca.ll
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…
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cleanuppad-large-codemodel.ll
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…
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cleanuppad-realign.ll
|
[X86] Print register names in .seh_* directives
|
2019-08-30 21:23:05 +00:00 |
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clear-highbits.ll
|
…
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|
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clear-lowbits.ll
|
…
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clear_upper_vector_element_bits.ll
|
[X86] EltsFromConsecutiveLoads - support common source loads (REAPPLIED)
|
2019-07-22 12:44:10 +00:00 |
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clflushopt.ll
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…
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clwb.ll
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…
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clz.ll
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…
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clzero.ll
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…
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cmov-double.ll
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…
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cmov-fp.ll
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…
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cmov-into-branch.ll
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…
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cmov-promotion.ll
|
Teach the DAGCombine to fold this pattern(c1 and c2 is constant).
|
2019-06-26 05:12:53 +00:00 |
|
cmov.ll
|
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
|
2019-06-13 13:56:19 +00:00 |
|
cmovcmov.ll
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
cmp-fast-isel.ll
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…
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cmp.ll
|
[X86] When promoting i16 compare with immediate to i32, try to use sign_extend for eq/ne if the input is truncated from a type with enough sign its.
|
2019-06-10 04:50:12 +00:00 |
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cmpxchg-clobber-flags.ll
|
…
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cmpxchg-i1.ll
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…
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cmpxchg-i128-i1.ll
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…
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cmpxchg8b.ll
|
[X86] Make CMPXCHG16B feature imply CMPXCHG8B feature.
|
2019-08-08 18:11:17 +00:00 |
|
cmpxchg8b_alloca_regalloc_handling.ll
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…
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cmpxchg16b.ll
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…
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coal-sections.ll
|
…
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coalesce-dbg-value-subreg-rewrite.mir
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…
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coalesce-dead-lanes.mir
|
…
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coalesce-esp.ll
|
…
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coalesce-implicitdef.ll
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…
|
|
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coalesce_commute_movsd.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
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coalesce_commute_subreg.ll
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…
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coalescer-commute1.ll
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…
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coalescer-commute2.ll
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…
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coalescer-commute3.ll
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…
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coalescer-commute4.ll
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…
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coalescer-commute5.ll
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…
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coalescer-cross.ll
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…
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coalescer-dce.ll
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…
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coalescer-dce2.ll
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…
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coalescer-identity.ll
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…
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coalescer-remat.ll
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…
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coalescer-subreg.ll
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…
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coalescer-win64.ll
|
…
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code-model-elf-memset.ll
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…
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code-model-elf.ll
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…
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code-model-kernel.ll
|
…
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|
code_placement.ll
|
Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
|
code_placement_align_all.ll
|
…
|
|
|
code_placement_cold_loop_blocks.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
code_placement_eh.ll
|
…
|
|
|
code_placement_ignore_succ_in_inner_loop.ll
|
Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
|
code_placement_loop_rotation.ll
|
…
|
|
|
code_placement_loop_rotation2.ll
|
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
|
2019-08-12 14:23:13 +00:00 |
|
code_placement_loop_rotation3.ll
|
…
|
|
|
code_placement_no_header_change.ll
|
Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
|
codegen-prepare-addrmode-sext.ll
|
…
|
|
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codegen-prepare-cast.ll
|
…
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codegen-prepare-crash.ll
|
…
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codegen-prepare-extload.ll
|
…
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codegen-prepare-replacephi.mir
|
…
|
|
|
codegen-prepare-uaddo.ll
|
…
|
|
|
codegen-prepare.ll
|
…
|
|
|
codemodel.ll
|
[X86] Use PC-relative mode for the kernel code model
|
2019-04-13 21:39:28 +00:00 |
|
coff-comdat.ll
|
…
|
|
|
coff-comdat2.ll
|
…
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|
|
coff-comdat3.ll
|
…
|
|
|
coff-feat00.ll
|
…
|
|
|
coff-fp-section-name.ll
|
[COFF] Fix section name for constants larger than 64 bits on Windows
|
2019-08-22 01:48:34 +00:00 |
|
coff-no-dead-strip.ll
|
…
|
|
|
coff-weak.ll
|
…
|
|
|
coldcc64.ll
|
…
|
|
|
combine-64bit-vec-binop.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
combine-abs.ll
|
…
|
|
|
combine-adc.ll
|
…
|
|
|
combine-add-ssat.ll
|
…
|
|
|
combine-add-usat.ll
|
…
|
|
|
combine-add.ll
|
[DAGCombiner][X86][AArch64][AMDGPU] (x + C) - y -> (x - y) + C fold. Try 3
|
2019-05-30 20:36:54 +00:00 |
|
combine-addo.ll
|
…
|
|
|
combine-adx.ll
|
…
|
|
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combine-and.ll
|
…
|
|
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combine-avx-intrinsics.ll
|
…
|
|
|
combine-avx2-intrinsics.ll
|
…
|
|
|
combine-bitreverse.ll
|
[SelectionDAG] computeKnownBits - support constant pool values from target
|
2019-05-24 10:03:11 +00:00 |
|
combine-bitselect.ll
|
[X86][AVX] getTargetConstantBitsFromNode - extract bits from X86ISD::SUBV_BROADCAST
|
2019-04-10 16:24:47 +00:00 |
|
combine-bswap.ll
|
…
|
|
|
combine-concatvectors.ll
|
…
|
|
|
combine-fabs.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
combine-fcopysign.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/combine-fcopysign.ll X86/dag-fmf-cse.ll X86/fast-isel-fneg.ll X86/fdiv.ll"
|
2019-06-13 19:24:38 +00:00 |
|
combine-lds.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
combine-mul.ll
|
[DAGCombine] visitMUL - allow shift by zero in MulByConstant.
|
2019-06-24 12:47:17 +00:00 |
|
combine-mulo.ll
|
…
|
|
|
combine-multiplies.ll
|
[DAG] Refactor DAGCombiner::ReassociateOps
|
2019-04-29 17:50:10 +00:00 |
|
combine-or.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
combine-pmuldq.ll
|
[X86][SSE] combinePMULDQ - pmuldq(x, 0) -> zero vector (PR43159)
|
2019-08-29 20:22:08 +00:00 |
|
combine-rotates.ll
|
…
|
|
|
combine-sbb.ll
|
[x86] try harder to form LEA from ADD to avoid flag conflicts (PR40483)
|
2019-07-18 12:48:01 +00:00 |
|
combine-sdiv.ll
|
[X86] Pre-commit test cases and test run line changes for D67087
|
2019-09-04 17:33:38 +00:00 |
|
combine-select.ll
|
…
|
|
|
combine-sext-in-reg.ll
|
…
|
|
|
combine-shl.ll
|
[DAGCombiner] Support (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C)) non-uniform folds.
|
2019-06-20 14:42:27 +00:00 |
|
combine-smax.ll
|
…
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|
|
combine-smin.ll
|
…
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|
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combine-sra.ll
|
…
|
|
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combine-srem.ll
|
[X86] Pre-commit test cases and test run line changes for D67087
|
2019-09-04 17:33:38 +00:00 |
|
combine-srl.ll
|
…
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|
|
combine-sse41-intrinsics.ll
|
[X86][SSE] Swap X86ISD::BLENDV inputs with an inverted selection mask (PR42825)
|
2019-08-09 12:44:20 +00:00 |
|
combine-sub-ssat.ll
|
…
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|
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combine-sub-usat.ll
|
…
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|
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combine-sub.ll
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…
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combine-subo.ll
|
…
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|
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combine-testm-and.ll
|
…
|
|
|
combine-udiv.ll
|
[TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support.
|
2019-06-27 14:25:54 +00:00 |
|
combine-umax.ll
|
…
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|
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combine-umin.ll
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…
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|
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combine-urem.ll
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…
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|
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commandline-metadata.ll
|
…
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|
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commute-3dnow.ll
|
…
|
|
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commute-blend-avx2.ll
|
…
|
|
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commute-blend-sse41.ll
|
…
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|
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commute-clmul.ll
|
…
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|
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commute-fcmp.ll
|
…
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|
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commute-intrinsic.ll
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…
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|
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commute-two-addr.ll
|
…
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|
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commute-vpclmulqdq-avx.ll
|
…
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|
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commute-vpclmulqdq-avx512.ll
|
…
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|
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commute-xop.ll
|
…
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commuted-blend-mask.ll
|
…
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|
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compact-unwind.ll
|
…
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compare-add.ll
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…
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|
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compare-global.ll
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…
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|
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compare-inf.ll
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…
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|
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compare_folding.ll
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…
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|
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compiler_used.ll
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…
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|
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complex-asm.ll
|
…
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|
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complex-fastmath.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
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complex-fca.ll
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…
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|
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computeKnownBits_urem.ll
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…
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|
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condbr_if.ll
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…
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|
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condbr_switch.ll
|
…
|
|
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conditional-indecrement.ll
|
…
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|
|
conditional-tailcall-samedest.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
conditional-tailcall.ll
|
[X86] Print register names in .seh_* directives
|
2019-08-30 21:23:05 +00:00 |
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consecutive-load-shuffle.ll
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…
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|
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const-base-addr.ll
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…
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|
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const-shift-of-constmasked.ll
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[NFC][CodeGen][X86][AArch64] Add and-const-mask + const-shift pattern tests
|
2019-05-14 20:17:04 +00:00 |
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constant-combines.ll
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…
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|
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constant-hoisting-and.ll
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…
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constant-hoisting-bfi.ll
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…
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constant-hoisting-cmp.ll
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…
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constant-hoisting-optnone.ll
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…
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constant-hoisting-shift-immediate.ll
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…
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constant-pool-remat-0.ll
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…
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constant-pool-sharing.ll
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…
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constpool.ll
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…
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|
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constrained-fp80-trunc-ext.ll
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[FPEnv] Lower STRICT_FP_EXTEND and STRICT_FP_ROUND nodes in preprocess phase of ISelLowering to mirror non-strict nodes on x86.
|
2019-06-14 16:28:55 +00:00 |
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constructor.ll
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…
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convert-2-addr-3-addr-inc64.ll
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…
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copy-eflags.ll
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[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
|
2019-06-13 13:56:19 +00:00 |
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copy-propagation.ll
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[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
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copysign-constant-magnitude.ll
|
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
|
2019-07-02 17:51:02 +00:00 |
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cpus-amd-no-x86_64.ll
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…
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cpus-amd.ll
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…
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|
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cpus-intel-no-x86_64.ll
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…
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|
|
cpus-intel.ll
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[X86] Support -march=tigerlake
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2019-08-12 01:29:46 +00:00 |
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cpus-no-x86_64.ll
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…
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|
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cpus-other.ll
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…
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|
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crash-O0.ll
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RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
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crash-lre-eliminate-dead-def.ll
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…
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crash-nosse.ll
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…
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crash.ll
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…
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critical-anti-dep-breaker.ll
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…
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critical-edge-split-2.ll
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…
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cse-add-with-overflow.ll
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…
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csr-split.ll
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[NFC][Regalloc] Add testcases for D66576
|
2019-08-26 05:06:30 +00:00 |
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cstring.ll
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…
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ctor-priority-coff.ll
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…
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ctpop-combine.ll
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[SDAG] expand ctpop != 1
|
2019-06-25 14:46:52 +00:00 |
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cvt16.ll
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…
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cvtv2f32.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
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cxx_tlscc64.ll
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…
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dag-fmf-cse.ll
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Revert "[NFC][CodeGen] Add unary FNeg tests to X86/combine-fcopysign.ll X86/dag-fmf-cse.ll X86/fast-isel-fneg.ll X86/fdiv.ll"
|
2019-06-13 19:24:38 +00:00 |
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dag-merge-fast-accesses.ll
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[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
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dag-optnone.ll
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…
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dag-rauw-cse.ll
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…
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dag-update-nodetomatch.ll
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…
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dagcombine-and-setcc.ll
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…
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dagcombine-buildvector.ll
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…
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|
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dagcombine-cse.ll
|
Recommit r358887 "[TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handling"
|
2019-05-13 04:03:35 +00:00 |
|
dagcombine-select.ll
|
…
|
|
|
dagcombine-shifts.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
dagcombine-tokenfactor-limit-crash.ll
|
Recommit r360171: [DAGCombiner] Avoid creating large tokenfactors in visitTokenFactor.
|
2019-06-03 01:30:19 +00:00 |
|
dagcombine-unsafe-math.ll
|
Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control
|
2019-07-31 21:57:28 +00:00 |
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darwin-bzero.ll
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…
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darwin-no-dead-strip.ll
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…
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darwin-preemption.ll
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…
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darwin-quote.ll
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…
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darwin-tls.ll
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…
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dbg-baseptr.ll
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…
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dbg-changes-codegen-branch-folding.ll
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…
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dbg-changes-codegen-branch-folding2.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
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dbg-changes-codegen.ll
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…
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dbg-combine.ll
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…
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dbg-line-0-no-discriminator.ll
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…
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dbg-value-superreg-copy.mir
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…
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debug-loclists.ll
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…
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debug-nodebug-crash.ll
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…
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debuginfo-locations-dce.ll
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…
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debugloc-argsize.ll
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…
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debugloc-no-line-0.ll
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[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
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deopt-bundles.ll
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…
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deopt-intrinsic-cconv.ll
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…
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deopt-intrinsic.ll
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…
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disable-tail-calls.ll
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…
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discontiguous-loops.ll
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…
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discriminate-mem-ops-missing-info.ll
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[llvm] X86DiscriminateMemOps: insert debug info when missing
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2019-05-10 00:12:51 +00:00 |
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discriminate-mem-ops-skip-pfetch.ll
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Skip over prefetches
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2019-05-10 21:27:55 +00:00 |
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discriminate-mem-ops.ll
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…
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div-rem-pair-recomposition-signed.ll
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[NFC][CodeGen][X86][AArch64] div-rem pair reconstruction tests (PR42673)
|
2019-07-25 16:39:57 +00:00 |
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div-rem-pair-recomposition-unsigned.ll
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[NFC][CodeGen][X86][AArch64] div-rem pair reconstruction tests (PR42673)
|
2019-07-25 16:39:57 +00:00 |
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div-rem-simplify.ll
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…
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div8.ll
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…
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divide-by-constant.ll
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…
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divide-windows-itanium.ll
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…
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divrem.ll
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…
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divrem8_ext.ll
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…
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dllexport-x86_64.ll
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…
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dllexport.ll
|
…
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dllimport-x86_64.ll
|
…
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dllimport.ll
|
…
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|
dollar-name.ll
|
…
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domain-reassignment-implicit-def.ll
|
…
|
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|
domain-reassignment-test.ll
|
…
|
|
|
domain-reassignment.mir
|
[X86] Regenerate checks for domain-reassignment.mir
|
2019-04-15 05:22:47 +00:00 |
|
dont-trunc-store-double-to-float.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
dropped_constructor.ll
|
…
|
|
|
dtor-priority-coff.ll
|
Fixed placement of llvm.global_dtors on Windows.
|
2019-08-19 21:07:03 +00:00 |
|
dwarf-comp-dir.ll
|
…
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dwarf-eh-prepare.ll
|
…
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dwarf-headers.ll
|
…
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dwarf-split-line-1.ll
|
…
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dwarf-split-line-2.ll
|
…
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|
dyn-stackalloc.ll
|
…
|
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|
dyn_alloca_aligned.ll
|
…
|
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|
dynamic-alloca-in-entry.ll
|
…
|
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|
dynamic-alloca-lifetime.ll
|
…
|
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dynamic-allocas-VLAs.ll
|
…
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dynamic-regmask.ll
|
…
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early-cfi-sections.ll
|
…
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early-ifcvt-crash.ll
|
…
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early-ifcvt.ll
|
…
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eh-frame-unreachable.ll
|
…
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eh-label.ll
|
…
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eh-nolandingpads.ll
|
…
|
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eh-null-personality.ll
|
…
|
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|
eh-unknown.ll
|
…
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|
|
eh_frame.ll
|
…
|
|
|
eip-addressing-i386.ll
|
…
|
|
|
element-wise-atomic-memory-intrinsics.ll
|
[Tests] Yet more combination of tests for unordered.atomic memset
|
2019-05-07 17:45:52 +00:00 |
|
elf-associated.ll
|
Revert r367501 "Create unique, but identically-named ELF sections..."
|
2019-08-07 20:45:23 +00:00 |
|
elf-comdat.ll
|
…
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|
elf-comdat2.ll
|
…
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|
emit-big-cst.ll
|
…
|
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|
empty-function.ll
|
Revert [Windows] Disable TrapUnreachable for Win64, add SEH_NoReturn
|
2019-09-03 22:27:27 +00:00 |
|
empty-functions.ll
|
…
|
|
|
empty-struct-return-type.ll
|
…
|
|
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emutls-pic.ll
|
…
|
|
|
emutls-pie.ll
|
…
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|
|
emutls.ll
|
…
|
|
|
emutls_generic.ll
|
…
|
|
|
enqcmd-intrinsics.ll
|
[X86] Add ENQCMD instructions
|
2019-05-30 03:59:16 +00:00 |
|
epilogue-cfi-fp.ll
|
…
|
|
|
epilogue-cfi-no-fp.ll
|
…
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epilogue.ll
|
…
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|
equiv_with_fndef.ll
|
…
|
|
|
equiv_with_vardef.ll
|
…
|
|
|
evex-to-vex-compress.mir
|
[X86] Remove MOVDI2SSrm/MOV64toSDrm/MOVSS2DImr/MOVSDto64mr CodeGenOnly instructions.
|
2019-06-18 03:23:15 +00:00 |
|
exception-label.ll
|
…
|
|
|
exedeps-movq.ll
|
…
|
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|
exedepsfix-broadcast.ll
|
…
|
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|
expand-integer-x86_64-intrinsic-error.ll
|
…
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|
expand-opaque-const.ll
|
…
|
|
|
expand-post-ra-pseudo.mir
|
…
|
|
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expand-vr64-gr64-copy.mir
|
…
|
|
|
extend-set-cc-uses-dbg.ll
|
…
|
|
|
extend.ll
|
…
|
|
|
extended-fma-contraction.ll
|
…
|
|
|
extern_weak.ll
|
[COFF] Use COFF stubs for extern_weak functions
|
2019-05-07 23:06:21 +00:00 |
|
extmul64.ll
|
…
|
|
|
extmul128.ll
|
…
|
|
|
extract-bits.ll
|
[X86] X86DAGToDAGISel::matchBitExtract(): pattern c: truncation awareness
|
2019-06-26 12:19:47 +00:00 |
|
extract-combine.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
extract-concat.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
extract-extract.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
extract-fp.ll
|
[X86] Combine fminnum/fmaxnum with non-nan operand to fmin/fmax
|
2019-05-25 16:44:29 +00:00 |
|
extract-insert.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
extract-lowbits.ll
|
[X86] X86DAGToDAGISel::matchBitExtract(): pattern c: truncation awareness
|
2019-06-26 12:19:47 +00:00 |
|
extract-store.ll
|
[X86] Enable fp128 as a legal type with SSE1 rather than with MMX.
|
2019-09-02 20:16:30 +00:00 |
|
extractelement-fp.ll
|
[DAGCombiner] try to move bitcast after extract_subvector
|
2019-05-12 14:43:20 +00:00 |
|
extractelement-from-arg.ll
|
…
|
|
|
extractelement-index.ll
|
…
|
|
|
extractelement-legalization-cycle.ll
|
…
|
|
|
extractelement-legalization-store-ordering.ll
|
…
|
|
|
extractelement-load.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
extractelement-shuffle.ll
|
…
|
|
|
extractps.ll
|
…
|
|
|
f16c-intrinsics-fast-isel.ll
|
…
|
|
|
f16c-intrinsics.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
fabs.ll
|
…
|
|
|
fadd-combines.ll
|
[DAGCombiner] exclude x*2.0 from normal negation profitability rules
|
2019-08-09 21:37:32 +00:00 |
|
fast-cc-callee-pops.ll
|
…
|
|
|
fast-cc-merge-stack-adj.ll
|
…
|
|
|
fast-cc-pass-in-regs.ll
|
…
|
|
|
fast-isel-abort-warm.ll
|
…
|
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|
fast-isel-agg-constant.ll
|
…
|
|
|
fast-isel-args-fail.ll
|
…
|
|
|
fast-isel-args-fail2.ll
|
…
|
|
|
fast-isel-args.ll
|
…
|
|
|
fast-isel-atomic.ll
|
…
|
|
|
fast-isel-avoid-unnecessary-pic-base.ll
|
…
|
|
|
fast-isel-bail.ll
|
…
|
|
|
fast-isel-bc.ll
|
…
|
|
|
fast-isel-bitcasts-avx.ll
|
…
|
|
|
fast-isel-bitcasts-avx512.ll
|
…
|
|
|
fast-isel-bitcasts.ll
|
…
|
|
|
fast-isel-branch_weights.ll
|
…
|
|
|
fast-isel-call-bool.ll
|
…
|
|
|
fast-isel-call-cleanup.ll
|
…
|
|
|
fast-isel-call.ll
|
…
|
|
|
fast-isel-cmp-branch.ll
|
…
|
|
|
fast-isel-cmp-branch2.ll
|
…
|
|
|
fast-isel-cmp-branch3.ll
|
…
|
|
|
fast-isel-cmp.ll
|
…
|
|
|
fast-isel-constant.ll
|
…
|
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|
fast-isel-constpool.ll
|
…
|
|
|
fast-isel-constrain-store-indexreg.ll
|
…
|
|
|
fast-isel-deadcode.ll
|
…
|
|
|
fast-isel-divrem-x86-64.ll
|
…
|
|
|
fast-isel-divrem.ll
|
…
|
|
|
fast-isel-double-half-convertion.ll
|
…
|
|
|
fast-isel-emutls.ll
|
…
|
|
|
fast-isel-expect.ll
|
…
|
|
|
fast-isel-extract.ll
|
…
|
|
|
fast-isel-float-half-convertion.ll
|
…
|
|
|
fast-isel-fneg-kill.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
fast-isel-fneg.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/combine-fcopysign.ll X86/dag-fmf-cse.ll X86/fast-isel-fneg.ll X86/fdiv.ll"
|
2019-06-13 19:24:38 +00:00 |
|
fast-isel-fold-mem.ll
|
…
|
|
|
fast-isel-fptrunc-fpext.ll
|
…
|
|
|
fast-isel-gc-intrinsics.ll
|
…
|
|
|
fast-isel-gep.ll
|
…
|
|
|
fast-isel-gv.ll
|
…
|
|
|
fast-isel-i1.ll
|
…
|
|
|
fast-isel-int-float-conversion-x86-64.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
fast-isel-int-float-conversion.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
fast-isel-load-i1.ll
|
…
|
|
|
fast-isel-mem.ll
|
…
|
|
|
fast-isel-movsbl-indexreg.ll
|
…
|
|
|
fast-isel-nontemporal.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
fast-isel-noplt-pic.ll
|
…
|
|
|
fast-isel-ret-ext.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
fast-isel-select-cmov.ll
|
…
|
|
|
fast-isel-select-cmov2.ll
|
…
|
|
|
fast-isel-select-cmp.ll
|
…
|
|
|
fast-isel-select-pseudo-cmov.ll
|
[X86] Add CMOV_FR32X/CMOV_FR64X pseudo instructions. Use them in fast isel to fix a machine verifier error after adding test cases.
|
2019-05-11 16:00:28 +00:00 |
|
fast-isel-select-sse.ll
|
…
|
|
|
fast-isel-select.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
fast-isel-sext-zext.ll
|
…
|
|
|
fast-isel-sext.ll
|
…
|
|
|
fast-isel-shift.ll
|
…
|
|
|
fast-isel-sse12-fptoint.ll
|
…
|
|
|
fast-isel-stackcheck.ll
|
…
|
|
|
fast-isel-store.ll
|
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
|
2019-07-11 14:45:03 +00:00 |
|
fast-isel-tailcall.ll
|
…
|
|
|
fast-isel-tls.ll
|
…
|
|
|
fast-isel-trunc-kill-subreg.ll
|
…
|
|
|
fast-isel-uint-float-conversion-x86-64.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
fast-isel-uint-float-conversion.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
fast-isel-vecload.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
fast-isel-x32.ll
|
…
|
|
|
fast-isel-x86-64.ll
|
…
|
|
|
fast-isel-x86.ll
|
…
|
|
|
fast-isel.ll
|
…
|
|
|
fastcall-correct-mangling.ll
|
…
|
|
|
fastcc-2.ll
|
…
|
|
|
fastcc-byval.ll
|
…
|
|
|
fastcc-sret.ll
|
…
|
|
|
fastcc.ll
|
…
|
|
|
fastcc3struct.ll
|
…
|
|
|
fastisel-gep-promote-before-add.ll
|
…
|
|
|
fastisel-softfloat.ll
|
…
|
|
|
fastmath-float-half-conversion.ll
|
…
|
|
|
fcmove.ll
|
…
|
|
|
fcmp-constant.ll
|
[SelectionDAG] Add fcmp UNDEF handling to SelectionDAG::FoldSetCC
|
2019-04-05 14:56:21 +00:00 |
|
fdiv-combine-vec.ll
|
[DAGCombiner] try repeated fdiv divisor transform before building estimate (2nd try)
|
2019-05-02 15:02:08 +00:00 |
|
fdiv-combine.ll
|
adding more fmf propagation for selects plus updated tests
|
2019-06-15 04:53:51 +00:00 |
|
fdiv.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/combine-fcopysign.ll X86/dag-fmf-cse.ll X86/fast-isel-fneg.ll X86/fdiv.ll"
|
2019-06-13 19:24:38 +00:00 |
|
fentry-insertion.ll
|
…
|
|
|
field-extract-use-trunc.ll
|
…
|
|
|
fildll.ll
|
…
|
|
|
file-directive.ll
|
[llvm-readobj] Change -long-option to --long-option in tests. NFC
|
2019-05-01 05:27:20 +00:00 |
|
file-source-filename.ll
|
…
|
|
|
finite-libcalls.ll
|
…
|
|
|
fixed-stack-di-mir.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
fixup-bw-copy.ll
|
[DAGCombiner] Remove mostly redundant calls to AddToWorklist
|
2019-08-21 18:51:08 +00:00 |
|
fixup-bw-copy.mir
|
…
|
|
|
fixup-bw-inst.ll
|
…
|
|
|
fixup-bw-inst.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
fixup-lea.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
flags-copy-lowering.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
float-asmprint.ll
|
…
|
|
|
float-conv-elim.ll
|
…
|
|
|
floor-soft-float.ll
|
…
|
|
|
fltused.ll
|
…
|
|
|
fltused_function_pointer.ll
|
…
|
|
|
fltused_math.ll
|
…
|
|
|
fma-commute-x86.ll
|
…
|
|
|
fma-do-not-commute.ll
|
…
|
|
|
fma-fneg-combine-2.ll
|
[DAGCombine] GetNegatedExpression - add FMA\FMAD support
|
2019-08-23 10:49:46 +00:00 |
|
fma-fneg-combine.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma-fneg-combine.ll"
|
2019-06-13 19:24:41 +00:00 |
|
fma-intrinsics-canonical.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to X86/fma-intrinsics-canonical.ll"
|
2019-06-13 19:24:47 +00:00 |
|
fma-intrinsics-fast-isel.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to some X86/ and XCore/ tests."
|
2019-06-13 19:24:51 +00:00 |
|
fma-intrinsics-phi-213-to-231.ll
|
…
|
|
|
fma-intrinsics-x86-upgrade.ll
|
…
|
|
|
fma-intrinsics-x86.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma-intrinsics-x86.ll"
|
2019-06-13 19:24:57 +00:00 |
|
fma-phi-213-to-231.ll
|
…
|
|
|
fma-scalar-combine.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma-scalar-combine.ll"
|
2019-06-13 19:25:00 +00:00 |
|
fma-scalar-memfold.ll
|
…
|
|
|
fma.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
fma4-commute-x86.ll
|
…
|
|
|
fma4-fneg-combine.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma4-fneg-combine.ll"
|
2019-06-13 19:25:03 +00:00 |
|
fma4-intrinsics-x86-upgrade.ll
|
…
|
|
|
fma4-intrinsics-x86.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma4-intrinsics-x86.ll"
|
2019-06-13 19:24:54 +00:00 |
|
fma4-intrinsics-x86_64-folded-load.ll
|
…
|
|
|
fma4-scalar-memfold.ll
|
…
|
|
|
fma_patterns.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma_patterns.ll"
|
2019-06-13 19:25:06 +00:00 |
|
fma_patterns_wide.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to X86/fma_patterns_wide.ll"
|
2019-06-13 19:25:09 +00:00 |
|
fmaddsub-combine.ll
|
…
|
|
|
fmaxnum.ll
|
[X86] Combine fminnum/fmaxnum with non-nan operand to fmin/fmax
|
2019-05-25 16:44:29 +00:00 |
|
fmf-flags.ll
|
…
|
|
|
fmf-propagation.ll
|
Propagate fmf for setcc in SDAG for select folds
|
2019-06-03 21:53:26 +00:00 |
|
fminnum.ll
|
[X86] Combine fminnum/fmaxnum with non-nan operand to fmin/fmax
|
2019-05-25 16:44:29 +00:00 |
|
fmsubadd-combine.ll
|
…
|
|
|
fmul-combines.ll
|
Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control
|
2019-07-31 21:57:28 +00:00 |
|
fnabs.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to fmul-combines.ll fnabs.ll"
|
2019-06-13 19:25:12 +00:00 |
|
fold-add.ll
|
…
|
|
|
fold-and-shift-x86_64.ll
|
[X86] Teach foldMaskedShiftToScaledMask to look through an any_extend from i32 to i64 between the and & shl
|
2019-04-10 21:42:08 +00:00 |
|
fold-and-shift.ll
|
[X86] Prevent folding a load into an AND if that AND is really a ZEXT_INREG that should use movzx.
|
2019-04-24 19:28:38 +00:00 |
|
fold-call-2.ll
|
…
|
|
|
fold-call-3.ll
|
[X86] If PreprocessISelDAG reorders a load before a call, make sure we remove dead nodes from the graph
|
2019-04-30 17:56:47 +00:00 |
|
fold-call-oper.ll
|
…
|
|
|
fold-call.ll
|
…
|
|
|
fold-imm.ll
|
…
|
|
|
fold-load-binops.ll
|
[X86] Add load folding isel patterns to scalar_math_patterns and AVX512_scalar_math_fp_patterns.
|
2019-06-11 04:30:53 +00:00 |
|
fold-load-unops.ll
|
[X86] Teach selectScalarSSELoad to not narrow volatile loads.
|
2019-06-27 05:51:56 +00:00 |
|
fold-load-vec.ll
|
…
|
|
|
fold-load.ll
|
…
|
|
|
fold-mul-lohi.ll
|
…
|
|
|
fold-pcmpeqd-1.ll
|
…
|
|
|
fold-pcmpeqd-2.ll
|
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
|
2019-06-13 13:56:19 +00:00 |
|
fold-push.ll
|
…
|
|
|
fold-rmw-ops.ll
|
…
|
|
|
fold-sext-trunc.ll
|
…
|
|
|
fold-tied-op.ll
|
Revert rL357745: [SelectionDAG] Compute known bits of CopyFromReg
|
2019-04-10 18:00:41 +00:00 |
|
fold-vector-bv-crash.ll
|
…
|
|
|
fold-vector-sext-crash.ll
|
…
|
|
|
fold-vector-sext-crash2.ll
|
…
|
|
|
fold-vector-sext-zext.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
fold-vector-shl-crash.ll
|
…
|
|
|
fold-vector-shuffle-crash.ll
|
…
|
|
|
fold-vector-trunc-sitofp.ll
|
…
|
|
|
fold-vex.ll
|
…
|
|
|
fold-xmm-zero.ll
|
…
|
|
|
fold-zext-trunc.ll
|
…
|
|
|
fops-windows-itanium.ll
|
…
|
|
|
force-align-stack-alloca.ll
|
…
|
|
|
force-align-stack.ll
|
…
|
|
|
fp-arith.ll
|
…
|
|
|
fp-cvt.ll
|
…
|
|
|
fp-double-rounding.ll
|
…
|
|
|
fp-elim-and-no-fp-elim.ll
|
…
|
|
|
fp-elim.ll
|
…
|
|
|
fp-fast.ll
|
Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control
|
2019-07-31 21:57:28 +00:00 |
|
fp-fold.ll
|
Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control
|
2019-07-31 21:57:28 +00:00 |
|
fp-immediate-shorten.ll
|
…
|
|
|
fp-in-intregs.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to fp-fast.ll fp-fold.ll fp-in-intregs.ll fp-stack-compare-cmov.ll fp-stack-compare.ll fsxor-alignment.ll"
|
2019-06-13 19:25:16 +00:00 |
|
fp-intrinsics.ll
|
[FPEnv] Add fptosi and fptoui constrained intrinsics.
|
2019-08-28 16:33:36 +00:00 |
|
fp-load-trunc.ll
|
…
|
|
|
fp-logic-replace.ll
|
…
|
|
|
fp-logic.ll
|
…
|
|
|
fp-select-cmp-and.ll
|
…
|
|
|
fp-stack-2results.ll
|
[NFC] This is a test for the commit access.
|
2019-05-06 08:31:18 +00:00 |
|
fp-stack-O0-crash.ll
|
…
|
|
|
fp-stack-O0.ll
|
…
|
|
|
fp-stack-compare-cmov.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to fp-fast.ll fp-fold.ll fp-in-intregs.ll fp-stack-compare-cmov.ll fp-stack-compare.ll fsxor-alignment.ll"
|
2019-06-13 19:25:16 +00:00 |
|
fp-stack-compare.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to fp-fast.ll fp-fold.ll fp-in-intregs.ll fp-stack-compare-cmov.ll fp-stack-compare.ll fsxor-alignment.ll"
|
2019-06-13 19:25:16 +00:00 |
|
fp-stack-direct-ret.ll
|
…
|
|
|
fp-stack-ret-conv.ll
|
…
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fp-stack-ret-store.ll
|
…
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|
fp-stack-ret.ll
|
…
|
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fp-stack-retcopy.ll
|
…
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fp-stack-set-st1.ll
|
…
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|
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fp-stack.ll
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…
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fp-trunc.ll
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…
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fp-undef.ll
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…
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fp-une-cmp.ll
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…
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fp2sint.ll
|
…
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|
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fp128-calling-conv.ll
|
…
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|
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fp128-cast.ll
|
[X86] Enable fp128 as a legal type with SSE1 rather than with MMX.
|
2019-09-02 20:16:30 +00:00 |
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fp128-compare.ll
|
…
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|
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fp128-extract.ll
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…
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fp128-g.ll
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…
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fp128-i128.ll
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…
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|
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fp128-libcalls.ll
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…
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|
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fp128-load.ll
|
…
|
|
|
fp128-select.ll
|
[X86] Enable fp128 as a legal type with SSE1 rather than with MMX.
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2019-09-02 20:16:30 +00:00 |
|
fp128-store.ll
|
…
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|
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fp_constant_op.ll
|
…
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|
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fp_load_cast_fold.ll
|
…
|
|
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fp_load_fold.ll
|
…
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|
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fpcmp-soft-fp.ll
|
…
|
|
|
fpstack-debuginstr-kill.ll
|
…
|
|
|
fptosi-constant.ll
|
…
|
|
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frame-base.ll
|
…
|
|
|
frame-lowering-debug-intrinsic-2.ll
|
…
|
|
|
frame-lowering-debug-intrinsic.ll
|
…
|
|
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frame-order.ll
|
…
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frameaddr.ll
|
…
|
|
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frameregister.ll
|
…
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|
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frem-msvc32.ll
|
…
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|
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fsgsbase.ll
|
…
|
|
|
fshl.ll
|
…
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|
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fshr.ll
|
…
|
|
|
fsxor-alignment.ll
|
Revert "[NFC][CodeGen] Add unary fneg tests to fp-fast.ll fp-fold.ll fp-in-intregs.ll fp-stack-compare-cmov.ll fp-stack-compare.ll fsxor-alignment.ll"
|
2019-06-13 19:25:16 +00:00 |
|
ftrunc.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
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full-lsr.ll
|
…
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|
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funclet-layout.ll
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Revert [Windows] Disable TrapUnreachable for Win64, add SEH_NoReturn
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2019-09-03 22:27:27 +00:00 |
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function-alias.ll
|
…
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|
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function-subtarget-features-2.ll
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…
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function-subtarget-features.ll
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…
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funnel-shift-rot.ll
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…
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funnel-shift.ll
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…
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|
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ga-offset.ll
|
…
|
|
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ga-offset2.ll
|
…
|
|
|
gather-addresses.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
gcc_except_table.ll
|
[X86] Print register names in .seh_* directives
|
2019-08-30 21:23:05 +00:00 |
|
gcc_except_table_functions.ll
|
…
|
|
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gep-expanded-vector.ll
|
…
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|
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getelementptr.ll
|
…
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gfni-intrinsics.ll
|
…
|
|
|
ghc-cc.ll
|
…
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|
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ghc-cc64.ll
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…
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|
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global-access-pie-copyrelocs.ll
|
…
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global-access-pie.ll
|
…
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global-fill.ll
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…
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global-sections-comdat.ll
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…
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global-sections-tls.ll
|
…
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global-sections.ll
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…
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gnu-seh-nolpads.ll
|
…
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gpr-to-mask.ll
|
…
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greedy_regalloc_bad_eviction_sequence.ll
|
…
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gs-fold.ll
|
…
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|
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h-register-addressing-32.ll
|
…
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h-register-addressing-64.ll
|
…
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h-register-store.ll
|
…
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h-registers-0.ll
|
…
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h-registers-1.ll
|
…
|
|
|
h-registers-2.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
h-registers-3.ll
|
…
|
|
|
haddsub-2.ll
|
…
|
|
|
haddsub-3.ll
|
[x86] make sure horizontal op and broadcast types match to simplify (PR41414)
|
2019-04-24 14:05:08 +00:00 |
|
haddsub-shuf.ll
|
[X86][AVX] Add broadcast(v4f64 hadd) test
|
2019-06-13 11:42:32 +00:00 |
|
haddsub-undef.ll
|
[X86][SSE] Relax use limits for lowerAddSubToHorizontalOp (PR32433)
|
2019-05-13 16:02:45 +00:00 |
|
haddsub.ll
|
[SDAG][x86] check for relaxed math when matching an FP reduction
|
2019-08-15 12:43:15 +00:00 |
|
half.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
handle-move.ll
|
…
|
|
|
hhvm-cc.ll
|
…
|
|
|
hidden-vis-2.ll
|
…
|
|
|
hidden-vis-3.ll
|
…
|
|
|
hidden-vis-4.ll
|
…
|
|
|
hidden-vis-pic.ll
|
…
|
|
|
hidden-vis.ll
|
…
|
|
|
hipe-cc.ll
|
…
|
|
|
hipe-cc64.ll
|
…
|
|
|
hipe-prologue.ll
|
…
|
|
|
hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
|
[Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 fold
|
2019-07-24 22:57:22 +00:00 |
|
hoist-and-by-const-from-shl-in-eqcmp-zero.ll
|
[Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 fold
|
2019-07-24 22:57:22 +00:00 |
|
hoist-common.ll
|
…
|
|
|
hoist-invariant-load.ll
|
…
|
|
|
hoist-spill-lpad.ll
|
…
|
|
|
hoist-spill.ll
|
…
|
|
|
horizontal-reduce-smax.ll
|
[X86][SSE] Enable min/max partial reduction
|
2019-08-06 11:00:34 +00:00 |
|
horizontal-reduce-smin.ll
|
[X86][SSE] Enable min/max partial reduction
|
2019-08-06 11:00:34 +00:00 |
|
horizontal-reduce-umax.ll
|
[X86][SSE] Enable min/max partial reduction
|
2019-08-06 11:00:34 +00:00 |
|
horizontal-reduce-umin.ll
|
[X86][SSE] Enable min/max partial reduction
|
2019-08-06 11:00:34 +00:00 |
|
horizontal-shuffle-demanded.ll
|
[X86][SSE] SimplifyDemandedBits - call PEXTRB/PEXTRW SimplifyDemandedVectorElts as well.
|
2019-05-11 21:35:50 +00:00 |
|
horizontal-shuffle.ll
|
…
|
|
|
huge-stack-offset.ll
|
…
|
|
|
huge-stack-offset2.ll
|
…
|
|
|
i1narrowfail.ll
|
…
|
|
|
i2k.ll
|
…
|
|
|
i16lshr8pat.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
i64-mem-copy.ll
|
…
|
|
|
i64-to-float.ll
|
[X86][AVX] X86ISD::PERMV/PERMV3 node types can never fold index ops
|
2019-04-16 19:18:53 +00:00 |
|
i128-add.ll
|
[X86] Delay combineIncDecVector until after op legalization.
|
2019-08-26 22:17:54 +00:00 |
|
i128-and-beyond.ll
|
…
|
|
|
i128-immediate.ll
|
…
|
|
|
i128-mul.ll
|
[SDAG] Fold umul_lohi with 0 or 1 multiplicand
|
2019-08-25 08:04:22 +00:00 |
|
i128-ret.ll
|
…
|
|
|
i128-sdiv.ll
|
…
|
|
|
i256-add.ll
|
…
|
|
|
i386-setjmp-pic.ll
|
…
|
|
|
i386-shrink-wrapping.ll
|
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
|
2019-06-13 13:56:19 +00:00 |
|
i386-tlscall-fastregalloc.ll
|
…
|
|
|
i486-fence-loop.ll
|
…
|
|
|
i686-win-shrink-wrapping.ll
|
…
|
|
|
iabs.ll
|
…
|
|
|
icall-branch-funnel.ll
|
[CodeGen] Make branch funnels pass the machine verifier
|
2019-07-03 17:16:45 +00:00 |
|
icmp-opt.ll
|
…
|
|
|
ident-metadata.ll
|
…
|
|
|
ifunc-asm.ll
|
[AsmPrinter] Delete redundant .type foo, @function when emitting an ifunc
|
2019-08-14 10:30:27 +00:00 |
|
illegal-bitfield-loadstore.ll
|
…
|
|
|
illegal-insert.ll
|
…
|
|
|
illegal-vector-args-return.ll
|
…
|
|
|
immediate_merging.ll
|
…
|
|
|
immediate_merging64.ll
|
…
|
|
|
implicit-faultmap.ll
|
…
|
|
|
implicit-null-check-negative.ll
|
…
|
|
|
implicit-null-check.ll
|
…
|
|
|
implicit-null-checks.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
implicit-null-chk-reg-rewrite.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
implicit-use-spill.mir
|
…
|
|
|
imul-lea-2.ll
|
…
|
|
|
imul-lea.ll
|
…
|
|
|
imul.ll
|
[SDAG] Fold umul_lohi with 0 or 1 multiplicand
|
2019-08-25 08:04:22 +00:00 |
|
inalloca-ctor.ll
|
…
|
|
|
inalloca-invoke.ll
|
…
|
|
|
inalloca-regparm.ll
|
…
|
|
|
inalloca-stdcall.ll
|
…
|
|
|
inalloca.ll
|
…
|
|
|
inc-of-add.ll
|
[NFC][Codegen][X86][AArch64][ARM][PowerPC] Recommit: Add test coverage for "add-of-inc" vs "sub-of-not"
|
2019-07-02 16:48:49 +00:00 |
|
inconsistent_landingpad.ll
|
…
|
|
|
indirect-branch-tracking-r2.ll
|
[X86] [CET] Deal with return-twice function such as vfork, setjmp when
|
2019-05-22 00:50:21 +00:00 |
|
indirect-branch-tracking.ll
|
…
|
|
|
indirect-hidden.ll
|
…
|
|
|
init-priority.ll
|
[IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format
|
2019-05-15 02:35:32 +00:00 |
|
inline-0bh.ll
|
…
|
|
|
inline-asm-2addr.ll
|
…
|
|
|
inline-asm-A-constraint.ll
|
…
|
|
|
inline-asm-R-constraint.ll
|
…
|
|
|
inline-asm-avx-v-constraint-32bit.ll
|
…
|
|
|
inline-asm-avx-v-constraint.ll
|
…
|
|
|
inline-asm-avx512f-v-constraint.ll
|
…
|
|
|
inline-asm-avx512f-x-constraint.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
inline-asm-avx512vl-v-constraint-32bit.ll
|
…
|
|
|
inline-asm-avx512vl-v-constraint.ll
|
…
|
|
|
inline-asm-bad-constraint-n.ll
|
Emit diagnostic if an inline asm constraint requires an immediate
|
2019-08-03 05:52:47 +00:00 |
|
inline-asm-bad-modifier.ll
|
…
|
|
|
inline-asm-default-clobbers.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
inline-asm-duplicated-constraint.ll
|
…
|
|
|
inline-asm-e-constraint.ll
|
Emit diagnostic if an inline asm constraint requires an immediate
|
2019-08-03 05:52:47 +00:00 |
|
inline-asm-error.ll
|
…
|
|
|
inline-asm-flag-clobber.ll
|
…
|
|
|
inline-asm-flag-output.ll
|
…
|
|
|
inline-asm-fpstack.ll
|
…
|
|
|
inline-asm-h.ll
|
…
|
|
|
inline-asm-i-constraint-i1.ll
|
…
|
|
|
inline-asm-imm-out-of-range.ll
|
Emit diagnostic if an inline asm constraint requires an immediate
|
2019-08-03 05:52:47 +00:00 |
|
inline-asm-modifier-V.ll
|
…
|
|
|
inline-asm-modifier-c.ll
|
[AsmPrinter] refactor to support %c w/ GlobalAddress'
|
2019-04-26 18:45:04 +00:00 |
|
inline-asm-modifier-n.ll
|
…
|
|
|
inline-asm-modifier-q.ll
|
…
|
|
|
inline-asm-mrv.ll
|
…
|
|
|
inline-asm-multilevel-gep.ll
|
[TargetLowering] Handle multi depth GEPs w/ inline asm constraints
|
2019-05-13 17:27:44 +00:00 |
|
inline-asm-n-constraint.ll
|
Emit diagnostic if an inline asm constraint requires an immediate
|
2019-08-03 05:52:47 +00:00 |
|
inline-asm-out-regs.ll
|
…
|
|
|
inline-asm-pic.ll
|
…
|
|
|
inline-asm-ptr-cast.ll
|
…
|
|
|
inline-asm-q-regs.ll
|
…
|
|
|
inline-asm-sp-clobber-memcpy.ll
|
…
|
|
|
inline-asm-stack-realign.ll
|
…
|
|
|
inline-asm-stack-realign2.ll
|
…
|
|
|
inline-asm-stack-realign3.ll
|
…
|
|
|
inline-asm-tied.ll
|
…
|
|
|
inline-asm-x-scalar.ll
|
…
|
|
|
inline-asm.ll
|
…
|
|
|
inline-sse.ll
|
…
|
|
|
inlineasm-sched-bug.ll
|
Stricter check for the memory access.
|
2019-07-27 18:57:59 +00:00 |
|
inreg.ll
|
…
|
|
|
ins_split_regalloc.ll
|
…
|
|
|
ins_subreg_coalesce-1.ll
|
…
|
|
|
ins_subreg_coalesce-2.ll
|
…
|
|
|
ins_subreg_coalesce-3.ll
|
…
|
|
|
insert-into-constant-vector.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
insert-loaded-scalar.ll
|
…
|
|
|
insert-positions.ll
|
…
|
|
|
insert-prefetch-inline.afdo
|
…
|
|
|
insert-prefetch-inline.ll
|
…
|
|
|
insert-prefetch-invalid-instr.afdo
|
…
|
|
|
insert-prefetch-invalid-instr.ll
|
…
|
|
|
insert-prefetch-other.afdo
|
…
|
|
|
insert-prefetch.afdo
|
…
|
|
|
insert-prefetch.ll
|
…
|
|
|
insertelement-copytoregs.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
insertelement-duplicates.ll
|
…
|
|
|
insertelement-legalize.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
insertelement-ones.ll
|
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
|
2019-07-06 17:59:51 +00:00 |
|
insertelement-shuffle.ll
|
[X86] Teach lowerV4I32Shuffle to only use broadcasts if the mask has more than one undef element. Prioritize shifts over broadcast in lowerV8I16Shuffle.
|
2019-08-19 18:15:50 +00:00 |
|
insertelement-var-index.ll
|
…
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|
|
insertelement-zero.ll
|
[X86][AVX] Split VZEXT_MOVL ymm/zmm if the upper elements are not demanded.
|
2019-05-12 15:16:29 +00:00 |
|
insertps-O0-bug.ll
|
…
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|
|
insertps-combine.ll
|
[X86] XFormVExtractWithShuffleIntoLoad - handle shuffle mask scaling
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2019-08-13 11:11:42 +00:00 |
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insertps-from-constantpool.ll
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…
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insertps-unfold-load-bug.ll
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…
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instr-symbols.mir
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…
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int-intrinsic.ll
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…
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intersect-fma-fmf.ll
|
…
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interval-update-remat.ll
|
…
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invalid-liveness.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
invalid-shift-immediate.ll
|
…
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|
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invpcid-intrinsic.ll
|
…
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|
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ipra-inline-asm.ll
|
RegUsageInfoCollector: Skip AMDGPU entry point functions
|
2019-07-05 23:33:43 +00:00 |
|
ipra-local-linkage.ll
|
…
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|
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ipra-reg-alias.ll
|
…
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|
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ipra-reg-usage.ll
|
RegUsageInfoCollector: Skip AMDGPU entry point functions
|
2019-07-05 23:33:43 +00:00 |
|
ipra-transform.ll
|
…
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is-constant.ll
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…
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isel-optnone.ll
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…
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isel-sink.ll
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…
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isel-sink2.ll
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…
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isel-sink3.ll
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…
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isint.ll
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…
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isnan.ll
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…
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|
|
isnan2.ll
|
…
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|
|
ispositive.ll
|
…
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|
|
jump_sign.ll
|
[X86] Merge negated ISD::SUB nodes into X86ISD::SUB equivalent (PR40483)
|
2019-07-11 15:56:33 +00:00 |
|
known-bits-vector.ll
|
[x86] try to keep FP casted+truncated+extracted vector element out of GPRs
|
2019-07-15 18:17:23 +00:00 |
|
known-bits.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
known-signbits-vector.ll
|
[x86] try to keep FP casted+truncated+extracted vector element out of GPRs
|
2019-07-15 18:17:23 +00:00 |
|
kshift.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
label-annotation.ll
|
[codeview] Fix SDNode representation of annotation labels
|
2019-05-15 21:46:05 +00:00 |
|
label-heapallocsite.ll
|
Recommit "[MS] Emit S_HEAPALLOCSITE debug info in Selection DAG"
|
2019-08-07 22:49:40 +00:00 |
|
label-redefinition.ll
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…
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lack-of-signed-truncation-check.ll
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…
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lakemont.ll
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…
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large-code-model-isel.ll
|
…
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large-constants.ll
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…
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large-gep-chain.ll
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…
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large-gep-scale.ll
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…
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large-global.ll
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…
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large-pic-string.ll
|
…
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late-address-taken.ll
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…
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late-remat-update-2.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
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2019-04-05 19:28:09 +00:00 |
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late-remat-update.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
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2019-04-05 19:28:09 +00:00 |
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ldzero.ll
|
…
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lea-2.ll
|
[x86] update test checks; NFC
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2019-04-15 17:38:47 +00:00 |
|
lea-3.ll
|
[x86] update test checks; NFC
|
2019-04-15 17:38:47 +00:00 |
|
lea-4.ll
|
[x86] update test checks; NFC
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2019-04-15 17:38:47 +00:00 |
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lea-5.ll
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…
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|
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lea-dagdag.ll
|
[x86] try to widen 'shl' as part of LEA formation
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2019-04-17 22:38:51 +00:00 |
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lea-opt-cse1.ll
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…
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lea-opt-cse2.ll
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…
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lea-opt-cse3.ll
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…
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lea-opt-cse4.ll
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…
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lea-opt-memop-check-1.ll
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…
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lea-opt-memop-check-2.ll
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…
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lea-opt-with-debug.mir
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…
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lea-opt.ll
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…
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lea-recursion.ll
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…
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lea.ll
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…
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leaFixup32.mir
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[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
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2019-05-25 06:17:47 +00:00 |
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leaFixup64.mir
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[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
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2019-05-25 06:17:47 +00:00 |
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leaf-fp-elim.ll
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…
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legalize-fmp-oeq-vector-select.ll
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…
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legalize-libcalls.ll
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…
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legalize-shift-64.ll
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…
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legalize-shift.ll
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…
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legalize-shl-vec.ll
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…
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legalize-sub-zero-2.ll
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…
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legalize-sub-zero.ll
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…
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legalize-types-remapid.ll
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…
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legalize-vaarg.ll
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[SelectionDAG] Legalize vaargs that require vector splitting
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2019-06-18 12:24:02 +00:00 |
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legalizedag_vec.ll
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…
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libcall-sret.ll
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…
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licm-dominance.ll
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…
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licm-nested.ll
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…
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licm-regpressure.ll
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…
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licm-symbol.ll
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…
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lifetime-alias.ll
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[DAGCombiner] Fix invalid alias analysis.
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2019-05-13 09:07:37 +00:00 |
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limit-split-cost.mir
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[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
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2019-04-05 19:28:09 +00:00 |
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limited-prec.ll
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…
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linux-preemption.ll
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…
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lit.local.cfg
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[lit] Delete empty lines at the end of lit.local.cfg NFC
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2019-06-17 09:51:07 +00:00 |
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live-out-reg-info.ll
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…
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live-range-nosubreg.ll
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…
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liveness-local-regalloc.ll
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…
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llc-override-mcpu-mattr.ll
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…
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llc-print-machineinstrs.mir
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…
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llc-start-stop-instance.ll
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…
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llrint-conv-i32.ll
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[CodeGen] Add lrint/llrint builtins
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2019-05-28 20:47:44 +00:00 |
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llrint-conv.ll
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[CodeGen] Add lrint/llrint builtins
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2019-05-28 20:47:44 +00:00 |
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llround-conv-i32.ll
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[CodeGen] Add lround/llround builtins
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2019-05-16 13:15:27 +00:00 |
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llround-conv.ll
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[CodeGen] Add lround/llround builtins
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2019-05-16 13:15:27 +00:00 |
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load-combine-dbg.ll
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…
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load-combine.ll
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[DAGCombiner] Remove mostly redundant calls to AddToWorklist
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2019-08-21 18:51:08 +00:00 |
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load-local-v3i1.ll
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[X86] Automatically generate load-local-v3i1.ll . NFC
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2019-08-23 18:12:33 +00:00 |
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load-partial.ll
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[X86][SSE] Add shuffled load tests from PR16739
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2019-08-16 14:47:59 +00:00 |
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load-scalar-as-vector.ll
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…
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load-slice.ll
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…
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loadStore_vectorizer.ll
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…
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loc-remat.ll
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…
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local_stack_symbol_ordering.ll
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…
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localescape.ll
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[X86] Print register names in .seh_* directives
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2019-08-30 21:23:05 +00:00 |
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log2_not_readnone.ll
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…
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logical-load-fold.ll
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…
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long-setcc.ll
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…
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longlong-deadload.ll
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…
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loop-blocks.ll
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Revert [MBP] Disable aggressive loop rotate in plain mode
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2019-08-29 19:03:58 +00:00 |
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loop-hoist.ll
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…
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loop-rotate.ll
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Revert [MBP] Disable aggressive loop rotate in plain mode
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2019-08-29 19:03:58 +00:00 |
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loop-search.ll
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[Codegen] Merge tail blocks with no successors after block placement
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2019-06-13 18:11:32 +00:00 |
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loop-strength-reduce-2.ll
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…
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loop-strength-reduce-3.ll
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…
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loop-strength-reduce-crash.ll
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…
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loop-strength-reduce.ll
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…
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loop-strength-reduce2.ll
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…
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loop-strength-reduce4.ll
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…
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loop-strength-reduce5.ll
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…
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loop-strength-reduce6.ll
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…
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loop-strength-reduce7.ll
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…
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loop-strength-reduce8.ll
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…
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lower-bitcast.ll
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Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
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2019-08-07 16:33:37 +00:00 |
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lower-ptrmask.ll
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Add ptrmask intrinsic
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2019-08-15 10:12:26 +00:00 |
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lower-vec-shift-2.ll
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…
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lower-vec-shift.ll
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…
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lower-vec-shuffle-bug.ll
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…
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lrint-conv-i32.ll
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[CodeGen] Add lrint/llrint builtins
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2019-05-28 20:47:44 +00:00 |
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lrint-conv.ll
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[CodeGen] Add lrint/llrint builtins
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2019-05-28 20:47:44 +00:00 |
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lround-conv-i32.ll
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[CodeGen] Add lround/llround builtins
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2019-05-16 13:15:27 +00:00 |
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lround-conv.ll
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[CodeGen] Add lround/llround builtins
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2019-05-16 13:15:27 +00:00 |
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lrshrink.ll
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[X86] Regenerate lrshrink test checks to make D65354 diff easier
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2019-07-31 12:30:24 +00:00 |
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lsr-crash-empty-uses.ll
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…
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lsr-delayed-fold.ll
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…
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lsr-i386.ll
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…
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lsr-interesting-step.ll
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…
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lsr-loop-exit-cond.ll
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Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
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lsr-negative-stride.ll
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…
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lsr-nonaffine.ll
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…
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lsr-normalization.ll
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…
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lsr-overflow.ll
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…
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lsr-quadratic-expand.ll
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…
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lsr-redundant-addressing.ll
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…
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lsr-reuse-trunc.ll
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…
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lsr-reuse.ll
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…
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lsr-sort.ll
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…
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lsr-static-addr.ll
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[X86] Initial cleanups on the FixupLEAs pass. Separate Atom LEA creation from other LEA optimizations.
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2019-04-30 17:56:28 +00:00 |
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lsr-wrap.ll
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…
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lwp-intrinsics-x86_64.ll
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…
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lwp-intrinsics.ll
|
[X86] Add a non-ambiguous check prefix to lwp-intrinsics.ll for the case when only the feature is specified and not the CPUs.
|
2019-05-08 19:20:53 +00:00 |
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lzcnt-tzcnt.ll
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…
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|
|
lzcnt-zext-cmp.ll
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…
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|
|
lzcnt.ll
|
[X86] Regenerate LZCNT tests on x86/x32/x64 targets
|
2019-05-23 13:30:10 +00:00 |
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macCatalyst.ll
|
[macCatalyst] Use macCatalyst pretty name in .build_version darwin
|
2019-07-12 22:06:08 +00:00 |
|
machine-combiner-int-vec.ll
|
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
|
2019-07-11 14:45:03 +00:00 |
|
machine-combiner-int.ll
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…
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|
|
machine-combiner.ll
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[X86] Add avx512 command lines and test cases to machine-combiner.ll
|
2019-06-02 00:07:48 +00:00 |
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machine-copy-prop.mir
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…
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machine-cp-debug.mir
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…
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machine-cp.ll
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[Codegen] Merge tail blocks with no successors after block placement
|
2019-06-13 18:11:32 +00:00 |
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machine-cse.ll
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…
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machine-outliner-debuginfo.ll
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…
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machine-outliner-disubprogram.ll
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…
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machine-outliner-noredzone.ll
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…
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machine-outliner-tailcalls.ll
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…
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machine-outliner.ll
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…
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machine-region-info.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
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machine-sink-and-implicit-null-checks.ll
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…
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machine-sink.ll
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…
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machine-trace-metrics-crash.ll
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…
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machinesink-merge-debuginfo.ll
|
[debug-info] Make a couple of tests more robust.
|
2019-06-27 15:53:07 +00:00 |
|
machinesink-null-debuginfo.ll
|
[debug-info] Make a couple of tests more robust.
|
2019-06-27 15:53:07 +00:00 |
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macho-comdat.ll
|
…
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macho-trap.ll
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…
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madd.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
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mangle-question-mark.ll
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…
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mask-negated-bool.ll
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…
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masked-iv-safe.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
masked-iv-unsafe.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
masked_compressstore.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
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masked_expandload.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
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masked_gather.ll
|
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches.
|
2019-07-31 22:58:15 +00:00 |
|
masked_gather_scatter.ll
|
[SelectionDAGBuilder] Teach gather/scatter getUniformBase to look through vector zeroinitializer indices in addition to scalar zeroes.
|
2019-08-14 21:38:56 +00:00 |
|
masked_gather_scatter_widen.ll
|
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
|
2019-08-07 16:33:37 +00:00 |
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masked_load.ll
|
[SelectionDAG][X86] Move setcc mask splitting for mload/mstore/mgather/mscatter from DAGCombiner to the type legalizer.
|
2019-08-08 21:14:08 +00:00 |
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masked_store.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
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masked_store_trunc.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
masked_store_trunc_ssat.ll
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[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
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masked_store_trunc_usat.ll
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[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
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maskmovdqu.ll
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…
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materialize.ll
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…
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mature-mc-support.ll
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…
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mbp-false-cfg-break.ll
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…
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mcinst-avx-lowering.ll
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…
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mcinst-lowering.ll
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…
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mcu-abi.ll
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[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
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mem-intrin-base-reg.ll
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…
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mem-promote-integers.ll
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…
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membarrier.ll
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…
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memcmp-mergeexpand.ll
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Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."
|
2019-06-26 12:13:13 +00:00 |
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memcmp-minsize.ll
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…
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memcmp-optsize.ll
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Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."
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2019-06-26 12:13:13 +00:00 |
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memcmp.ll
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Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."
|
2019-06-26 12:13:13 +00:00 |
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memcpy-2.ll
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…
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memcpy-from-string.ll
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…
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memcpy-struct-by-value.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
memcpy.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
mempcpy-32.ll
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…
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mempcpy.ll
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…
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memset-2.ll
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…
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|
memset-3.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
memset-nonzero.ll
|
[x86] split more 256-bit stores of concatenated vectors
|
2019-06-05 16:40:57 +00:00 |
|
memset-sse-stack-realignment.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
memset-zero.ll
|
[Tests] Expand coverage of small memset zero idioms
|
2019-05-07 23:48:42 +00:00 |
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memset.ll
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…
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|
memset64-on-x86-32.ll
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…
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merge-consecutive-loads-128.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
merge-consecutive-loads-256.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
merge-consecutive-loads-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
merge-consecutive-stores-i1.ll
|
…
|
|
|
merge-consecutive-stores-nt.ll
|
[X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into isLoadBitCastBeneficial/isStoreBitCastBeneficial to allow X86 to bypass it
|
2019-07-09 19:55:28 +00:00 |
|
merge-consecutive-stores.ll
|
…
|
|
|
merge-sp-update-lea.ll
|
…
|
|
|
merge-sp-updates-cfi.ll
|
…
|
|
|
merge-store-constants.ll
|
…
|
|
|
merge-store-partially-alias-loads.ll
|
…
|
|
|
merge-vector-stores-scale-idx-crash.ll
|
…
|
|
|
merge_store.ll
|
[DAG] Refactor DAGCombiner::ReassociateOps
|
2019-04-29 17:50:10 +00:00 |
|
merge_store_duplicated_loads.ll
|
…
|
|
|
mfence.ll
|
…
|
|
|
midpoint-int-vec-128.ll
|
[TargetLowering] SimplifyMultipleUseDemandedBits - add VECTOR_SHUFFLE support.
|
2019-07-23 15:35:55 +00:00 |
|
midpoint-int-vec-256.ll
|
[x86] narrow extract subvector of vector select
|
2019-06-07 13:17:46 +00:00 |
|
midpoint-int-vec-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
midpoint-int.ll
|
…
|
|
|
min-legal-vector-width.ll
|
[X86] Improve codegen of v8i64->v8i16 and v16i32->v16i8 truncate with avx512vl, avx512bw, min-legal-vector-width<=256 and prefer-vector-width=256
|
2019-08-08 21:36:47 +00:00 |
|
mingw-alloca.ll
|
…
|
|
|
mingw-comdats-xdata.ll
|
…
|
|
|
mingw-comdats.ll
|
…
|
|
|
mingw-refptr.ll
|
[TargetMachine] Don't try to create COFFSTUB references on windows on non-COFF
|
2019-08-20 18:58:05 +00:00 |
|
misaligned-memset.ll
|
…
|
|
|
misched-aa-colored.ll
|
…
|
|
|
misched-aa-mmos.ll
|
…
|
|
|
misched-balance.ll
|
…
|
|
|
misched-code-difference-with-debug.ll
|
…
|
|
|
misched-copy.ll
|
…
|
|
|
misched-crash.ll
|
…
|
|
|
misched-fusion.ll
|
…
|
|
|
misched-ilp.ll
|
…
|
|
|
misched-matmul.ll
|
…
|
|
|
misched-matrix.ll
|
…
|
|
|
misched-new.ll
|
…
|
|
|
misched_phys_reg_assign_order.ll
|
Recommit r358211 "[X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87, but no SSE2"
|
2019-04-11 19:19:42 +00:00 |
|
mmx-arg-passing-x86-64.ll
|
[X86] Add custom type legalization for bitcasting mmx to v2i32/v4i16/v8i8 to use movq2dq instead of going through memory.
|
2019-08-15 18:23:37 +00:00 |
|
mmx-arg-passing.ll
|
…
|
|
|
mmx-arith.ll
|
[X86] Add custom type legalization for bitcasting mmx to v2i32/v4i16/v8i8 to use movq2dq instead of going through memory.
|
2019-08-15 18:23:37 +00:00 |
|
mmx-bitcast-fold.ll
|
…
|
|
|
mmx-bitcast.ll
|
…
|
|
|
mmx-build-vector.ll
|
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
|
2019-07-02 17:51:02 +00:00 |
|
mmx-coalescing.ll
|
…
|
|
|
mmx-copy-gprs.ll
|
…
|
|
|
mmx-cvt.ll
|
[X86] Add custom type legalization for bitcasting mmx to v2i32/v4i16/v8i8 to use movq2dq instead of going through memory.
|
2019-08-15 18:23:37 +00:00 |
|
mmx-fold-load.ll
|
…
|
|
|
mmx-fold-zero.ll
|
…
|
|
|
mmx-intrinsics.ll
|
…
|
|
|
mmx-only.ll
|
…
|
|
|
mod128.ll
|
…
|
|
|
movbe.ll
|
…
|
|
|
movddup-load-fold.ll
|
…
|
|
|
movdir-intrinsic-x86.ll
|
…
|
|
|
movdir-intrinsic-x86_64.ll
|
…
|
|
|
move_latch_to_loop_top.ll
|
Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
|
movfs.ll
|
…
|
|
|
movgs.ll
|
…
|
|
|
movmsk-cmp.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
movmsk.ll
|
…
|
|
|
movntdq-no-avx.ll
|
…
|
|
|
movpc32-check.ll
|
…
|
|
|
movtopush.ll
|
…
|
|
|
movtopush.mir
|
Describe stack-id as an enum
|
2019-06-17 09:13:29 +00:00 |
|
movtopush64.ll
|
…
|
|
|
ms-inline-asm-avx512.ll
|
[X86] Remove what little support we had for MPX
|
2019-08-29 18:09:02 +00:00 |
|
ms-inline-asm-redundant-clobber.ll
|
…
|
|
|
ms-inline-asm.ll
|
…
|
|
|
mul-constant-i8.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
mul-constant-i16.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
mul-constant-i32.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
mul-constant-i64.ll
|
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
|
mul-constant-result.ll
|
[Codegen] Merge tail blocks with no successors after block placement
|
2019-06-13 18:11:32 +00:00 |
|
mul-i256.ll
|
[SDAG] Fold umul_lohi with 0 or 1 multiplicand
|
2019-08-25 08:04:22 +00:00 |
|
mul-i512.ll
|
[SDAG] Fold umul_lohi with 0 or 1 multiplicand
|
2019-08-25 08:04:22 +00:00 |
|
mul-i1024.ll
|
[SDAG] Fold umul_lohi with 0 or 1 multiplicand
|
2019-08-25 08:04:22 +00:00 |
|
mul-legalize.ll
|
…
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|
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mul-remat.ll
|
…
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|
|
mul-shift-reassoc.ll
|
…
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|
|
mul64.ll
|
…
|
|
|
mul128.ll
|
[SDAG] Fold umul_lohi with 0 or 1 multiplicand
|
2019-08-25 08:04:22 +00:00 |
|
mul128_sext_loop.ll
|
…
|
|
|
mulfix_combine.ll
|
[DAGCombiner] Add simple folds for SMULFIX/UMULFIX/SMULFIXSAT
|
2019-08-16 13:16:48 +00:00 |
|
mulo-pow2.ll
|
[SDAG] Recursively legalize both vector mulo results
|
2019-05-10 20:42:48 +00:00 |
|
muloti.ll
|
…
|
|
|
mult-alt-generic-i686.ll
|
…
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|
|
mult-alt-generic-x86_64.ll
|
…
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|
|
mult-alt-x86.ll
|
…
|
|
|
multiple-loop-post-inc.ll
|
…
|
|
|
multiple-return-values-cross-block.ll
|
…
|
|
|
mulvi32.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
mulx32.ll
|
…
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|
|
mulx64.ll
|
…
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|
|
musttail-fastcall.ll
|
[X86] Disable use of zmm registers for varargs musttail calls under prefer-vector-width=256 and min-legal-vector-width=256.
|
2019-08-12 17:43:26 +00:00 |
|
musttail-indirect.ll
|
…
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|
|
musttail-thiscall.ll
|
…
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|
|
musttail-varargs.ll
|
[X86] Print register names in .seh_* directives
|
2019-08-30 21:23:05 +00:00 |
|
musttail.ll
|
…
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|
|
mwaitx.ll
|
…
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|
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named-reg-alloc.ll
|
…
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|
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named-reg-notareg.ll
|
…
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|
|
nancvt.ll
|
…
|
|
|
narrow-shl-cst.ll
|
[X86] Don't turn (and (shl X, C1), C2) into (shl (and X, (C1 >> C2), C2) if the original AND can represented by MOVZX.
|
2019-04-20 04:38:53 +00:00 |
|
narrow-shl-load.ll
|
…
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|
|
narrow_op-1.ll
|
…
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|
|
neg-of-3ops-lea.ll
|
[X86][Codegen] Add missed pattern that may be a lea+neg
|
2019-06-08 19:38:14 +00:00 |
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neg-shl-add.ll
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…
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|
|
neg_cmp.ll
|
…
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|
|
neg_fp.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to some X86/ and XCore/ tests."
|
2019-06-13 19:24:51 +00:00 |
|
negate-add-zero.ll
|
[IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format
|
2019-05-15 02:35:32 +00:00 |
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negate-i1.ll
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…
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|
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negate-shift.ll
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…
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negate.ll
|
…
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|
|
negative-offset.ll
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[NFC][X86] Autogenerate negative-offset.ll test
|
2019-05-22 15:34:43 +00:00 |
|
negative-sin.ll
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…
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|
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negative-stride-fptosi-user.ll
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…
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|
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negative-subscript.ll
|
…
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|
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negative_zero.ll
|
…
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|
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new-remat.ll
|
…
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|
|
newline-and-quote.ll
|
…
|
|
|
no-and8ri8.ll
|
…
|
|
|
no-cmov.ll
|
…
|
|
|
no-plt-libcalls.ll
|
Add, and infer, a nofree function attribute
|
2019-07-08 15:57:56 +00:00 |
|
no-plt.ll
|
…
|
|
|
no-prolog-kill.ll
|
…
|
|
|
no-sse2-avg.ll
|
…
|
|
|
no-stack-arg-probe.ll
|
…
|
|
|
nobt.ll
|
…
|
|
|
nocf_check.ll
|
…
|
|
|
nocx16.ll
|
…
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|
|
nomovtopush.ll
|
[X86] Fix stack probe issue on windows32.
|
2019-08-10 02:49:02 +00:00 |
|
non-lazy-bind.ll
|
…
|
|
|
non-unique-sections.ll
|
…
|
|
|
non-value-mem-operand.mir
|
[X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class.
|
2019-06-18 03:23:11 +00:00 |
|
nonconst-static-ev.ll
|
…
|
|
|
nonconst-static-iv.ll
|
…
|
|
|
nontemporal-2.ll
|
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
|
2019-07-11 14:45:03 +00:00 |
|
nontemporal-3.ll
|
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026)
|
2019-06-17 18:20:04 +00:00 |
|
nontemporal-loads-2.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
nontemporal-loads.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
nontemporal.ll
|
…
|
|
|
noreturn-call-linux.ll
|
[X86] Don't emit unreachable stack adjustments
|
2019-08-29 21:24:41 +00:00 |
|
noreturn-call.ll
|
[X86] Don't emit unreachable stack adjustments
|
2019-08-29 21:24:41 +00:00 |
|
norex-subreg.ll
|
…
|
|
|
nosse-error1.ll
|
…
|
|
|
nosse-error2.ll
|
…
|
|
|
nosse-varargs.ll
|
…
|
|
|
nosse-vector.ll
|
…
|
|
|
not-and-simplify.ll
|
…
|
|
|
note-cet-property.ll
|
…
|
|
|
note-sections.ll
|
…
|
|
|
null-streamer.ll
|
…
|
|
|
objc-gc-module-flags.ll
|
…
|
|
|
object-size.ll
|
…
|
|
|
oddshuffles.ll
|
[DAGCombiner][X86] Teach visitCONCAT_VECTORS to combine (concat_vectors (concat_vectors X, Y), undef)) -> (concat_vectors X, Y, undef, undef)
|
2019-08-20 22:12:50 +00:00 |
|
oddsubvector.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
|
[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 3)
|
2019-06-27 21:52:10 +00:00 |
|
opaque-constant-asm.ll
|
…
|
|
|
opt-ext-uses.ll
|
…
|
|
|
opt-shuff-tstore.ll
|
…
|
|
|
opt_phis.mir
|
…
|
|
|
opt_phis2.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
optimize-max-0.ll
|
…
|
|
|
optimize-max-1.ll
|
…
|
|
|
optimize-max-2.ll
|
…
|
|
|
optimize-max-3.ll
|
…
|
|
|
or-address.ll
|
…
|
|
|
or-branch.ll
|
[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
|
2019-06-25 17:29:18 +00:00 |
|
or-lea.ll
|
…
|
|
|
osx-private-labels.ll
|
…
|
|
|
overflow-intrinsic-setcc-fold.ll
|
…
|
|
|
overflow.ll
|
[SDAG] Fold umul_lohi with 0 or 1 multiplicand
|
2019-08-25 08:04:22 +00:00 |
|
overlap-shift.ll
|
…
|
|
|
packed_struct.ll
|
…
|
|
|
packss.ll
|
[X86] isTargetShuffleEquivalent - add BUILD_VECTOR matching
|
2019-08-18 17:15:26 +00:00 |
|
paddus.ll
|
[X86] Add DAG combine to fold any_extend_vector_inreg+truncstore to an extractelement+store
|
2019-07-31 22:43:08 +00:00 |
|
palignr.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
parity.ll
|
…
|
|
|
partial-fold32.ll
|
…
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|
|
partial-fold64.ll
|
…
|
|
|
partition.ll
|
Add IR support, ELF section and user documentation for partitioning feature.
|
2019-05-29 03:29:01 +00:00 |
|
pass-three.ll
|
…
|
|
|
patchable-prologue.ll
|
…
|
|
|
patchpoint-invoke.ll
|
…
|
|
|
patchpoint-verifiable.mir
|
…
|
|
|
patchpoint-webkit_jscc.ll
|
…
|
|
|
patchpoint.ll
|
…
|
|
|
pause.ll
|
…
|
|
|
peep-setb.ll
|
…
|
|
|
peep-test-0.ll
|
…
|
|
|
peep-test-1.ll
|
…
|
|
|
peep-test-2.ll
|
…
|
|
|
peep-test-3.ll
|
…
|
|
|
peep-test-4.ll
|
…
|
|
|
peephole-cvt-sse.ll
|
…
|
|
|
peephole-fold-movsd.ll
|
[X86] Regenerate load fold peephole test.
|
2019-07-04 12:33:37 +00:00 |
|
peephole-fold-testrr.mir
|
[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
|
2019-06-25 17:29:18 +00:00 |
|
peephole-multiple-folds.ll
|
…
|
|
|
peephole-na-phys-copy-folding.ll
|
…
|
|
|
peephole-recurrence.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
peephole.mir
|
Revert r359392 and r358887
|
2019-05-06 19:29:24 +00:00 |
|
personality.ll
|
…
|
|
|
personality_size.ll
|
…
|
|
|
phaddsub-extract.ll
|
[DAGCombine] matchBinOpReduction - add partial reduction matching
|
2019-07-24 17:29:56 +00:00 |
|
phaddsub-undef.ll
|
[X86][SSE] LowerBuildVectorv4x32 - don't insert MOVQ for undef elts
|
2019-05-13 16:10:11 +00:00 |
|
phaddsub.ll
|
[X86] isHorizontalBinOp - add extract_subvector(shuffle(x)) handling (PR39921)
|
2019-06-02 15:47:49 +00:00 |
|
phi-bit-propagation.ll
|
…
|
|
|
phi-immediate-factoring.ll
|
…
|
|
|
phielim-split.ll
|
…
|
|
|
phys-reg-local-regalloc.ll
|
…
|
|
|
phys_subreg_coalesce-2.ll
|
…
|
|
|
phys_subreg_coalesce-3.ll
|
…
|
|
|
phys_subreg_coalesce.ll
|
…
|
|
|
physreg-pairs-error.ll
|
…
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|
|
physreg-pairs.ll
|
…
|
|
|
pic-load-remat.ll
|
…
|
|
|
pic.ll
|
…
|
|
|
pic_jumptable.ll
|
…
|
|
|
pie.ll
|
…
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|
|
pku.ll
|
…
|
|
|
pmaddubsw.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
pmovext.ll
|
…
|
|
|
pmovsx-inreg.ll
|
[x86] split 256-bit store of concatenated vectors
|
2019-06-04 16:40:04 +00:00 |
|
pmul.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
pmulh.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
pmulld.ll
|
…
|
|
|
pointer-vector.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
pop-stack-cleanup-msvc.ll
|
…
|
|
|
pop-stack-cleanup.ll
|
…
|
|
|
popcnt.ll
|
[X86] Add custom isel to select ADD/SUB/OR/XOR/AND to their non-immediate forms under optsize when the immediate has additional users.
|
2019-07-04 22:53:57 +00:00 |
|
post-ra-sched-with-debug.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
post-ra-sched.ll
|
…
|
|
|
postalloc-coalescing.ll
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…
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postra-ignore-dbg-instrs.mir
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[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
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postra-licm.ll
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pow.75.ll
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pow.ll
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powi.ll
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pr1462.ll
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pr2326.ll
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pr2585.ll
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pr2656.ll
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[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
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2019-07-02 17:51:02 +00:00 |
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pr2659.ll
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pr10526.ll
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pr11202.ll
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pr11334.ll
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[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
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2019-07-06 17:59:57 +00:00 |
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pr11415.ll
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Reapply r359906, "RegAllocFast: Add heuristic to detect values not live-out of a block"
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2019-05-03 19:06:57 +00:00 |
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pr11468.ll
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pr14088.ll
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pr14098.ll
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pr14161.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
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pr14204.ll
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pr23664.ll
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pr24139.ll
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pr24374.ll
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Revert [Windows] Disable TrapUnreachable for Win64, add SEH_NoReturn
|
2019-09-03 22:27:27 +00:00 |
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pr24602.ll
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pr25828.ll
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pr26350.ll
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pr26835.ll
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pr26870.ll
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pr27071.ll
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pr27202.ll
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[X86] Add custom isel to select ADD/SUB/OR/XOR/AND to their non-immediate forms under optsize when the immediate has additional users.
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2019-07-04 22:53:57 +00:00 |
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pr27501.ll
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pr27591.ll
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pr27681.mir
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[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
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pr28129.ll
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pr28173.ll
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pr28444.ll
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Revert rL357745: [SelectionDAG] Compute known bits of CopyFromReg
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2019-04-10 18:00:41 +00:00 |
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pr28472.ll
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[X86] Automatically generate various tests. NFC
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2019-08-26 13:53:29 +00:00 |
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pr28489.ll
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pr28515.ll
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pr29022.ll
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pr29061.ll
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pr29112.ll
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[X86][SSE] matchBinaryPermuteShuffle - split INSERTPS combines
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2019-08-08 13:23:53 +00:00 |
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pr29170.ll
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pr29222.ll
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pr30284.ll
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[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
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2019-06-25 10:51:15 +00:00 |
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pr30290.ll
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pr30430.ll
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[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
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2019-07-02 17:51:02 +00:00 |
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pr30511.ll
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pr30562.ll
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pr30813.ll
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pr30821.mir
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[X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class.
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2019-06-18 03:23:11 +00:00 |
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pr31045.ll
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pr31956.ll
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pr32241.ll
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RegAllocFast: Improve hinting heuristic
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2019-05-16 12:50:39 +00:00 |
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pr32256.ll
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RegAllocFast: Improve hinting heuristic
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2019-05-16 12:50:39 +00:00 |
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pr32278.ll
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pr32282.ll
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[SelectionDAG] Use KnownBits::computeForAddSub/computeForAddCarry
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2019-04-15 07:19:11 +00:00 |
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pr32284.ll
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RegAllocFast: Improve hinting heuristic
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2019-05-16 12:50:39 +00:00 |
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pr32329.ll
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[X86] Remove dead nodes left after ReplaceAllUsesWith calls during address matching
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2019-04-24 18:02:07 +00:00 |
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pr32340.ll
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RegAllocFast: Improve hinting heuristic
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2019-05-16 12:50:39 +00:00 |
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pr32345.ll
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RegAllocFast: Improve hinting heuristic
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2019-05-16 12:50:39 +00:00 |
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pr32368.ll
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pr32451.ll
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pr32484.ll
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Reapply r359906, "RegAllocFast: Add heuristic to detect values not live-out of a block"
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2019-05-03 19:06:57 +00:00 |
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pr32515.ll
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pr32659.ll
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pr32907.ll
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pr33010.ll
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Fix pr33010, a 2 year old crashing regression
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2019-05-06 22:09:31 +00:00 |
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pr33290.ll
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pr34592.ll
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RegAllocFast: Improve hinting heuristic
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2019-05-16 12:50:39 +00:00 |
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pr34605.ll
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pr34634.ll
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pr34653.ll
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Reapply r359906, "RegAllocFast: Add heuristic to detect values not live-out of a block"
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2019-05-03 19:06:57 +00:00 |
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pr34657.ll
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pr35918.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
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pr35972.ll
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pr37820.ll
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pr37826.ll
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pr37879.ll
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[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
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2019-05-06 21:39:51 +00:00 |
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pr37916.ll
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pr38038.ll
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pr38185.ll
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Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
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pr38217.ll
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pr38533.ll
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pr38639.ll
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pr38738.ll
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pr38743.ll
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This reverts r365061 and r365062 (test update)
|
2019-07-05 12:42:06 +00:00 |
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pr38762.ll
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pr38763.ll
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pr38865-3.ll
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pr38865.ll
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pr38952.mir
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[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
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pr39098.ll
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…
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pr39187-g.ll
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pr39243.ll
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[DebugInfo] Combine Trivial and NonTrivial flags
|
2019-04-11 20:25:10 +00:00 |
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pr39666.ll
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[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches for expandload/compressstore.
|
2019-08-02 23:43:53 +00:00 |
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pr39733.ll
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…
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pr39896.ll
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Rename ExpandISelPseudo->FinalizeISel, delay register reservation
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2019-06-19 00:25:39 +00:00 |
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pr39926.ll
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pr40090.ll
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pr40289-64bit.ll
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pr40289.ll
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pr40529.ll
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pr40539.ll
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pr40631_deadstore_elision.ll
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pr40730.ll
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pr40737.ll
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pr40811.ll
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pr40891.ll
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pr40994.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
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pr41619.ll
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[X86] Add test case for mask register variant of PR41619 which should be fixed after r360552
|
2019-05-13 15:45:20 +00:00 |
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pr41678.ll
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RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
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pr41748.ll
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[SelectionDAG][X86] Support inline assembly returning an mmx register into a type with fewer than 64 bits.
|
2019-05-06 19:50:14 +00:00 |
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pr42452.ll
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[X86] Improve the type checking fast-isel handling of vector bitcasts.
|
2019-07-01 07:09:34 +00:00 |
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pr42565.ll
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[X86] Don't convert 8 or 16 bit ADDs to LEAs on Atom in FixupLEAPass.
|
2019-07-11 01:01:39 +00:00 |
|
pr42616.ll
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[X86] Remove offset of 8 from the call to FuseInst for UNPCKLPDrr folding added in r365287.
|
2019-07-14 04:13:33 +00:00 |
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pr42727.ll
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[SelectionDAG] makeEquivalentMemoryOrdering - early out for equal chains (PR42727)
|
2019-07-24 16:53:14 +00:00 |
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pr42870.ll
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[X86] Match the IR pattern form movmsk on SSE1 only targets where v4i32 isn't legal
|
2019-08-10 07:51:13 +00:00 |
|
pr42905.ll
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[X86] Don't allow combineSIntToFP to create v2i32 vectors after type legalization.
|
2019-08-06 21:43:15 +00:00 |
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pr42909.ll
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[X86] Remove -x86-experimental-vector-widening-legalization command line option and all its uses.
|
2019-08-08 06:48:22 +00:00 |
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pr42992.ll
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[X86] Manually reimplement getTargetInsertSubreg in X86DAGToDAGISel::matchBitExtract so we can call insertDAGNode on the target constant.
|
2019-08-16 04:47:44 +00:00 |
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pr42998.ll
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[X86] Teach -Os immediate sharing code to not count constant uses that will become INC/DEC.
|
2019-08-25 05:22:40 +00:00 |
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pr43157.ll
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[X86] Make inline assembly 'x' and 'v' constraints work for f128.
|
2019-08-29 05:13:56 +00:00 |
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pre-coalesce-2.ll
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…
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pre-coalesce.ll
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…
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pre-coalesce.mir
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[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
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pre-ra-sched.ll
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…
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prefer-avx256-lzcnt.ll
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…
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prefer-avx256-mask-extend.ll
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[X86] Move VPTESTM matching from the isel table to custom code in X86ISelDAGToDAG.
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2019-04-14 18:26:11 +00:00 |
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prefer-avx256-mask-shuffle.ll
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[X86][AVX] Add SimplifyDemandedVectorElts support for KSHIFTL/KSHIFTR
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2019-08-27 13:13:17 +00:00 |
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prefer-avx256-popcnt.ll
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prefer-avx256-shift.ll
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prefer-avx256-trunc.ll
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prefer-avx256-wide-mul.ll
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…
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prefetch.ll
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prefixdata.ll
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preserve_allcc64.ll
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preserve_mostcc64.ll
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private-2.ll
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…
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private.ll
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…
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probe-stack-x32.ll
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[X86] Fix stack probing on x32 (PR41477)
|
2019-04-20 07:25:46 +00:00 |
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prolog-push-seq.ll
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…
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prologepilog_deref_size.mir
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Describe stack-id as an enum
|
2019-06-17 09:13:29 +00:00 |
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prologue-epilogue-remarks.mir
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…
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prologuedata.ll
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…
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promote-assert-zext.ll
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…
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promote-i16.ll
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…
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promote-trunc.ll
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…
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promote-vec3.ll
|
[TargetLowering] Teach computeRegisterProperties to only widen v3i16/v3f16 vectors to the next power of 2 type if that's legal.
|
2019-08-18 06:28:06 +00:00 |
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promote.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
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2019-08-07 16:24:26 +00:00 |
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ps4-noreturn.ll
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…
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ps4-ssp-nop.ll
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…
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psadbw.ll
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[X86][SSE] Add test showing missing demanded elts PSADBW handling
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2019-08-12 14:01:16 +00:00 |
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pseudo_cmov_lower.ll
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…
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pseudo_cmov_lower1.ll
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…
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pseudo_cmov_lower2.ll
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…
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pshufb-mask-comments.ll
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…
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pshufd-combine-crash.ll
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…
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psubus.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
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2019-08-07 16:24:26 +00:00 |
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ptest.ll
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…
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ptr-rotate.ll
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…
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ptrtoint-constexpr.ll
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…
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ptrtoint-narrow.ll
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[AsmPrinter] Treat a narrowing PtrToInt like Trunc
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2019-05-23 16:29:09 +00:00 |
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ptwrite32-intrinsic.ll
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…
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ptwrite64-intrinsic.ll
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…
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pull-binop-through-shift.ll
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[DAGCombiner] visitShiftByConstant(): drop bogus signbit check
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2019-05-17 15:52:58 +00:00 |
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pull-conditional-binop-through-shift.ll
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[NFC] Fixup FileCheck option name in tests added in rL360881
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2019-05-16 12:39:34 +00:00 |
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push-cfi-debug.ll
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…
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push-cfi-obj.ll
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[llvm-readobj] Change -long-option to --long-option in tests. NFC
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2019-05-01 05:27:20 +00:00 |
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push-cfi.ll
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…
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ragreedy-bug.ll
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Codegen: Fixed perf branch_weights in couple of tests. NFC.
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2019-04-15 09:30:31 +00:00 |
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ragreedy-hoist-spill.ll
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Revert [MBP] Disable aggressive loop rotate in plain mode
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2019-08-29 19:03:58 +00:00 |
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ragreedy-last-chance-recoloring.ll
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…
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rd-mod-wr-eflags.ll
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…
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rdpid.ll
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…
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rdpmc.ll
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…
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rdrand-x86_64.ll
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…
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rdrand.ll
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…
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rdseed-x86_64.ll
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…
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rdseed.ll
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…
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rdtsc-upgrade.ll
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…
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rdtsc.ll
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…
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read-fp-no-frame-pointer.ll
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…
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recip-fastmath.ll
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[x86] fix fdiv test; NFC
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2019-08-16 13:31:23 +00:00 |
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recip-fastmath2.ll
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…
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recip-pic.ll
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…
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red-zone.ll
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…
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red-zone2.ll
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…
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reduce-trunc-shl.ll
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…
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regalloc-advanced-split-cost.ll
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…
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regalloc-copy-hints.mir
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Describe stack-id as an enum
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2019-06-17 09:13:29 +00:00 |
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regalloc-fast-missing-live-out-spill.mir
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RegAllocFast: Set MayLiveAcrossBlocks when allocating uses
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2019-05-27 20:37:31 +00:00 |
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regalloc-reconcile-broken-hints.ll
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…
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regalloc-spill-at-ehpad.ll
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…
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regcall-no-plt.ll
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…
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reghinting.ll
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…
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regparm.ll
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…
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regpressure.ll
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…
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relptr-rodata.ll
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IR: Teach Constant::needsRelocation() that relative pointers don't need to be relocated.
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2019-07-18 20:56:21 +00:00 |
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rem.ll
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[X86] Pre-commit test cases and test run line changes for D67087
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2019-09-04 17:33:38 +00:00 |
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rem_crash.ll
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…
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remarks-section.ll
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Reland: [Remarks] Add support for serializing metadata for every remark streamer
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2019-07-26 01:33:30 +00:00 |
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remat-constant.ll
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…
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remat-fold-load.ll
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…
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remat-mov-0.ll
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…
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remat-phys-dead.ll
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…
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remat-scalar-zero.ll
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…
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replace-load-and-with-bzhi.ll
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…
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replace_unsupported_masked_mem_intrin.ll
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…
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ret-addr.ll
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…
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ret-i64-0.ll
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…
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ret-mmx.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
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2019-08-07 16:24:26 +00:00 |
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retpoline-external.ll
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…
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retpoline-regparm.ll
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…
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retpoline.ll
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…
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return-ext.ll
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…
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return_zeroext_i2.ll
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…
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returned-trunc-tail-calls.ll
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…
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reverse_branches.ll
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Revert [MBP] Disable aggressive loop rotate in plain mode
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2019-08-29 19:03:58 +00:00 |
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rip-rel-address.ll
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…
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rip-rel-lea.ll
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…
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rodata-relocs.ll
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…
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rot16.ll
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…
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rot32.ll
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…
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rot64.ll
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…
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rotate-extract-vector.ll
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[DAGCombiner] Match (add X, X) as (shl X, 1) when detecting rotate.
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2019-08-31 11:40:02 +00:00 |
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rotate-extract.ll
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[DAGCombiner] Match (add X, X) as (shl X, 1) when detecting rotate.
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2019-08-31 11:40:02 +00:00 |
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rotate-multi.ll
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…
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rotate.ll
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…
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rotate2.ll
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…
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rotate4.ll
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[x86] make 8-bit shl undesirable
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2019-04-08 13:58:50 +00:00 |
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rotate_vec.ll
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…
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rounding-ops.ll
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…
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rrlist-livereg-corrutpion.ll
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…
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rtm.ll
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…
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sad.ll
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[X86] Improve lowering of v2i32 SAD handling in combineLoopSADPattern.
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2019-08-23 05:33:27 +00:00 |
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sad_variations.ll
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…
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sadd_sat.ll
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…
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sadd_sat_vec.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
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2019-08-07 16:24:26 +00:00 |
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saddo-redundant-add.ll
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[X86] Automatically generate various tests. NFC
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2019-08-26 13:53:29 +00:00 |
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safestack.ll
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…
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safestack_inline.ll
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…
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safestack_ssp.ll
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…
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sandybridge-loads.ll
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[x86] avoid vector load narrowing with extracted store uses (PR42305)
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2019-06-19 18:13:47 +00:00 |
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sar_fold.ll
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…
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sar_fold64.ll
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…
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sat-add.ll
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[TargetLowering] SimplifyMultipleUseDemandedBits - add VECTOR_SHUFFLE support.
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2019-07-23 15:35:55 +00:00 |
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sbb.ll
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…
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scalar-extract.ll
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…
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scalar-fp-to-i32.ll
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[X86] Don't use Expand for i32 fp_to_uint on SSE1/2 targets on 32-bit target.
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2019-09-03 05:57:18 +00:00 |
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scalar-fp-to-i64.ll
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[X86] Convert f32/f64 FANDN/FAND/FOR/FXOR to vector logic ops and scalar_to_vector/extract_vector_elts to reduce isel patterns.
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2019-06-10 00:41:07 +00:00 |
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scalar-int-to-fp.ll
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[X86] Custom promote i32->f80 uint_to_fp on AVX512 64-bit targets.
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2019-09-03 02:51:10 +00:00 |
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scalar-min-max-fill-operand.ll
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…
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scalar_sse_minmax.ll
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…
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scalar_widen_div.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
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2019-08-07 16:24:26 +00:00 |
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scalarize-bitcast.ll
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…
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scalarize-fp.ll
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[DAGCombiner] generalize binop-of-splats scalarization
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2019-04-23 13:16:41 +00:00 |
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scatter-schedule.ll
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…
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scavenger.mir
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…
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scev-interchange.ll
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…
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scheduler-backtracking.ll
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[DAGCombiner] Combine OR as ADD when no common bits are set
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2019-04-23 10:01:08 +00:00 |
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sdiv-exact.ll
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[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
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2019-07-08 06:52:49 +00:00 |
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sdiv-pow2.ll
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…
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section_mergeable_size.ll
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…
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segmented-stacks-dynamic.ll
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…
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segmented-stacks-standalone.ll
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…
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segmented-stacks.ll
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[X86] for split stack, not save/restore nested arg if unused
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2019-07-19 12:54:44 +00:00 |
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seh-catch-all-win32.ll
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…
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seh-catch-all.ll
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…
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seh-catchpad.ll
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[X86] Print register names in .seh_* directives
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2019-08-30 21:23:05 +00:00 |
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seh-except-finally.ll
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…
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seh-exception-code.ll
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…
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seh-filter-no-personality.ll
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…
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seh-finally.ll
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…
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seh-localaddress.ll
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…
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seh-no-invokes.ll
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…
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seh-safe-div-win32.ll
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…
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seh-safe-div.ll
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…
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seh-stack-realign.ll
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…
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select-1-or-neg1.ll
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…
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select-mmx.ll
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…
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select-of-fp-constants.ll
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[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
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2019-07-02 17:51:02 +00:00 |
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select-with-and-or.ll
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…
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select.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
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2019-08-07 16:24:26 +00:00 |
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select_const.ll
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[x86] make 8-bit shl undesirable
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2019-04-08 13:58:50 +00:00 |
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select_meta.ll
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…
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selectcc-to-shiftand.ll
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…
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selectiondag-crash.ll
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…
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selectiondag-cse.ll
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…
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selectiondag-debug-loc.ll
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…
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selectiondag-dominator.ll
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…
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selectiondag-order.ll
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…
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setcc-combine.ll
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…
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setcc-logic.ll
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…
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setcc-lowering.ll
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[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
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2019-06-25 10:51:15 +00:00 |
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setcc-narrowing.ll
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…
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setcc-wide-types.ll
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[X86] Don't compare i128 through vector if construction not cheap (PR41971)
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2019-05-22 06:47:06 +00:00 |
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setcc.ll
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…
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setjmp-spills.ll
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…
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setoeq.ll
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…
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setuge.ll
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…
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sext-i1.ll
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…
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sext-load.ll
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…
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sext-ret-val.ll
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…
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sext-setcc-self.ll
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…
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sext-subreg.ll
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…
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sext-trunc.ll
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…
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sha.ll
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…
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shadow-stack.ll
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…
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shift-amount-mod.ll
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[DAGCombine][X86][AArch64][MIPS][LANAI] (C - x) - y -> C - (x + y) fold (PR41952)
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2019-06-04 11:06:21 +00:00 |
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shift-and-x86_64.ll
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…
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shift-and.ll
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…
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shift-avx2-crash.ll
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[X86] Automatically generate shift tests. NFC
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2019-08-20 23:47:19 +00:00 |
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shift-bmi2.ll
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…
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shift-coalesce.ll
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[X86] Automatically generate shift tests. NFC
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2019-08-20 23:47:19 +00:00 |
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shift-codegen.ll
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…
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shift-combine-crash.ll
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[X86] Automatically generate shift tests. NFC
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2019-08-20 23:47:19 +00:00 |
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shift-combine.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
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2019-08-07 16:24:26 +00:00 |
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shift-double-x86_64.ll
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…
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shift-double.ll
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…
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shift-folding.ll
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…
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shift-i128.ll
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[X86] Automatically generate shift tests. NFC
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2019-08-20 23:47:19 +00:00 |
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shift-i256.ll
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…
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shift-logic.ll
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[DAGCombiner] improve throughput of shift+logic+shift
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2019-09-01 18:38:15 +00:00 |
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shift-mask.ll
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[X86] Disable shouldFoldConstantShiftPairToMask for scalar shifts on AMD targets (PR40758)
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2019-05-14 15:21:28 +00:00 |
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shift-one.ll
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[X86] Automatically generate shift tests. NFC
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2019-08-20 23:47:19 +00:00 |
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shift-pair.ll
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…
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shift-parts.ll
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[X86] Automatically generate shift tests. NFC
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2019-08-20 23:47:19 +00:00 |
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shift-pcmp.ll
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…
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shift_minsize.ll
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[SelectionDAG] Don't generate libcalls for wide shifts on Windows (PR42711)
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2019-08-28 13:55:10 +00:00 |
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shl-anyext.ll
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…
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shl-crash-on-legalize.ll
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…
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shl-i64.ll
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…
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shl_elim.ll
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[X86] Automatically generate various tests. NFC
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2019-08-26 13:53:29 +00:00 |
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shl_undef.ll
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…
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shrink-compare.ll
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…
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shrink-fp-const1.ll
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…
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shrink-fp-const2.ll
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…
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shrink-wrap-chkstk-x86_64.ll
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[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
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2019-06-13 13:56:19 +00:00 |
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shrink-wrap-chkstk.ll
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…
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shrink-wrapping-vla.ll
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…
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shrink_vmul.ll
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Revert [X86] SimplifyDemandedVectorElts - attempt to recombine target shuffle using DemandedElts mask (reapplied)
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2019-08-16 23:08:56 +00:00 |
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shrink_vmul_sse.ll
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…
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shrink_wrap_dbg_value.mir
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Describe stack-id as an enum
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2019-06-17 09:13:29 +00:00 |
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shrinkwrap-hang.ll
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…
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shuffle-combine-crash-2.ll
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…
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shuffle-combine-crash.ll
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[X86] Automatically generate various tests. NFC
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2019-08-26 13:53:29 +00:00 |
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shuffle-extract-subvector.ll
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…
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shuffle-of-insert.ll
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…
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shuffle-of-splat-multiuses.ll
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…
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shuffle-strided-with-offset-128.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
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2019-08-07 16:24:26 +00:00 |
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shuffle-strided-with-offset-256.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
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2019-08-07 16:24:26 +00:00 |
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shuffle-strided-with-offset-512.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
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2019-08-07 16:24:26 +00:00 |
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shuffle-vs-trunc-128.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
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shuffle-vs-trunc-256.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
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2019-08-07 16:24:26 +00:00 |
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shuffle-vs-trunc-512.ll
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[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
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2019-08-30 17:35:08 +00:00 |
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sibcall-2.ll
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…
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sibcall-3.ll
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…
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sibcall-4.ll
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…
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sibcall-5.ll
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…
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sibcall-6.ll
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…
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sibcall-byval.ll
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…
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sibcall-win64.ll
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…
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sibcall.ll
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[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
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2019-06-25 17:29:18 +00:00 |
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signbit-shift.ll
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[DAGCombiner] Combine OR as ADD when no common bits are set
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2019-04-23 10:01:08 +00:00 |
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signed-truncation-check.ll
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…
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simple-register-allocation-read-undef.mir
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[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
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2019-04-05 19:28:09 +00:00 |
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simple-zext.ll
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…
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sincos-opt.ll
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[TargetLowering][PS4] Add sincos(f) lib functions when target is PS4
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2019-09-02 16:53:32 +00:00 |
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sincos.ll
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…
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sink-addsub-of-const.ll
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[DAGCombine][X86][AArch64][MIPS][LANAI] (C - x) - y -> C - (x + y) fold (PR41952)
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2019-06-04 11:06:21 +00:00 |
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sink-blockfreq.ll
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…
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sink-cheap-instructions.ll
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…
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sink-gep-before-mem-inst.ll
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…
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sink-hoist.ll
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…
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sink-local-value.ll
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…
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sink-out-of-loop.ll
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…
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sitofp.ll
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…
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sjlj-baseptr.ll
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…
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sjlj-eh.ll
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…
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sjlj-shadow-stack-liveness.mir
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Rename ExpandISelPseudo->FinalizeISel, delay register reservation
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2019-06-19 00:25:39 +00:00 |
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sjlj.ll
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…
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slow-incdec.ll
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…
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slow-pmulld.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
slow-unaligned-mem.ll
|
…
|
|
|
small-byval-memcpy.ll
|
…
|
|
|
smul-with-overflow.ll
|
…
|
|
|
smul_fix.ll
|
[CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIX
|
2019-09-03 19:35:07 +00:00 |
|
smul_fix_sat.ll
|
[CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIX
|
2019-09-03 19:35:07 +00:00 |
|
smul_fix_sat_constants.ll
|
[X86] Remove redundant ';' chars ending IR lines in lit tests. NFC
|
2019-08-11 19:27:14 +00:00 |
|
soft-fp-legal-in-HW-reg.ll
|
…
|
|
|
soft-fp.ll
|
…
|
|
|
soft-sitofp.ll
|
…
|
|
|
speculative-load-hardening-call-and-ret.ll
|
…
|
|
|
speculative-load-hardening-gather.ll
|
…
|
|
|
speculative-load-hardening-indirect.ll
|
…
|
|
|
speculative-load-hardening.ll
|
Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
|
splat-const.ll
|
…
|
|
|
splat-for-size.ll
|
…
|
|
|
split-eh-lpad-edges.ll
|
…
|
|
|
split-extend-vector-inreg.ll
|
…
|
|
|
split-store.ll
|
[DAGCombiner] Combine OR as ADD when no common bits are set
|
2019-04-23 10:01:08 +00:00 |
|
split-vector-bitcast.ll
|
…
|
|
|
split-vector-rem.ll
|
…
|
|
|
sqrt-fastmath-mir.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
sqrt-fastmath-tune.ll
|
…
|
|
|
sqrt-fastmath.ll
|
…
|
|
|
sqrt-partial.ll
|
…
|
|
|
sqrt.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
srem-seteq-optsize.ll
|
[CodeGen][SelectionDAG] More efficient code for X % C == 0 (SREM case)
|
2019-08-13 14:57:37 +00:00 |
|
srem-seteq-vec-nonsplat.ll
|
[TargetLowering] x s% C == 0 fold: vector divisor with INT_MIN handling
|
2019-08-19 15:01:42 +00:00 |
|
srem-seteq-vec-splat.ll
|
[CodeGen][SelectionDAG] More efficient code for X % C == 0 (SREM case)
|
2019-08-13 14:57:37 +00:00 |
|
srem-seteq.ll
|
[X86] Pre-commit test cases and test run line changes for D67087
|
2019-09-04 17:33:38 +00:00 |
|
sret-implicit.ll
|
…
|
|
|
sse-align-0.ll
|
…
|
|
|
sse-align-1.ll
|
…
|
|
|
sse-align-2.ll
|
…
|
|
|
sse-align-3.ll
|
…
|
|
|
sse-align-4.ll
|
…
|
|
|
sse-align-5.ll
|
…
|
|
|
sse-align-6.ll
|
…
|
|
|
sse-align-7.ll
|
…
|
|
|
sse-align-8.ll
|
…
|
|
|
sse-align-9.ll
|
…
|
|
|
sse-align-10.ll
|
…
|
|
|
sse-align-11.ll
|
…
|
|
|
sse-align-12.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
sse-commute.ll
|
…
|
|
|
sse-cvttp2si.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
sse-domains.ll
|
…
|
|
|
sse-fcopysign.ll
|
[X86] Add patterns to select (scalar_to_vector (loadf32)) as (V)MOVSSrm instead of COPY_TO_REGCLASS + (V)MOVSSrm_alt.
|
2019-07-02 17:51:02 +00:00 |
|
sse-fsignum.ll
|
…
|
|
|
sse-intel-ocl.ll
|
…
|
|
|
sse-intrinsics-fast-isel-x86_64.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
sse-intrinsics-fast-isel.ll
|
[X86] Separate the memory size of vzext_load/vextract_store from the element size of the result type. Use them improve the codegen of v2f32 loads/stores with sse1 only.
|
2019-07-15 02:02:31 +00:00 |
|
sse-intrinsics-x86-upgrade.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
sse-intrinsics-x86.ll
|
…
|
|
|
sse-intrinsics-x86_64-upgrade.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
sse-intrinsics-x86_64.ll
|
…
|
|
|
sse-load-ret.ll
|
…
|
|
|
sse-minmax.ll
|
…
|
|
|
sse-only.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
sse-regcall.ll
|
…
|
|
|
sse-scalar-fp-arith-unary.ll
|
…
|
|
|
sse-scalar-fp-arith.ll
|
[X86] Add load folding isel patterns to scalar_math_patterns and AVX512_scalar_math_fp_patterns.
|
2019-06-11 04:30:53 +00:00 |
|
sse-unaligned-mem-feature.ll
|
…
|
|
|
sse-varargs.ll
|
…
|
|
|
sse1-fcopysign.ll
|
…
|
|
|
sse1.ll
|
…
|
|
|
sse2-intrinsics-canonical.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
sse2-intrinsics-fast-isel-x86_64.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
sse2-intrinsics-fast-isel.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
sse2-intrinsics-x86-upgrade.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
sse2-intrinsics-x86.ll
|
[X86] Restore the pavg intrinsics.
|
2019-04-15 17:17:35 +00:00 |
|
sse2-intrinsics-x86_64-upgrade.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
sse2-intrinsics-x86_64.ll
|
…
|
|
|
sse2-vector-shifts.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
sse2.ll
|
[X86] Make movsd commutable to shufpd with a 0x02 immediate on pre-SSE4.1 targets.
|
2019-07-08 06:52:43 +00:00 |
|
sse3-avx-addsub-2.ll
|
…
|
|
|
sse3-avx-addsub.ll
|
…
|
|
|
sse3-intrinsics-fast-isel.ll
|
…
|
|
|
sse3-intrinsics-x86.ll
|
…
|
|
|
sse3.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
sse4a-intrinsics-fast-isel.ll
|
…
|
|
|
sse4a-upgrade.ll
|
…
|
|
|
sse4a.ll
|
…
|
|
|
sse41-intrinsics-fast-isel.ll
|
…
|
|
|
sse41-intrinsics-x86-upgrade.ll
|
…
|
|
|
sse41-intrinsics-x86.ll
|
…
|
|
|
sse41-pmovxrm.ll
|
…
|
|
|
sse41.ll
|
[X86] Add a DAG combine to combine INSERTPS and VBROADCAST of a scalar load. Remove corresponding isel patterns.
|
2019-08-29 05:48:48 +00:00 |
|
sse42-intrinsics-fast-isel-x86_64.ll
|
…
|
|
|
sse42-intrinsics-fast-isel.ll
|
…
|
|
|
sse42-intrinsics-x86.ll
|
…
|
|
|
sse42-intrinsics-x86_64.ll
|
…
|
|
|
sse_partial_update.ll
|
…
|
|
|
sse_reload_fold.ll
|
…
|
|
|
ssp-data-layout.ll
|
…
|
|
|
ssp-guard-spill.ll
|
…
|
|
|
ssse3-intrinsics-fast-isel.ll
|
…
|
|
|
ssse3-intrinsics-x86.ll
|
…
|
|
|
ssub_sat.ll
|
[X86] Remove redundant ';' chars ending IR lines in lit tests. NFC
|
2019-08-11 19:27:14 +00:00 |
|
ssub_sat_vec.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
stack-align-memcpy.ll
|
[NFC] Update memcpy tests
|
2019-05-06 09:46:50 +00:00 |
|
stack-align.ll
|
…
|
|
|
stack-align2.ll
|
…
|
|
|
stack-folding-3dnow.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-adx-x86_64.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-adx.mir
|
[X86] Merge the different SETcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:27:49 +00:00 |
|
stack-folding-avx512bf16.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-avx512vp2intersect.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-bmi.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-bmi2.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-bmi2.mir
|
…
|
|
|
stack-folding-fp-avx1.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-fp-avx512.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-fp-avx512vl.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-fp-sse42.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-int-avx1.ll
|
[X86][CodeGen][NFC] Delay `combineIncDecVector()` from DAGCombine to X86DAGToDAGISel
|
2019-08-29 10:50:09 +00:00 |
|
stack-folding-int-avx2.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-int-avx512.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-int-avx512vl.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-int-avx512vnni.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-int-sse42.ll
|
[X86][CodeGen][NFC] Delay `combineIncDecVector()` from DAGCombine to X86DAGToDAGISel
|
2019-08-29 10:50:09 +00:00 |
|
stack-folding-lwp.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-mmx.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-sha.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-tbm.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-x86_64.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-folding-xop.ll
|
[X86] Automatically generate stack folding tests. NFC
|
2019-08-25 20:48:14 +00:00 |
|
stack-probe-red-zone.ll
|
…
|
|
|
stack-probe-size.ll
|
…
|
|
|
stack-probes.ll
|
…
|
|
|
stack-protector-dbginfo.ll
|
…
|
|
|
stack-protector-msvc.ll
|
…
|
|
|
stack-protector-remarks.ll
|
…
|
|
|
stack-protector-target.ll
|
…
|
|
|
stack-protector-vreg-to-vreg-copy.ll
|
…
|
|
|
stack-protector-weight.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
stack-protector.ll
|
StackProtector: Use PointerMayBeCaptured
|
2019-06-12 14:23:33 +00:00 |
|
stack-size-section-function-sections.ll
|
…
|
|
|
stack-size-section.ll
|
…
|
|
|
stack-update-frame-opcode.ll
|
…
|
|
|
stack_guard_remat.ll
|
…
|
|
|
stackguard-internal.ll
|
…
|
|
|
stackmap-fast-isel.ll
|
…
|
|
|
stackmap-frame-setup.ll
|
…
|
|
|
stackmap-large-constants.ll
|
…
|
|
|
stackmap-large-location-size.ll
|
…
|
|
|
stackmap-liveness.ll
|
…
|
|
|
stackmap-nops.ll
|
…
|
|
|
stackmap-shadow-optimization.ll
|
…
|
|
|
stackmap.ll
|
…
|
|
|
stackpointer.ll
|
…
|
|
|
statepoint-allocas.ll
|
…
|
|
|
statepoint-call-lowering.ll
|
…
|
|
|
statepoint-far-call.ll
|
…
|
|
|
statepoint-forward.ll
|
…
|
|
|
statepoint-gctransition-call-lowering.ll
|
…
|
|
|
statepoint-invoke.ll
|
…
|
|
|
statepoint-live-in.ll
|
…
|
|
|
statepoint-no-realign-stack.ll
|
[Statepoints] Fix overalignment of loads in no-realign-stack functions
|
2019-08-02 20:17:37 +00:00 |
|
statepoint-stack-usage.ll
|
…
|
|
|
statepoint-stackmap-format.ll
|
…
|
|
|
statepoint-uniqueing.ll
|
…
|
|
|
statepoint-vector-bad-spill.ll
|
…
|
|
|
statepoint-vector.ll
|
…
|
|
|
stdarg.ll
|
…
|
|
|
stdcall-notailcall.ll
|
…
|
|
|
stdcall.ll
|
…
|
|
|
store-empty-member.ll
|
…
|
|
|
store-fp-constant.ll
|
…
|
|
|
store-global-address.ll
|
…
|
|
|
store-narrow.ll
|
[X86] Automatically generate various tests. NFC
|
2019-08-26 13:53:29 +00:00 |
|
store-zero-and-minus-one.ll
|
…
|
|
|
store_op_load_fold.ll
|
…
|
|
|
store_op_load_fold2.ll
|
…
|
|
|
stores-merging.ll
|
…
|
|
|
storetrunc-fp.ll
|
…
|
|
|
stride-nine-with-base-reg.ll
|
…
|
|
|
stride-reuse.ll
|
…
|
|
|
sttni.ll
|
…
|
|
|
sub-of-not.ll
|
[Codegen][X86][AArch64][ARM][PowerPC] Inc-of-add vs sub-of-not (PR42457)
|
2019-07-03 09:41:35 +00:00 |
|
sub-with-overflow.ll
|
[DAGCombiner][X86][SystemZ] Canonicalize SSUBO with immediate RHS to SADDO by negating the immediate.
|
2019-04-09 18:33:56 +00:00 |
|
sub.ll
|
…
|
|
|
subcarry.ll
|
[DAGCombiner] fold (addcarry (xor a, -1), b, c) -> (subcarry b, a, !c) and flip carry.
|
2019-07-16 15:17:00 +00:00 |
|
subreg-to-reg-0.ll
|
…
|
|
|
subreg-to-reg-1.ll
|
…
|
|
|
subreg-to-reg-2.ll
|
…
|
|
|
subreg-to-reg-3.ll
|
…
|
|
|
subreg-to-reg-4.ll
|
…
|
|
|
subreg-to-reg-6.ll
|
…
|
|
|
subvector-broadcast.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
sunkaddr-ext.ll
|
…
|
|
|
swap.ll
|
…
|
|
|
swift-error.ll
|
…
|
|
|
swift-return.ll
|
RegAllocFast: Improve hinting heuristic
|
2019-05-16 12:50:39 +00:00 |
|
swiftcc.ll
|
[X86] Enable tail calls for CallingConv::Swift
|
2019-04-05 20:18:25 +00:00 |
|
swifterror.ll
|
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
|
2019-06-14 23:08:59 +00:00 |
|
swiftself.ll
|
[FastISel] Skip creating unnecessary vregs for arguments
|
2019-06-10 16:53:37 +00:00 |
|
switch-bt.ll
|
…
|
|
|
switch-crit-edge-constant.ll
|
…
|
|
|
switch-default-only.ll
|
…
|
|
|
switch-density.ll
|
…
|
|
|
switch-edge-weight.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
switch-jump-table.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
switch-lower-peel-top-case.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
switch-or.ll
|
…
|
|
|
switch-order-weight.ll
|
…
|
|
|
switch-zextload.ll
|
…
|
|
|
switch.ll
|
[test] Change comment wording (NFC)
|
2019-06-18 23:31:10 +00:00 |
|
swizzle-2.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
swizzle-avx2.ll
|
…
|
|
|
system-intrinsics-64-xsave.ll
|
…
|
|
|
system-intrinsics-64-xsavec.ll
|
…
|
|
|
system-intrinsics-64-xsaveopt.ll
|
…
|
|
|
system-intrinsics-64-xsaves.ll
|
…
|
|
|
system-intrinsics-64.ll
|
…
|
|
|
system-intrinsics-xgetbv.ll
|
…
|
|
|
system-intrinsics-xsave.ll
|
…
|
|
|
system-intrinsics-xsavec.ll
|
…
|
|
|
system-intrinsics-xsaveopt.ll
|
…
|
|
|
system-intrinsics-xsaves.ll
|
…
|
|
|
system-intrinsics-xsetbv.ll
|
…
|
|
|
system-intrinsics.ll
|
…
|
|
|
tail-call-attrs.ll
|
…
|
|
|
tail-call-casts.ll
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…
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tail-call-conditional.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
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tail-call-got.ll
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…
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tail-call-legality.ll
|
…
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tail-call-mutable-memarg.ll
|
…
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tail-call-parameter-attrs-mismatch.ll
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…
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tail-call-win64.ll
|
…
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|
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tail-dup-addr.ll
|
…
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|
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tail-dup-catchret.ll
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…
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tail-dup-debugloc.ll
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
tail-dup-merge-loop-headers.ll
|
Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
|
tail-dup-no-other-successor.ll
|
…
|
|
|
tail-dup-repeat.ll
|
Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
|
tail-merge-after-mbp.mir
|
[Codegen] Merge tail blocks with no successors after block placement
|
2019-06-13 18:11:32 +00:00 |
|
tail-merge-debugloc.ll
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
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tail-merge-identical.ll
|
…
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tail-merge-unreachable.ll
|
…
|
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tail-merge-wineh.ll
|
…
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|
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tail-opts.ll
|
[Codegen] Merge tail blocks with no successors after block placement
|
2019-06-13 18:11:32 +00:00 |
|
tail-threshold.ll
|
[Codegen] Merge tail blocks with no successors after block placement
|
2019-06-13 18:11:32 +00:00 |
|
tailcall-64.ll
|
…
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|
|
tailcall-assume.ll
|
[CodeGen/Analysis] Intrinsic llvm.assume should not block tail call optimization
|
2019-08-16 16:26:12 +00:00 |
|
tailcall-calleesave.ll
|
…
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|
|
tailcall-cgp-dup.ll
|
[CGP] Look through bitcasts when duplicating returns for tail calls
|
2019-04-23 21:57:46 +00:00 |
|
tailcall-disable.ll
|
…
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tailcall-fastisel.ll
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…
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tailcall-largecode.ll
|
…
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tailcall-lifetime-end.ll
|
…
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tailcall-mem-intrinsics.ll
|
…
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|
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tailcall-msvc-conventions.ll
|
…
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|
|
tailcall-multiret.ll
|
…
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|
|
tailcall-pseudo-64.mir
|
[X86] Preserve operand flag when expanding TCRETURNri
|
2019-04-05 20:18:21 +00:00 |
|
tailcall-pseudo.mir
|
[X86] Preserve operand flag when expanding TCRETURNri
|
2019-04-05 20:18:21 +00:00 |
|
tailcall-readnone.ll
|
…
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|
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tailcall-returndup-void.ll
|
…
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|
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tailcall-ri64.ll
|
…
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|
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tailcall-stackalign.ll
|
…
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|
|
tailcall-structret.ll
|
…
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tailcall.ll
|
…
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tailcallbyval.ll
|
…
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|
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tailcallbyval64.ll
|
…
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|
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tailcallfp.ll
|
…
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|
|
tailcallfp2.ll
|
…
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|
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tailcallpic1.ll
|
…
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|
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tailcallpic2.ll
|
…
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tailcallpic3.ll
|
…
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|
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tailcallstack64.ll
|
…
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|
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taildup-crash.ll
|
…
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|
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tailjmp_gotpcrel_relax_relocation.ll
|
…
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|
|
targetLoweringGeneric.ll
|
…
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|
|
tbm-intrinsics-fast-isel-x86_64.ll
|
[X86] Teach convertToThreeAddress to handle SUB with immediate
|
2019-07-15 23:07:56 +00:00 |
|
tbm-intrinsics-fast-isel.ll
|
[X86] Teach convertToThreeAddress to handle SUB with immediate
|
2019-07-15 23:07:56 +00:00 |
|
tbm-intrinsics-x86_64.ll
|
…
|
|
|
tbm-intrinsics.ll
|
…
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|
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tbm_patterns.ll
|
[X86] Add patterns with and_flag_nocf for BLSI and TBM instructions.
|
2019-07-10 22:44:32 +00:00 |
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test-nofold.ll
|
…
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|
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test-shrink-bug.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
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test-shrink.ll
|
…
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|
|
test-vs-bittest.ll
|
[DAGCombiner] try to form test+set out of shift+mask patterns
|
2019-09-02 14:52:09 +00:00 |
|
test_x86condbr_globaladdr.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
testb-je-fusion.ll
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…
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testl-commute.ll
|
…
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this-return-64.ll
|
…
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throws-cfi-fp.ll
|
…
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throws-cfi-no-fp.ll
|
…
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|
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tls-addr-non-leaf-function.ll
|
…
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tls-android-negative.ll
|
…
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tls-android.ll
|
…
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|
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tls-local-dynamic.ll
|
…
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tls-models.ll
|
…
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|
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tls-no-plt.ll
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[X86] -fno-plt: use GOT __tls_get_addr only if GOTPCRELX is enabled
|
2019-07-11 10:10:09 +00:00 |
|
tls-pic.ll
|
…
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tls-pie.ll
|
…
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|
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tls-shrink-wrapping.ll
|
…
|
|
|
tls-windows-itanium.ll
|
[llvm-readobj] Change -long-option to --long-option in tests. NFC
|
2019-05-01 05:27:20 +00:00 |
|
tls.ll
|
…
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|
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tlv-1.ll
|
…
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|
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tlv-2.ll
|
…
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|
|
tlv-3.ll
|
…
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|
|
token_landingpad.ll
|
…
|
|
|
trap.ll
|
Revert [Windows] Disable TrapUnreachable for Win64, add SEH_NoReturn
|
2019-09-03 22:27:27 +00:00 |
|
tree_way_unsigned_cmp.ll
|
[NFC] Added test from PR19758
|
2019-06-09 15:12:46 +00:00 |
|
trunc-and.ll
|
[DAGCombiner][x86] prevent infinite loop from truncate/extend transforms
|
2019-08-05 11:27:07 +00:00 |
|
trunc-ext-ld-st.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
trunc-store.ll
|
…
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|
|
trunc-subvector.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
trunc-to-bool.ll
|
…
|
|
|
twoaddr-coalesce-2.ll
|
…
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|
|
twoaddr-coalesce-3.ll
|
[X86] Pre-commit test cases and test run line changes for D67087
|
2019-09-04 17:33:38 +00:00 |
|
twoaddr-coalesce.ll
|
…
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|
|
twoaddr-dbg-value.mir
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…
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|
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twoaddr-lea.ll
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[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
|
2019-05-25 06:17:47 +00:00 |
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twoaddr-pass-sink.ll
|
…
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twoaddr-sink-terminator.ll
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…
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|
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typeid-alias.ll
|
CodeGen: Don't follow aliases when extracting type info.
|
2019-08-02 17:43:45 +00:00 |
|
uadd_sat.ll
|
[X86] Remove redundant ';' chars ending IR lines in lit tests. NFC
|
2019-08-11 19:27:14 +00:00 |
|
uadd_sat_vec.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
uint64-to-float.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
uint_to_fp-2.ll
|
…
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|
|
uint_to_fp-3.ll
|
…
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|
|
uint_to_fp.ll
|
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
|
2019-05-06 21:39:51 +00:00 |
|
umul-with-carry.ll
|
…
|
|
|
umul-with-overflow.ll
|
…
|
|
|
umul_fix.ll
|
[CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIX
|
2019-09-03 19:35:07 +00:00 |
|
umulo-64-legalisation-lowering.ll
|
…
|
|
|
umulo-128-legalisation-lowering.ll
|
[SDAG] Fold umul_lohi with 0 or 1 multiplicand
|
2019-08-25 08:04:22 +00:00 |
|
unaligned-32-byte-memops.ll
|
…
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|
|
unaligned-load.ll
|
…
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|
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unaligned-spill-folding.ll
|
…
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|
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undef-eflags.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
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undef-globals-bss.ll
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…
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undef-label.ll
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…
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undef-ops.ll
|
…
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|
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unfold-masked-merge-scalar-constmask-innerouter.ll
|
…
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|
|
unfold-masked-merge-scalar-constmask-interleavedbits.ll
|
…
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|
|
unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
|
…
|
|
|
unfold-masked-merge-scalar-constmask-lowhigh.ll
|
…
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|
|
unfold-masked-merge-scalar-variablemask.ll
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…
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|
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unfold-masked-merge-vector-variablemask-const.ll
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…
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unfold-masked-merge-vector-variablemask.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
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unknown-location.ll
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…
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unreachable-loop-sinking.ll
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…
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|
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unreachable-mbb-undef-phi.mir
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…
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|
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unreachable-trap.ll
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Revert [Windows] Disable TrapUnreachable for Win64, add SEH_NoReturn
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2019-09-03 22:27:27 +00:00 |
|
unreachableblockelim.ll
|
…
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|
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unused_stackslots.ll
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…
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|
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unwind-init.ll
|
…
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|
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unwindraise.ll
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…
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|
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update-terminator-debugloc.ll
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
update-terminator.mir
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
|
2019-04-05 19:28:09 +00:00 |
|
urem-i8-constant.ll
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…
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|
|
urem-power-of-two.ll
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…
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|
|
urem-seteq-optsize.ll
|
[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 3)
|
2019-06-27 21:52:10 +00:00 |
|
urem-seteq-vec-nonsplat.ll
|
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
|
2019-08-07 11:43:13 +00:00 |
|
urem-seteq-vec-splat.ll
|
[NFC][X86][AArch64] Revisit test coverage for X s% C == 0 fold - add tests for negative divisors, INT_MIN divisors
|
2019-07-30 08:00:49 +00:00 |
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urem-seteq.ll
|
[NFC][X86][AArch64] Revisit test coverage for X s% C == 0 fold - add tests for negative divisors, INT_MIN divisors
|
2019-07-30 08:00:49 +00:00 |
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use-add-flags.ll
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…
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|
|
usub_sat.ll
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[X86] Remove redundant ';' chars ending IR lines in lit tests. NFC
|
2019-08-11 19:27:14 +00:00 |
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usub_sat_vec.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
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utf8.ll
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…
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utf16-cfstrings.ll
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…
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|
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uwtables.ll
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…
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|
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v2f32.ll
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…
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|
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v4f32-immediate.ll
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…
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|
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v4i32load-crash.ll
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…
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|
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v8i1-masks.ll
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…
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vaargs.ll
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…
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|
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vaes-intrinsics-avx-x86.ll
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…
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|
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vaes-intrinsics-avx512-x86.ll
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…
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|
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vaes-intrinsics-avx512vl-x86.ll
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…
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|
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var-permute-128.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
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var-permute-256.ll
|
[X86][SSE] Fold extract_subvector(vselect(x,y,z),0) -> vselect(extract_subvector(x,0),extract_subvector(y,0),extract_subvector(z,0))
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2019-06-22 17:57:01 +00:00 |
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var-permute-512.ll
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[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
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vararg-callee-cleanup.ll
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…
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vararg_no_start.ll
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…
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vararg_tailcall.ll
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…
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variable-sized-darwin-bzero.ll
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…
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variadic-node-pic.ll
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…
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vastart-defs-eflags.ll
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…
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vbinop-simplify-bug.ll
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…
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vec-copysign-avx512.ll
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…
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vec-copysign.ll
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…
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vec-libcalls.ll
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…
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vec-loadsingles-alignment.ll
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…
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vec-trunc-store.ll
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…
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vec3.ll
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…
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vec_align.ll
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[X86] Autogenerate vec_* tests. NFC
|
2019-08-20 23:11:29 +00:00 |
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vec_align_i256.ll
|
[X86] Autogenerate vec_* tests. NFC
|
2019-08-20 23:11:29 +00:00 |
|
vec_anyext.ll
|
[X86] Autogenerate vec_* tests. NFC
|
2019-08-20 23:11:29 +00:00 |
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vec_call.ll
|
[X86] Autogenerate vec_* tests. NFC
|
2019-08-20 23:11:29 +00:00 |
|
vec_cast.ll
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[TargetLowering] Teach computeRegisterProperties to only widen v3i16/v3f16 vectors to the next power of 2 type if that's legal.
|
2019-08-18 06:28:06 +00:00 |
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vec_cast2.ll
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Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
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2019-08-07 16:33:37 +00:00 |
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vec_cast3.ll
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Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
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2019-08-07 16:33:37 +00:00 |
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vec_cmp_sint-128.ll
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…
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vec_cmp_uint-128.ll
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…
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vec_compare-sse4.ll
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…
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vec_compare.ll
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…
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vec_ctbits.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
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vec_ext_inreg.ll
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…
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vec_extract-avx.ll
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[X86] Add DAG combine to turn (vzmovl (insert_subvector undef, X, 0)) into (insert_subvector allzeros, (vzmovl X), 0)
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2019-06-21 19:10:21 +00:00 |
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vec_extract-mmx.ll
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[X86] Add custom type legalization for bitcasting mmx to v2i32/v4i16/v8i8 to use movq2dq instead of going through memory.
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2019-08-15 18:23:37 +00:00 |
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vec_extract-sse4.ll
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…
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vec_extract.ll
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[X86][SSE] LowerINSERT_VECTOR_ELT - early out for out of range indices
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2019-07-05 10:34:53 +00:00 |
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vec_fabs.ll
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…
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vec_floor.ll
|
[X86][InstCombine] Remove InstCombine code that turns X86 round intrinsics into llvm.ceil/floor. Remove some isel patterns that existed because that was happening.
|
2019-05-22 20:04:55 +00:00 |
|
vec_fneg.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to some X86/ and XCore/ tests."
|
2019-06-13 19:24:51 +00:00 |
|
vec_fp_to_int.ll
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[X86] Enable fp128 as a legal type with SSE1 rather than with MMX.
|
2019-09-02 20:16:30 +00:00 |
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vec_fpext.ll
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[X86] Remove avx512 isel patterns for fpextend+load. Prefer to only match fp extloads instead.
|
2019-05-31 06:21:53 +00:00 |
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vec_fptrunc.ll
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[x86] split 256-bit store of concatenated vectors
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2019-06-04 16:40:04 +00:00 |
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vec_i64.ll
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…
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vec_ins_extract-1.ll
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…
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vec_ins_extract.ll
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…
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vec_insert-2.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
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vec_insert-3.ll
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…
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vec_insert-4.ll
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…
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vec_insert-5.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
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vec_insert-7.ll
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[X86] Add custom type legalization for bitcasting mmx to v2i32/v4i16/v8i8 to use movq2dq instead of going through memory.
|
2019-08-15 18:23:37 +00:00 |
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vec_insert-8.ll
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…
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vec_insert-9.ll
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…
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vec_insert-mmx.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vec_int_to_fp.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
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vec_loadsingles.ll
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…
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vec_logical.ll
|
Revert "[NFC][CodeGen] Add unary FNeg tests to some X86/ and XCore/ tests."
|
2019-06-13 19:24:51 +00:00 |
|
vec_minmax_match.ll
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…
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vec_minmax_sint.ll
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[TargetLowering] SimplifyMultipleUseDemandedBits - add VECTOR_SHUFFLE support.
|
2019-07-23 15:35:55 +00:00 |
|
vec_minmax_uint.ll
|
[TargetLowering] SimplifyMultipleUseDemandedBits - add VECTOR_SHUFFLE support.
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2019-07-23 15:35:55 +00:00 |
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vec_partial.ll
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…
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vec_reassociate.ll
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…
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vec_return.ll
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…
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vec_round.ll
|
[X86] Autogenerate vec_* tests. NFC
|
2019-08-20 23:11:29 +00:00 |
|
vec_saddo.ll
|
[DAGCombiner][X86] Teach visitCONCAT_VECTORS to combine (concat_vectors (concat_vectors X, Y), undef)) -> (concat_vectors X, Y, undef, undef)
|
2019-08-20 22:12:50 +00:00 |
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vec_sdiv_to_shift.ll
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…
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vec_set-2.ll
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…
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vec_set-3.ll
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…
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vec_set-4.ll
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…
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|
|
vec_set-6.ll
|
…
|
|
|
vec_set-7.ll
|
…
|
|
|
vec_set-8.ll
|
…
|
|
|
vec_set-A.ll
|
…
|
|
|
vec_set-B.ll
|
…
|
|
|
vec_set-C.ll
|
…
|
|
|
vec_set-D.ll
|
…
|
|
|
vec_set-F.ll
|
…
|
|
|
vec_set-H.ll
|
…
|
|
|
vec_set.ll
|
…
|
|
|
vec_setcc-2.ll
|
[x86] use psubus for more vsetcc lowering (PR39859)
|
2019-04-23 15:20:17 +00:00 |
|
vec_setcc.ll
|
[TargetLowering] Teach computeRegisterProperties to only widen v3i16/v3f16 vectors to the next power of 2 type if that's legal.
|
2019-08-18 06:28:06 +00:00 |
|
vec_shift.ll
|
…
|
|
|
vec_shift2.ll
|
…
|
|
|
vec_shift3.ll
|
…
|
|
|
vec_shift4.ll
|
…
|
|
|
vec_shift5.ll
|
…
|
|
|
vec_shift6.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vec_shift7.ll
|
…
|
|
|
vec_shuf-insert.ll
|
[X86] Autogenerate vec_* tests. NFC
|
2019-08-20 23:11:29 +00:00 |
|
vec_smulo.ll
|
[DAGCombiner][X86] Teach visitCONCAT_VECTORS to combine (concat_vectors (concat_vectors X, Y), undef)) -> (concat_vectors X, Y, undef, undef)
|
2019-08-20 22:12:50 +00:00 |
|
vec_split.ll
|
[X86] Autogenerate vec_* tests. NFC
|
2019-08-20 23:11:29 +00:00 |
|
vec_ss_load_fold.ll
|
…
|
|
|
vec_ssubo.ll
|
[DAGCombiner][X86] Teach visitCONCAT_VECTORS to combine (concat_vectors (concat_vectors X, Y), undef)) -> (concat_vectors X, Y, undef, undef)
|
2019-08-20 22:12:50 +00:00 |
|
vec_trunc_sext.ll
|
[X86] Autogenerate vec_* tests. NFC
|
2019-08-20 23:11:29 +00:00 |
|
vec_uaddo.ll
|
[DAGCombiner][X86] Teach visitCONCAT_VECTORS to combine (concat_vectors (concat_vectors X, Y), undef)) -> (concat_vectors X, Y, undef, undef)
|
2019-08-20 22:12:50 +00:00 |
|
vec_udiv_to_shift.ll
|
[X86] Autogenerate vec_* tests. NFC
|
2019-08-20 23:11:29 +00:00 |
|
vec_uint_to_fp-fastmath.ll
|
…
|
|
|
vec_uint_to_fp.ll
|
…
|
|
|
vec_umulo.ll
|
[DAGCombiner][X86] Teach visitCONCAT_VECTORS to combine (concat_vectors (concat_vectors X, Y), undef)) -> (concat_vectors X, Y, undef, undef)
|
2019-08-20 22:12:50 +00:00 |
|
vec_unsafe-fp-math.ll
|
…
|
|
|
vec_usubo.ll
|
[DAGCombiner][X86] Teach visitCONCAT_VECTORS to combine (concat_vectors (concat_vectors X, Y), undef)) -> (concat_vectors X, Y, undef, undef)
|
2019-08-20 22:12:50 +00:00 |
|
vec_zero-2.ll
|
[X86] Autogenerate vec_* tests. NFC
|
2019-08-20 23:11:29 +00:00 |
|
vec_zero.ll
|
…
|
|
|
vec_zero_cse.ll
|
…
|
|
|
vecloadextract.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
vector-bitreverse.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-blend.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-compare-all_of.ll
|
[X86][SSE] Fold movmsk(not(x)) -> not(movmsk)
|
2019-05-17 17:56:25 +00:00 |
|
vector-compare-any_of.ll
|
[X86][SSE] Fold movmsk(not(x)) -> not(movmsk)
|
2019-05-17 17:56:25 +00:00 |
|
vector-compare-combines.ll
|
…
|
|
|
vector-compare-results.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-compare-simplify.ll
|
…
|
|
|
vector-constrained-fp-intrinsics-fma.ll
|
…
|
|
|
vector-constrained-fp-intrinsics.ll
|
[FPEnv] Add fptosi and fptoui constrained intrinsics.
|
2019-08-28 16:33:36 +00:00 |
|
vector-ext-logic.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-extend-inreg.ll
|
[X86] Use vmovq for v4i64/v4f64/v8i64/v8f64 vzmovl.
|
2019-06-21 17:24:21 +00:00 |
|
vector-fshl-128.ll
|
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
|
2019-08-07 11:43:13 +00:00 |
|
vector-fshl-256.ll
|
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
|
2019-08-07 11:43:13 +00:00 |
|
vector-fshl-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-fshl-rot-128.ll
|
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
|
2019-08-07 11:43:13 +00:00 |
|
vector-fshl-rot-256.ll
|
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
|
2019-08-07 11:43:13 +00:00 |
|
vector-fshl-rot-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-fshr-128.ll
|
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
|
2019-08-07 11:43:13 +00:00 |
|
vector-fshr-256.ll
|
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
|
2019-08-07 11:43:13 +00:00 |
|
vector-fshr-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-fshr-rot-128.ll
|
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
|
2019-08-07 11:43:13 +00:00 |
|
vector-fshr-rot-256.ll
|
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
|
2019-08-07 11:43:13 +00:00 |
|
vector-fshr-rot-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-gep.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-half-conversions.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-idiv-sdiv-128.ll
|
[DAGCombiner][X86][AArch64] (x - C) + y -> (x + y) - C fold. Try 2
|
2019-05-30 20:37:49 +00:00 |
|
vector-idiv-sdiv-256.ll
|
[DAGCombiner][X86][AArch64] (x - C) + y -> (x + y) - C fold. Try 2
|
2019-05-30 20:37:49 +00:00 |
|
vector-idiv-sdiv-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-idiv-udiv-128.ll
|
[X86][SSE] Lower shuffle as ANY_EXTEND_VECTOR_INREG
|
2019-08-10 16:46:07 +00:00 |
|
vector-idiv-udiv-256.ll
|
[X86] lowerBuildVectorToBitOp - support build_vector(shift()) -> shift(build_vector(),C)
|
2019-05-25 18:02:17 +00:00 |
|
vector-idiv-udiv-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-idiv-v2i32.ll
|
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
|
2019-08-07 16:33:37 +00:00 |
|
vector-idiv.ll
|
…
|
|
|
vector-interleave.ll
|
…
|
|
|
vector-intrinsics.ll
|
…
|
|
|
vector-lzcnt-128.ll
|
…
|
|
|
vector-lzcnt-256.ll
|
…
|
|
|
vector-lzcnt-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-lzcnt-sub128.ll
|
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
|
2019-08-07 16:33:37 +00:00 |
|
vector-merge-store-fp-constants.ll
|
…
|
|
|
vector-mul.ll
|
[X86] In decomposeMulByConstant, legalize the VT before querying whether the multiply is legal
|
2019-08-01 18:49:07 +00:00 |
|
vector-mulfix-legalize.ll
|
[DAGCombiner] Add simple folds for SMULFIX/UMULFIX/SMULFIXSAT
|
2019-08-16 13:16:48 +00:00 |
|
vector-narrow-binop.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-partial-undef.ll
|
…
|
|
|
vector-pcmp.ll
|
[SelectionDAG] computeKnownBits - support constant pool values from target
|
2019-05-24 10:03:11 +00:00 |
|
vector-popcnt-128.ll
|
…
|
|
|
vector-popcnt-256.ll
|
…
|
|
|
vector-popcnt-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-reduce-add.ll
|
[X86] Teach lowerV4I32Shuffle to only use broadcasts if the mask has more than one undef element. Prioritize shifts over broadcast in lowerV8I16Shuffle.
|
2019-08-19 18:15:50 +00:00 |
|
vector-reduce-and-bool.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-reduce-and.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-reduce-fadd-fast.ll
|
[SDAG][x86] check for relaxed math when matching an FP reduction
|
2019-08-15 12:43:15 +00:00 |
|
vector-reduce-fadd.ll
|
Change semantics of fadd/fmul vector reductions.
|
2019-06-11 08:22:10 +00:00 |
|
vector-reduce-fmax-nnan.ll
|
Improve reduction intrinsics by overloading result value.
|
2019-06-13 09:37:38 +00:00 |
|
vector-reduce-fmax.ll
|
Improve reduction intrinsics by overloading result value.
|
2019-06-13 09:37:38 +00:00 |
|
vector-reduce-fmin-nnan.ll
|
Improve reduction intrinsics by overloading result value.
|
2019-06-13 09:37:38 +00:00 |
|
vector-reduce-fmin.ll
|
Improve reduction intrinsics by overloading result value.
|
2019-06-13 09:37:38 +00:00 |
|
vector-reduce-fmul-fast.ll
|
Change semantics of fadd/fmul vector reductions.
|
2019-06-11 08:22:10 +00:00 |
|
vector-reduce-fmul.ll
|
Change semantics of fadd/fmul vector reductions.
|
2019-06-11 08:22:10 +00:00 |
|
vector-reduce-mul.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-reduce-or-bool.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-reduce-or.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-reduce-smax.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-reduce-smin.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-reduce-umax.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-reduce-umin.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-reduce-xor-bool.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-reduce-xor.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-rem.ll
|
…
|
|
|
vector-rotate-128.ll
|
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
|
2019-08-07 11:43:13 +00:00 |
|
vector-rotate-256.ll
|
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
|
2019-08-07 11:43:13 +00:00 |
|
vector-rotate-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-sext.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-shift-ashr-128.ll
|
…
|
|
|
vector-shift-ashr-256.ll
|
[DAGCombiner] try to move bitcast after extract_subvector
|
2019-05-12 14:43:20 +00:00 |
|
vector-shift-ashr-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-shift-ashr-sub128.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-shift-by-select-loop.ll
|
Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
|
vector-shift-lshr-128.ll
|
[CodeGenPrepare][x86] shift both sides of a vector select when profitable
|
2019-06-16 15:29:03 +00:00 |
|
vector-shift-lshr-256.ll
|
[X86][SSE] Add SSE vector shift support to SimplifyDemandedVectorEltsForTargetNode vector splitting
|
2019-05-01 13:51:09 +00:00 |
|
vector-shift-lshr-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-shift-lshr-sub128.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-shift-shl-128.ll
|
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
|
2019-08-07 11:43:13 +00:00 |
|
vector-shift-shl-256.ll
|
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::VECTOR_SHUFFLE
|
2019-08-07 11:43:13 +00:00 |
|
vector-shift-shl-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-shift-shl-sub128.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-shuffle-128-unpck.ll
|
…
|
|
|
vector-shuffle-128-v2.ll
|
[X86] In lowerVectorShuffle, instead of creating a new node to canonicalize the shuffle mask by commuting, just commute the mask and swap V1/V2.
|
2019-07-23 18:46:15 +00:00 |
|
vector-shuffle-128-v4.ll
|
[X86] Teach lowerV4I32Shuffle to only use broadcasts if the mask has more than one undef element. Prioritize shifts over broadcast in lowerV8I16Shuffle.
|
2019-08-19 18:15:50 +00:00 |
|
vector-shuffle-128-v8.ll
|
[X86] Teach lowerV4I32Shuffle to only use broadcasts if the mask has more than one undef element. Prioritize shifts over broadcast in lowerV8I16Shuffle.
|
2019-08-19 18:15:50 +00:00 |
|
vector-shuffle-128-v16.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-shuffle-256-v4.ll
|
[X86][AVX] Add PR34359 shuffle test case.
|
2019-07-12 17:42:32 +00:00 |
|
vector-shuffle-256-v8.ll
|
[X86][SSE] Lower shuffle as ANY_EXTEND_VECTOR_INREG
|
2019-08-10 16:46:07 +00:00 |
|
vector-shuffle-256-v16.ll
|
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
|
2019-07-04 10:17:10 +00:00 |
|
vector-shuffle-256-v32.ll
|
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
|
2019-07-04 10:17:10 +00:00 |
|
vector-shuffle-512-v8.ll
|
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
|
2019-06-25 10:51:15 +00:00 |
|
vector-shuffle-512-v16.ll
|
[X86] Teach lowerV4I32Shuffle to only use broadcasts if the mask has more than one undef element. Prioritize shifts over broadcast in lowerV8I16Shuffle.
|
2019-08-19 18:15:50 +00:00 |
|
vector-shuffle-512-v32.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-shuffle-512-v64.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-shuffle-avx512.ll
|
[X86] EltsFromConsecutiveLoads - Don't confuse elt count with vector element count (PR43170)
|
2019-08-31 16:21:31 +00:00 |
|
vector-shuffle-combining-avx.ll
|
[X86][AVX] Decode constant bits from insert_subvector(c1, c2, c3)
|
2019-06-15 17:05:24 +00:00 |
|
vector-shuffle-combining-avx2.ll
|
[X86] Use vmovq for v4i64/v4f64/v8i64/v8f64 vzmovl.
|
2019-06-21 17:24:21 +00:00 |
|
vector-shuffle-combining-avx512bw.ll
|
[X86][AVX] Decode constant bits from insert_subvector(c1, c2, c3)
|
2019-06-15 17:05:24 +00:00 |
|
vector-shuffle-combining-avx512bwvl.ll
|
…
|
|
|
vector-shuffle-combining-avx512vbmi.ll
|
[X86][AVX] Combine non-lane crossing binary shuffles using X86ISD::VPERMV3
|
2019-04-28 14:31:01 +00:00 |
|
vector-shuffle-combining-sse4a.ll
|
…
|
|
|
vector-shuffle-combining-sse41.ll
|
…
|
|
|
vector-shuffle-combining-ssse3.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
vector-shuffle-combining-xop.ll
|
[X86][AVX] Decode constant bits from insert_subvector(c1, c2, c3)
|
2019-06-15 17:05:24 +00:00 |
|
vector-shuffle-combining.ll
|
[DAGCombiner] (insert_vector_elt (vector_shuffle X, Y), (extract_vector_elt X, N), IdxC) -> (vector_shuffle X, Y)
|
2019-08-29 10:35:51 +00:00 |
|
vector-shuffle-masked.ll
|
…
|
|
|
vector-shuffle-mmx.ll
|
…
|
|
|
vector-shuffle-sse1.ll
|
[X86] Separate the memory size of vzext_load/vextract_store from the element size of the result type. Use them improve the codegen of v2f32 loads/stores with sse1 only.
|
2019-07-15 02:02:31 +00:00 |
|
vector-shuffle-sse4a.ll
|
…
|
|
|
vector-shuffle-sse41.ll
|
…
|
|
|
vector-shuffle-v1.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-shuffle-v48.ll
|
[X86][SSE] Regenerate v48 shuffle test on a variety of targets
|
2019-06-27 11:22:23 +00:00 |
|
vector-shuffle-variable-128.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
vector-shuffle-variable-256.ll
|
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
|
2019-07-06 17:59:57 +00:00 |
|
vector-sqrt.ll
|
…
|
|
|
vector-trunc-math.ll
|
[X86] When using AND+PACKUS in lowerV16I8Shuffle, generate the build vector directly in v16i8 with the correct 0x00 or 0xFF elements rather than using another VT and bitcasting it.
|
2019-07-22 19:58:49 +00:00 |
|
vector-trunc-packus.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-trunc-ssat.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-trunc-usat.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-trunc.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-truncate-combine.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vector-tzcnt-128.ll
|
…
|
|
|
vector-tzcnt-256.ll
|
…
|
|
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vector-tzcnt-512.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-unsigned-cmp.ll
|
…
|
|
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vector-variable-idx.ll
|
…
|
|
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vector-variable-idx2.ll
|
…
|
|
|
vector-width-store-merge.ll
|
[X86] Remove what little support we had for MPX
|
2019-08-29 18:09:02 +00:00 |
|
vector-zext.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
vector-zmov.ll
|
[X86] Add a DAG combine to turn vzmovl+load into vzload if the load isn't volatile. Remove isel patterns for vzmovl+load
|
2019-06-25 17:08:26 +00:00 |
|
vector.ll
|
…
|
|
|
vector_splat-const-shift-of-constmasked.ll
|
[NFC][CodeGen][X86][AArch64] Add and-const-mask + const-shift pattern tests
|
2019-05-14 20:17:04 +00:00 |
|
vectorcall.ll
|
…
|
|
|
version_directive.ll
|
…
|
|
|
vfcmp.ll
|
…
|
|
|
viabs.ll
|
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
|
2019-08-30 17:35:08 +00:00 |
|
virtreg-physreg-def-regallocfast.mir
|
[RegAllocFast] Scan physcial reg definitions before assigning virtual reg definitions
|
2019-05-08 18:30:26 +00:00 |
|
virtual-registers-cleared-in-machine-functions-liveins.ll
|
…
|
|
|
visibility.ll
|
…
|
|
|
visibility2.ll
|
…
|
|
|
vmaskmov-offset.ll
|
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
|
2019-06-19 00:25:39 +00:00 |
|
vmovq.ll
|
…
|
|
|
volatile-memstores-nooverlapping-load-stores.ll
|
Fixing @llvm.memcpy not honoring volatile.
|
2019-07-09 09:53:36 +00:00 |
|
volatile.ll
|
…
|
|
|
vortex-bug.ll
|
…
|
|
|
vp2intersect_multiple_pairs.ll
|
[X86] Regenerate vp2intersect tests
|
2019-07-31 12:17:10 +00:00 |
|
vpshufbitqbm-intrinsics-upgrade.ll
|
…
|
|
|
vpshufbitqbm-intrinsics.ll
|
…
|
|
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vsel-cmp-load.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vselect-2.ll
|
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
|
2019-07-08 06:52:49 +00:00 |
|
vselect-avx.ll
|
[CodeGen][SelectionDAG] More efficient code for X % C == 0 (SREM case)
|
2019-08-13 14:57:37 +00:00 |
|
vselect-constants.ll
|
…
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|
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vselect-minmax.ll
|
…
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|
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vselect-packss.ll
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…
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|
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vselect-pcmp.ll
|
…
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|
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vselect-zero.ll
|
…
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vselect.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vshift-1.ll
|
…
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|
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vshift-2.ll
|
…
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vshift-3.ll
|
…
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|
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vshift-4.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
vshift-5.ll
|
…
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|
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vshift-6.ll
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…
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|
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vshift_scalar.ll
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…
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|
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vshift_split.ll
|
…
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|
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vshift_split2.ll
|
…
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|
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vsplit-and.ll
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…
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|
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vzero-excess.ll
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…
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|
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waitpkg-intrinsics.ll
|
…
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|
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warn-stack.ll
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…
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|
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wbinvd-intrinsic.ll
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…
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|
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wbnoinvd-intrinsic.ll
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…
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|
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weak-undef.ll
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…
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weak.ll
|
…
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|
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weak_def_can_be_hidden.ll
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…
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|
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webkit-jscc.ll
|
…
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|
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wide-fma-contraction.ll
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…
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|
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wide-integer-cmp.ll
|
…
|
|
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wide-integer-fold.ll
|
…
|
|
|
widen_arith-1.ll
|
Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
|
widen_arith-2.ll
|
Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
|
widen_arith-3.ll
|
Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
|
widen_arith-4.ll
|
Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
|
widen_arith-5.ll
|
Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
|
widen_arith-6.ll
|
Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
|
widen_bitops-0.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
widen_bitops-1.ll
|
…
|
|
|
widen_cast-1.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
widen_cast-2.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
widen_cast-3.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
widen_cast-4.ll
|
Revert [MBP] Disable aggressive loop rotate in plain mode
|
2019-08-29 19:03:58 +00:00 |
|
widen_cast-5.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
widen_cast-6.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
widen_compare-1.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
widen_conv-1.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
widen_conv-2.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
widen_conv-3.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
widen_conv-4.ll
|
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
|
2019-08-07 16:24:26 +00:00 |
|
widen_conversions.ll
|
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
|
2019-08-07 16:33:37 +00:00 |
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widen_extract-1.ll
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…
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widen_load-0.ll
|
…
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|
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widen_load-1.ll
|
…
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|
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widen_load-2.ll
|
[TargetLowering] Teach computeRegisterProperties to only widen v3i16/v3f16 vectors to the next power of 2 type if that's legal.
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2019-08-18 06:28:06 +00:00 |
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widen_load-3.ll
|
[x86] avoid vector load narrowing with extracted store uses (PR42305)
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2019-06-19 18:13:47 +00:00 |
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widen_mul.ll
|
Recommit r368079 "[X86] Remove uses of the -x86-experimental-vector-widening-legalization flag from test/CodeGen/X86/"
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2019-08-07 16:33:37 +00:00 |
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widen_shuffle-1.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
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2019-08-07 16:24:26 +00:00 |
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widened-broadcast.ll
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…
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win-alloca-expander.ll
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…
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win-catchpad-csrs.ll
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[X86] Print register names in .seh_* directives
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2019-08-30 21:23:05 +00:00 |
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win-catchpad-nested-cxx.ll
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…
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win-catchpad-nested.ll
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…
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win-catchpad-varargs.ll
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…
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win-catchpad.ll
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[X86] Print register names in .seh_* directives
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2019-08-30 21:23:05 +00:00 |
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win-cleanuppad.ll
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…
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win-funclet-cfi.ll
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[X86] Print register names in .seh_* directives
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2019-08-30 21:23:05 +00:00 |
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win-mixed-ehpersonality.ll
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…
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win-smallparams.ll
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…
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win32-bool.ll
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…
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win32-eh-available-externally.ll
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IR: print value numbers for unnamed function arguments
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2019-08-03 14:28:34 +00:00 |
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win32-eh-states.ll
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…
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win32-eh.ll
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…
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win32-pic-jumptable.ll
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…
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win32-preemption.ll
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…
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win32-seh-catchpad-realign.ll
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…
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win32-seh-catchpad.ll
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…
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win32-seh-nested-finally.ll
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…
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win32-spill-xmm.ll
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…
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win32-ssp.ll
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…
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win32_sret.ll
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…
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win64-bool.ll
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…
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win64-byval.ll
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…
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win64-funclet-savexmm.ll
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[X86] Print register names in .seh_* directives
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2019-08-30 21:23:05 +00:00 |
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win64-jumptable.ll
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…
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win64-long-double.ll
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…
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win64-nosse-csrs.ll
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…
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win64_alloca_dynalloca.ll
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…
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win64_call_epi.ll
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Revert [Windows] Disable TrapUnreachable for Win64, add SEH_NoReturn
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2019-09-03 22:27:27 +00:00 |
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win64_eh.ll
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Revert [Windows] Disable TrapUnreachable for Win64, add SEH_NoReturn
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2019-09-03 22:27:27 +00:00 |
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win64_eh_leaf.ll
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[llvm-readobj] Change -long-option to --long-option in tests. NFC
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2019-05-01 05:27:20 +00:00 |
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win64_eh_leaf2.ll
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…
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win64_frame.ll
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[X86] Print register names in .seh_* directives
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2019-08-30 21:23:05 +00:00 |
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win64_nonvol.ll
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…
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win64_params.ll
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…
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win64_sibcall.ll
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…
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win64_vararg.ll
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…
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win_chkstk.ll
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…
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win_coreclr_chkstk.ll
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[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
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2019-05-25 06:17:47 +00:00 |
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win_coreclr_chkstk_liveins.mir
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Describe stack-id as an enum
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2019-06-17 09:13:29 +00:00 |
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win_cst_pool.ll
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Standardize on MSVC behavior for triples with no environment
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2019-07-08 21:05:20 +00:00 |
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windows-itanium-alloca.ll
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…
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wineh-coreclr.ll
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…
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wineh-exceptionpointer.ll
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…
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wineh-no-ehpads.ll
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…
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x32-cet-intrinsics.ll
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…
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x32-function_pointer-1.ll
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…
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x32-function_pointer-2.ll
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…
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x32-function_pointer-3.ll
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…
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x32-indirectbr.ll
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…
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x32-landingpad.ll
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…
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x32-lea-1.ll
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…
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x32-movtopush64.ll
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…
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x32-va_start.ll
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…
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x64-cet-intrinsics.ll
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…
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x86-16.ll
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…
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x86-32-intrcc.ll
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…
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x86-32-vector-calling-conv.ll
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…
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x86-64-and-mask.ll
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…
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x86-64-arg.ll
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…
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x86-64-asm.ll
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…
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x86-64-baseptr.ll
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…
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x86-64-bittest-logic.ll
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…
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x86-64-call.ll
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…
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x86-64-disp.ll
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…
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x86-64-double-precision-shift-left.ll
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…
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x86-64-double-precision-shift-right.ll
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…
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x86-64-double-shifts-Oz-Os-O2.ll
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…
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x86-64-double-shifts-var.ll
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…
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x86-64-extend-shift.ll
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…
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x86-64-flags-intrinsics.ll
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[X86] Print register names in .seh_* directives
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2019-08-30 21:23:05 +00:00 |
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x86-64-gv-offset.ll
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…
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x86-64-intrcc-nosse.ll
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…
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x86-64-intrcc.ll
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…
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x86-64-jumps.ll
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…
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x86-64-mem.ll
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…
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x86-64-ms_abi-vararg.ll
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…
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x86-64-pic-1.ll
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…
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x86-64-pic-2.ll
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…
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x86-64-pic-3.ll
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…
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x86-64-pic-4.ll
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…
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x86-64-pic-5.ll
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…
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x86-64-pic-6.ll
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…
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x86-64-pic-7.ll
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…
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x86-64-pic-8.ll
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x86-64-pic-9.ll
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…
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x86-64-pic-10.ll
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x86-64-pic-11.ll
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…
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x86-64-pic-12.ll
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…
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x86-64-pic.ll
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…
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x86-64-plt-relative-reloc.ll
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…
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x86-64-psub.ll
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…
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x86-64-ptr-arg-simple.ll
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…
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x86-64-ret0.ll
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…
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x86-64-shortint.ll
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…
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x86-64-sret-return-2.ll
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…
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x86-64-sret-return.ll
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…
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x86-64-stack-and-frame-ptr.ll
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…
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x86-64-static-relo-movl.ll
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…
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x86-64-tls-1.ll
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x86-64-varargs.ll
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x86-64-veccallcc.ll
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x86-big-ret.ll
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x86-cmov-converter.ll
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[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
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2019-06-14 23:08:59 +00:00 |
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x86-flags-intrinsics.ll
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…
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x86-fold-pshufb.ll
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…
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x86-framelowering-trap.ll
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…
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x86-inline-asm-validation.ll
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…
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x86-interleaved-access.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
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2019-08-07 16:24:26 +00:00 |
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x86-interleaved-check.ll
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…
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x86-interrupt_cc.ll
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[WinEH] Allocate space in funclets stack to save XMM CSRs
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2019-08-27 01:53:24 +00:00 |
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x86-interrupt_cld.ll
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…
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x86-interrupt_vzeroupper.ll
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…
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x86-mixed-alignment-dagcombine.ll
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[X86] Automatically generate various tests. NFC
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2019-08-26 13:53:29 +00:00 |
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x86-no_caller_saved_registers-preserve.ll
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[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
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2019-05-06 21:39:51 +00:00 |
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x86-no_caller_saved_registers.ll
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…
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x86-plt-relative-reloc.ll
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…
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x86-repmov-copy-eflags.ll
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…
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x86-sanitizer-shrink-wrapping.ll
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…
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x86-setcc-int-to-fp-combine.ll
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…
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x86-shifts.ll
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Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
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2019-08-07 16:24:26 +00:00 |
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x86-shrink-wrap-unwind.ll
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…
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x86-shrink-wrapping.ll
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[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
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2019-06-25 17:29:18 +00:00 |
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x86-store-gv-addr.ll
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x86-upgrade-avx-vbroadcast.ll
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x86-upgrade-avx2-vbroadcast.ll
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x86-win64-shrink-wrapping.ll
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…
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x86_64-mul-by-const.ll
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…
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x87.ll
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…
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xaluo.ll
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[DAGCombiner][X86][SystemZ] Canonicalize SSUBO with immediate RHS to SADDO by negating the immediate.
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2019-04-09 18:33:56 +00:00 |
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xchg-nofold.ll
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[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
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2019-06-13 13:56:19 +00:00 |
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xmm-r64.ll
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…
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xmulo.ll
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…
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xop-ifma.ll
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[X86] Add a hack to combinePMULDQ to manually turn SIGN_EXTEND_VECTOR_INREG/ZERO_EXTEND_VECTOR_INREG inputs into an ANY_EXTEND_VECTOR_INREG style shuffle
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2019-08-26 18:23:26 +00:00 |
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xop-intrinsics-fast-isel.ll
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…
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xop-intrinsics-x86_64-upgrade.ll
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…
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xop-intrinsics-x86_64.ll
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…
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xop-mask-comments.ll
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…
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xop-pcmov.ll
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…
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xor-combine-debugloc.ll
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Rename ExpandISelPseudo->FinalizeISel, delay register reservation
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2019-06-19 00:25:39 +00:00 |
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xor-icmp.ll
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…
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xor-select-i1-combine.ll
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…
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xor.ll
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Revert r368276 "[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::EXTRACT_VECTOR_ELT"
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2019-08-13 09:33:25 +00:00 |
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xray-attribute-instrumentation.ll
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…
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xray-custom-log.ll
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…
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xray-empty-firstmbb.mir
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…
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xray-empty-function.mir
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…
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xray-log-args.ll
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…
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xray-loop-detection.ll
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…
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xray-multiplerets-in-blocks.mir
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…
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xray-section-group.ll
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…
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xray-selective-instrumentation-miss.ll
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…
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xray-selective-instrumentation.ll
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…
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xray-tail-call-sled.ll
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…
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xray-typed-event-log.ll
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…
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xtest.ll
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…
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zero-remat.ll
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…
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zext-demanded.ll
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…
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zext-extract_subreg.ll
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…
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zext-fold.ll
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…
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zext-inreg-0.ll
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…
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zext-inreg-1.ll
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…
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zext-logicop-shift-load.ll
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[TargetLowering][X86] Teach SimplifyDemandedBits to use ShrinkDemandedOp on ISD::SHL nodes.
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2019-04-12 06:49:28 +00:00 |
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zext-sext.ll
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[DAGCombiner][X86][AArch64][AMDGPU] (x + C) - y -> (x - y) + C fold. Try 3
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2019-05-30 20:36:54 +00:00 |
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zext-shl.ll
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zext-trunc.ll
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…
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zlib-longest-match.ll
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…
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