llvm-project/llvm/test/CodeGen
Chandler Carruth 41ed4034dd [x86] Revert the X86FoldTablesEmitter due to more miscompiles.
In testing, we've found yet another miscompile caused by the new tables.
And this one is even less clear how to fix (we could teach it to fold
a 16-bit load instead of the 32-bit load it wants, or block folding
entirely).

Also, the approach to excluding instructions seems increasingly to not
scale well.

I have left a more detailed analysis on the review log for the original
patch (https://reviews.llvm.org/D32684) along with suggested path
forward. I will land an additional test case that I wrote which covers
the code that was miscompiling (folding into the output of `pextrw`) in
a subsequent commit to keep this a pure revert.

For each commit reverted here, I've restricted the revert to the
non-test code touching the x86 fold table emission until the last commit
where I did revert the test updates. This means the *new* test cases
added for `insertps` and `xchg` remain untouched (and continue to pass).

Reverted commits:
r304540: [X86] Don't fold into memory operands into insertps in the ...
r304347: [TableGen] Adapt more places to getValueAsString now ...
r304163: [X86] Don't fold away the memory operand of an xchg.
r304123: Don't capture a temporary std::string in a StringRef.
r304122: Resubmit "[X86] Adding new LLVM TableGen backend that ..."

Original commit was in r304088, and after a string of fixes was reverted
previously in r304121 to fix build bots, and then re-landed in r304122.

llvm-svn: 304762
2017-06-06 02:15:31 +00:00
..
AArch64 [InlineSpiller] Don't spill fully undef values 2017-06-05 23:51:27 +00:00
AMDGPU RenameIndependentSubregs: Fix handling of undef tied operands 2017-06-05 22:58:57 +00:00
ARM [ARM] GlobalISel: Constrain callee register on indirect calls 2017-06-05 12:54:53 +00:00
AVR [AVR] Fix a big in shift operator lowering; Authored by Dr. Gergo Erdi 2017-05-31 06:27:46 +00:00
BPF [bpf] fix a bug which causes incorrect big endian reloc fixup 2017-05-05 18:05:00 +00:00
Generic CodeGen/LLVMTargetMachine: Refactor ISel pass construction; NFCI 2017-06-06 00:26:13 +00:00
Hexagon [Hexagon] Return 0 from getDotNewPredOp when .new opcode does not exist 2017-06-02 14:07:06 +00:00
Inputs
Lanai CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
MIR CodeGen: Refactor MIR parsing 2017-06-06 00:44:35 +00:00
MSP430 [MSP430] Fix PR33050: Don't use ADD16ri to lower FrameIndex. 2017-05-24 15:08:30 +00:00
Mips [mips][microMIPS] Extending size reduction pass with LBU16, LHU16, SB16 and SH16 2017-06-02 14:14:21 +00:00
NVPTX Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB." 2017-05-18 18:50:05 +00:00
Nios2 [Nios2] Target registration 2017-05-29 09:48:30 +00:00
PowerPC RegisterScavenging: Add ScavengerTest pass 2017-06-02 23:01:42 +00:00
SPARC Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB." 2017-05-18 18:50:05 +00:00
SystemZ [SystemZ] Simplify test case. NFC 2017-06-02 23:40:58 +00:00
Thumb Move machine-cse-physreg.mir to test/CodeGen/Thumb 2017-05-24 17:20:47 +00:00
Thumb2 MIR: remove explicit "noVRegs" property. 2017-05-30 21:28:57 +00:00
WebAssembly [wasm] Fix test after r304117. 2017-05-29 16:32:52 +00:00
WinEH
X86 [x86] Revert the X86FoldTablesEmitter due to more miscompiles. 2017-06-06 02:15:31 +00:00
XCore AsmPrinter: mark the beginning and the end of a function in verbose mode 2017-05-23 21:22:16 +00:00