forked from OSchip/llvm-project
538 lines
20 KiB
TableGen
538 lines
20 KiB
TableGen
//===--- HexagonPseudo.td -------------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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let PrintMethod = "printGlobalOperand" in {
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def globaladdress : Operand<i32>;
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def globaladdressExt : Operand<i32>;
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}
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let isPseudo = 1 in {
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let isCodeGenOnly = 0 in
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def A2_iconst : Pseudo<(outs IntRegs:$Rd32), (ins s23_2Imm:$Ii), "${Rd32}=iconst(#${Ii})">;
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def DUPLEX_Pseudo : InstHexagon<(outs), (ins s32_0Imm:$offset), "DUPLEX", [], "", DUPLEX, TypePSEUDO>;
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}
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let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
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isAsmParserOnly = 1 in
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def TFRI64_V2_ext : ALU64_rr<(outs DoubleRegs:$dst),
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(ins s32_0Imm:$src1, s8_0Imm:$src2),
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"$dst=combine(#$src1,#$src2)">;
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// HI/LO Instructions
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let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
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hasNewValue = 1, opNewValue = 0 in
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class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp>
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: InstHexagon<(outs IntRegs:$dst),
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(ins u16_0Imm:$imm_value),
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"$dst"#RegHalf#"=#$imm_value", [], "", ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, OpcodeHexagon {
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bits<5> dst;
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bits<32> imm_value;
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let Inst{27} = Rs;
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let Inst{26-24} = MajOp;
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let Inst{21} = MinOp;
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let Inst{20-16} = dst;
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let Inst{23-22} = imm_value{15-14};
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let Inst{13-0} = imm_value{13-0};
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}
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let isAsmParserOnly = 1 in {
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def LO : REG_IMMED<".l", 0b0, 0b001, 0b1>;
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def HI : REG_IMMED<".h", 0b0, 0b010, 0b1>;
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}
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let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in {
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def CONST32 : CONSTLDInst<(outs IntRegs:$Rd), (ins i32imm:$v),
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"$Rd = CONST32(#$v)", []>;
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def CONST64 : CONSTLDInst<(outs DoubleRegs:$Rd), (ins i64imm:$v),
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"$Rd = CONST64(#$v)", []>;
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}
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let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
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isCodeGenOnly = 1 in
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def PS_true : SInst<(outs PredRegs:$dst), (ins), "", []>;
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let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
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isCodeGenOnly = 1 in
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def PS_false : SInst<(outs PredRegs:$dst), (ins), "", []>;
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let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
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def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
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".error \"should not emit\" ", []>;
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let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
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def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
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".error \"should not emit\" ", []>;
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let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
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Defs = [PC, LC0], Uses = [SA0, LC0] in {
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def ENDLOOP0 : Endloop<(outs), (ins b30_2Imm:$offset),
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":endloop0",
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[]>;
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}
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let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
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Defs = [PC, LC1], Uses = [SA1, LC1] in {
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def ENDLOOP1 : Endloop<(outs), (ins b30_2Imm:$offset),
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":endloop1",
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[]>;
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}
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let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
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opExtendable = 0, hasSideEffects = 0 in
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class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0>
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: CRInst<(outs), (ins brOp:$offset, u10_0Imm:$src2),
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#mnemonic#"($offset,#$src2)",
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[], "" , CR_tc_3x_SLOT3> {
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bits<9> offset;
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bits<10> src2;
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let IClass = 0b0110;
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let Inst{27-22} = 0b100100;
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let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
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let Inst{20-16} = src2{9-5};
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let Inst{12-8} = offset{8-4};
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let Inst{7-5} = src2{4-2};
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let Inst{4-3} = offset{3-2};
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let Inst{1-0} = src2{1-0};
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}
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let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
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opExtendable = 0, hasSideEffects = 0 in
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class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0>
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: CRInst<(outs), (ins brOp:$offset, IntRegs:$src2),
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#mnemonic#"($offset,$src2)",
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[], "" ,CR_tc_3x_SLOT3> {
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bits<9> offset;
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bits<5> src2;
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let IClass = 0b0110;
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let Inst{27-22} = 0b000000;
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let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
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let Inst{20-16} = src2;
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let Inst{12-8} = offset{8-4};
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let Inst{4-3} = offset{3-2};
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}
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multiclass LOOP_ri<string mnemonic> {
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let isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
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def iext: LOOP_iBase<mnemonic, b30_2Imm, 1>;
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def rext: LOOP_rBase<mnemonic, b30_2Imm, 1>;
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}
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}
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let Defs = [SA0, LC0, USR] in
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defm J2_loop0 : LOOP_ri<"loop0">;
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// Interestingly only loop0's appear to set usr.lpcfg
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let Defs = [SA1, LC1] in
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defm J2_loop1 : LOOP_ri<"loop1">;
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let isCall = 1, hasSideEffects = 1, isPredicable = 0,
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isExtended = 0, isExtendable = 1, opExtendable = 0,
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isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in
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class T_Call<string ExtStr>
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: JInst<(outs), (ins a30_2Imm:$dst),
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"call " # ExtStr # "$dst", [], "", J_tc_2early_SLOT23> {
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let BaseOpcode = "call";
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bits<24> dst;
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let IClass = 0b0101;
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let Inst{27-25} = 0b101;
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let Inst{24-16,13-1} = dst{23-2};
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let Inst{0} = 0b0;
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}
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let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [R16],
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isPredicable = 0 in
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def CALLProfile : T_Call<"">;
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let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1,
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Defs = [PC, R31, R6, R7, P0] in
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def PS_call_stk : T_Call<"">;
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let isCall = 1, hasSideEffects = 1, cofMax1 = 1 in
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class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
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dag InputDag = (ins IntRegs:$Rs)>
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: JInst<(outs), InputDag,
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!if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
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"if ($Pu) callr $Rs"),
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"callr $Rs"),
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[], "", J_tc_2early_SLOT2> {
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bits<5> Rs;
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bits<2> Pu;
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let isPredicated = isPred;
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let isPredicatedFalse = isPredNot;
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let IClass = 0b0101;
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let Inst{27-25} = 0b000;
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let Inst{24-23} = !if (isPred, 0b10, 0b01);
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let Inst{22} = 0;
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let Inst{21} = isPredNot;
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let Inst{9-8} = !if (isPred, Pu, 0b00);
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let Inst{20-16} = Rs;
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}
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let isCodeGenOnly = 1 in {
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def PS_callr_nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return.
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}
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let isCall = 1, hasSideEffects = 1,
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isExtended = 0, isExtendable = 1, opExtendable = 0, isCodeGenOnly = 1,
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BaseOpcode = "PS_call_nr", isExtentSigned = 1, opExtentAlign = 2,
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Itinerary = J_tc_2early_SLOT23 in
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class Call_nr<bits<5> nbits, bit isPred, bit isFalse, dag iops>
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: Pseudo<(outs), iops, "">, PredRel {
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bits<2> Pu;
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bits<17> dst;
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let opExtentBits = nbits;
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let isPredicable = 0; // !if(isPred, 0, 1);
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let isPredicated = 0; // isPred;
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let isPredicatedFalse = isFalse;
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}
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def PS_call_nr : Call_nr<24, 0, 0, (ins s32_0Imm:$Ii)>;
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//def PS_call_nrt: Call_nr<17, 1, 0, (ins PredRegs:$Pu, s32_0Imm:$dst)>;
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//def PS_call_nrf: Call_nr<17, 1, 1, (ins PredRegs:$Pu, s32_0Imm:$dst)>;
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let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
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isPredicable = 1, hasSideEffects = 0, InputType = "reg",
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cofMax1 = 1 in
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class T_JMPr
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: InstHexagon<(outs), (ins IntRegs:$dst), "jumpr $dst", [],
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"", J_tc_2early_SLOT2, TypeJ>, OpcodeHexagon {
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bits<5> dst;
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let IClass = 0b0101;
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let Inst{27-21} = 0b0010100;
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let Inst{20-16} = dst;
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}
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// A return through builtin_eh_return.
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let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
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isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
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def EH_RETURN_JMPR : T_JMPr;
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// Indirect tail-call.
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let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
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isTerminator = 1, isCodeGenOnly = 1 in
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def PS_tailcall_r : T_JMPr;
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//
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// Direct tail-calls.
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let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
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isTerminator = 1, isCodeGenOnly = 1 in
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def PS_tailcall_i : Pseudo<(outs), (ins a30_2Imm:$dst), "", []>;
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let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in
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def PS_aligna : Pseudo<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>;
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// Generate frameindex addresses. The main reason for the offset operand is
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// that every instruction that is allowed to have frame index as an operand
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// will then have that operand followed by an immediate operand (the offset).
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// This simplifies the frame-index elimination code.
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//
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let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
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isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in {
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def PS_fi : Pseudo<(outs IntRegs:$Rd),
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(ins IntRegs:$fi, s32_0Imm:$off), "">;
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def PS_fia : Pseudo<(outs IntRegs:$Rd),
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(ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
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}
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class CondStr<string CReg, bit True, bit New> {
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string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
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}
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class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
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string S = Mnemonic # !if(Taken, ":t", ":nt");
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}
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let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
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hasSideEffects = 0, InputType = "reg", cofMax1 = 1 in
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class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>
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: InstHexagon<(outs), (ins PredRegs:$src, IntRegs:$dst),
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CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
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JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst",
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[], "", J_tc_2early_SLOT2, TypeJ>, OpcodeHexagon {
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let isTaken = isTak;
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let isPredicatedFalse = PredNot;
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let isPredicatedNew = isPredNew;
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bits<2> src;
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bits<5> dst;
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let IClass = 0b0101;
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let Inst{27-22} = 0b001101;
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let Inst{21} = PredNot;
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let Inst{20-16} = dst;
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let Inst{12} = isTak;
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let Inst{11} = isPredNew;
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let Inst{9-8} = src;
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}
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multiclass JMPR_Pred<bit PredNot> {
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def NAME : T_JMPr_c<PredNot, 0, 0>; // not taken
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// Predicate new
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def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken
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def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken
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}
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multiclass JMPR_base<string BaseOp> {
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let BaseOpcode = BaseOp in {
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def NAME : T_JMPr;
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defm t : JMPR_Pred<0>;
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defm f : JMPR_Pred<1>;
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}
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}
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let isTerminator = 1, hasSideEffects = 0, isReturn = 1, isCodeGenOnly = 1, isBarrier = 1 in
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defm PS_jmpret : JMPR_base<"JMPret">, PredNewRel;
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//defm V6_vtran2x2_map : HexagonMapping<(outs VectorRegs:$Vy32, VectorRegs:$Vx32), (ins VectorRegs:$Vx32in, IntRegs:$Rt32), "vtrans2x2(${Vy32},${Vx32},${Rt32})", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, VectorRegs:$Vx32in, IntRegs:$Rt32)>;
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// The reason for the custom inserter is to record all ALLOCA instructions
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// in MachineFunctionInfo.
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let Defs = [R29], isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 1 in
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def PS_alloca: InstHexagon<(outs IntRegs:$Rd),
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(ins IntRegs:$Rs, u32_0Imm:$A), "",
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[], "", ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>;
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// Load predicate.
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
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isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
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def LDriw_pred : LDInst<(outs PredRegs:$dst),
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(ins IntRegs:$addr, s32_0Imm:$off),
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".error \"should not emit\"", []>;
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// Load modifier.
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
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isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
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def LDriw_mod : LDInst<(outs ModRegs:$dst),
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(ins IntRegs:$addr, s32_0Imm:$off),
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".error \"should not emit\"", []>;
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// Vector load
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let Predicates = [HasV60T, UseHVX] in
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let mayLoad = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in
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class V6_LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = CVI_VM_LD,
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IType type = TypeCVI_VM_LD>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
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// Vector store
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let Predicates = [HasV60T, UseHVX] in
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let mayStore = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in
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class V6_STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = CVI_VM_ST,
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IType type = TypeCVI_VM_ST>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
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let isCodeGenOnly = 1, isPseudo = 1 in
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def PS_pselect : ALU64_rr<(outs DoubleRegs:$Rd),
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(ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
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".error \"should not emit\" ", []>;
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let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
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isPredicable = 1,
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isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
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opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
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class T_JMP<string ExtStr>
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: JInst_CJUMP_UCJUMP<(outs), (ins b30_2Imm:$dst),
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"jump " # ExtStr # "$dst",
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[], "", J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT> {
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bits<24> dst;
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let IClass = 0b0101;
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let Inst{27-25} = 0b100;
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let Inst{24-16} = dst{23-15};
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let Inst{13-1} = dst{14-2};
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}
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// Restore registers and dealloc return function call.
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let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
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Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP<"">;
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let isExtended = 1, opExtendable = 0 in
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def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP<"">;
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let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
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def RESTORE_DEALLOC_RET_JMP_V4_PIC : T_JMP<"">;
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let isExtended = 1, opExtendable = 0 in
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def RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC : T_JMP<"">;
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}
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}
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// Restore registers and dealloc frame before a tail call.
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let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
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def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<"">, PredRel;
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let isExtended = 1, opExtendable = 0 in
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def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT : T_Call<"">, PredRel;
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let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
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def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC : T_Call<"">, PredRel;
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let isExtended = 1, opExtendable = 0 in
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def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC : T_Call<"">, PredRel;
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}
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}
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// Save registers function call.
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let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
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def SAVE_REGISTERS_CALL_V4 : T_Call<"">, PredRel;
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let isExtended = 1, opExtendable = 0 in
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def SAVE_REGISTERS_CALL_V4_EXT : T_Call<"">, PredRel;
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let Defs = [P0] in
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def SAVE_REGISTERS_CALL_V4STK : T_Call<"">, PredRel;
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|
|
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let Defs = [P0], isExtended = 1, opExtendable = 0 in
|
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def SAVE_REGISTERS_CALL_V4STK_EXT : T_Call<"">, PredRel;
|
|
|
|
let Defs = [R14, R15, R28] in
|
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def SAVE_REGISTERS_CALL_V4_PIC : T_Call<"">, PredRel;
|
|
|
|
let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in
|
|
def SAVE_REGISTERS_CALL_V4_EXT_PIC : T_Call<"">, PredRel;
|
|
|
|
let Defs = [R14, R15, R28, P0] in
|
|
def SAVE_REGISTERS_CALL_V4STK_PIC : T_Call<"">, PredRel;
|
|
|
|
let Defs = [R14, R15, R28, P0], isExtended = 1, opExtendable = 0 in
|
|
def SAVE_REGISTERS_CALL_V4STK_EXT_PIC : T_Call<"">, PredRel;
|
|
}
|
|
|
|
// Vector load/store pseudos
|
|
|
|
let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in
|
|
class STrivv_template<RegisterClass RC>
|
|
: V6_STInst<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src), "", []>;
|
|
|
|
def PS_vstorerw_ai: STrivv_template<VecDblRegs>,
|
|
Requires<[HasV60T,UseHVXSgl]>;
|
|
def PS_vstorerwu_ai: STrivv_template<VecDblRegs>,
|
|
Requires<[HasV60T,UseHVXSgl]>;
|
|
def PS_vstorerw_ai_128B: STrivv_template<VecDblRegs128B>,
|
|
Requires<[HasV60T,UseHVXDbl]>;
|
|
def PS_vstorerwu_ai_128B: STrivv_template<VecDblRegs128B>,
|
|
Requires<[HasV60T,UseHVXDbl]>;
|
|
|
|
|
|
let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in
|
|
class LDrivv_template<RegisterClass RC>
|
|
: V6_LDInst<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off), "", []>;
|
|
|
|
def PS_vloadrw_ai: LDrivv_template<VecDblRegs>,
|
|
Requires<[HasV60T,UseHVXSgl]>;
|
|
def PS_vloadrwu_ai: LDrivv_template<VecDblRegs>,
|
|
Requires<[HasV60T,UseHVXSgl]>;
|
|
def PS_vloadrw_ai_128B: LDrivv_template<VecDblRegs128B>,
|
|
Requires<[HasV60T,UseHVXDbl]>;
|
|
def PS_vloadrwu_ai_128B: LDrivv_template<VecDblRegs128B>,
|
|
Requires<[HasV60T,UseHVXDbl]>;
|
|
|
|
// Store vector predicate pseudo.
|
|
let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
|
|
isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in {
|
|
def PS_vstorerq_ai : STInst<(outs),
|
|
(ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs:$src1),
|
|
".error \"should not emit\" ", []>,
|
|
Requires<[HasV60T,UseHVXSgl]>;
|
|
|
|
def PS_vstorerq_ai_128B : STInst<(outs),
|
|
(ins IntRegs:$base, s32_0Imm:$offset, VectorRegs:$src1),
|
|
".error \"should not emit\" ", []>,
|
|
Requires<[HasV60T,UseHVXSgl]>;
|
|
|
|
def PS_vloadrq_ai : STInst<(outs),
|
|
(ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs128B:$src1),
|
|
".error \"should not emit\" ", []>,
|
|
Requires<[HasV60T,UseHVXDbl]>;
|
|
|
|
def PS_vloadrq_ai_128B : STInst<(outs),
|
|
(ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs128B:$src1),
|
|
".error \"should not emit\" ", []>,
|
|
Requires<[HasV60T,UseHVXDbl]>;
|
|
}
|
|
|
|
class VSELInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
|
|
string cstr = "", InstrItinClass itin = CVI_VA_DV,
|
|
IType type = TypeCVI_VA_DV>
|
|
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
|
|
|
|
let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
|
|
def PS_vselect: VSELInst<(outs VectorRegs:$dst),
|
|
(ins PredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), "", []>,
|
|
Requires<[HasV60T,UseHVXSgl]>;
|
|
def PS_vselect_128B: VSELInst<(outs VectorRegs128B:$dst),
|
|
(ins PredRegs:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3),
|
|
"", []>, Requires<[HasV60T,UseHVXDbl]>;
|
|
def PS_wselect: VSELInst<(outs VecDblRegs:$dst),
|
|
(ins PredRegs:$src1, VecDblRegs:$src2, VecDblRegs:$src3), "", []>,
|
|
Requires<[HasV60T,UseHVXSgl]>;
|
|
def PS_wselect_128B: VSELInst<(outs VecDblRegs128B:$dst),
|
|
(ins PredRegs:$src1, VecDblRegs128B:$src2, VecDblRegs128B:$src3),
|
|
"", []>, Requires<[HasV60T,UseHVXDbl]>;
|
|
}
|
|
|
|
// Store predicate.
|
|
let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
|
|
isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
|
|
def STriw_pred : STInst<(outs),
|
|
(ins IntRegs:$addr, s32_0Imm:$off, PredRegs:$src1),
|
|
".error \"should not emit\"", []>;
|
|
// Store modifier.
|
|
let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
|
|
isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
|
|
def STriw_mod : STInst<(outs),
|
|
(ins IntRegs:$addr, s32_0Imm:$off, ModRegs:$src1),
|
|
".error \"should not emit\"", []>;
|
|
|
|
let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
|
|
isAsmParserOnly = 1 in
|
|
def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u64_0Imm:$src1),
|
|
"$dst = #$src1">;
|
|
|
|
// Hexagon doesn't have a vector multiply with C semantics.
|
|
// Instead, generate a pseudo instruction that gets expaneded into two
|
|
// scalar MPYI instructions.
|
|
// This is expanded by ExpandPostRAPseudos.
|
|
let isPseudo = 1 in
|
|
def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd),
|
|
(ins DoubleRegs:$Rs, DoubleRegs:$Rt), "", []>;
|
|
|
|
let isPseudo = 1 in
|
|
def PS_vmulw_acc : PseudoM<(outs DoubleRegs:$Rd),
|
|
(ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt), "", [],
|
|
"$Rd = $Rx">;
|
|
|
|
def DuplexIClass0: InstDuplex < 0 >;
|
|
def DuplexIClass1: InstDuplex < 1 >;
|
|
def DuplexIClass2: InstDuplex < 2 >;
|
|
let isExtendable = 1 in {
|
|
def DuplexIClass3: InstDuplex < 3 >;
|
|
def DuplexIClass4: InstDuplex < 4 >;
|
|
def DuplexIClass5: InstDuplex < 5 >;
|
|
def DuplexIClass6: InstDuplex < 6 >;
|
|
def DuplexIClass7: InstDuplex < 7 >;
|
|
}
|
|
def DuplexIClass8: InstDuplex < 8 >;
|
|
def DuplexIClass9: InstDuplex < 9 >;
|
|
def DuplexIClassA: InstDuplex < 0xA >;
|
|
def DuplexIClassB: InstDuplex < 0xB >;
|
|
def DuplexIClassC: InstDuplex < 0xC >;
|
|
def DuplexIClassD: InstDuplex < 0xD >;
|
|
def DuplexIClassE: InstDuplex < 0xE >;
|
|
def DuplexIClassF: InstDuplex < 0xF >;
|