forked from OSchip/llvm-project
31 lines
760 B
LLVM
31 lines
760 B
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; Check that we generate new value jump, both registers, with one
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; of the registers as new.
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@Reg = common global i8 0, align 1
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define i32 @main() nounwind {
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entry:
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; CHECK: if (cmp.gt(r{{[0-9]+}}.new, r{{[0-9]+}})) jump:{{[t|nt]}} .LBB{{[0-9]+}}_{{[0-9]+}}
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%Reg2 = alloca i8, align 1
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%0 = load i8* %Reg2, align 1
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%conv0 = zext i8 %0 to i32
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%1 = load i8* @Reg, align 1
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%conv1 = zext i8 %1 to i32
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%tobool = icmp sle i32 %conv0, %conv1
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br i1 %tobool, label %if.then, label %if.else
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if.then:
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call void @bar(i32 1, i32 2)
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br label %if.end
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if.else:
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call void @baz(i32 10, i32 20)
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br label %if.end
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if.end:
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ret i32 0
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}
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declare void @bar(i32, i32)
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declare void @baz(i32, i32)
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