David Sherwood 23ad660b5d [SVE][CodeGen] At -O0 fallback to DAG ISel when translating alloca with scalable types ... When building code at -O0 We weren't falling back to DAG ISel correctly when encountering alloca instructions with scalable vector types. This is because the alloca has no operands that are scalable. I've fixed this by adding a check in AArch64ISelLowering::fallBackToDAGISel for alloca instructions with scalable types. Differential Revision: https://reviews.llvm.org/D84746		2020-07-30 08:40:53 +01:00
..
arm64-callingconv-ios.ll	[AArch64] Provide Darwin variants of most calling conventions	2020-05-20 16:03:48 -07:00
arm64-callingconv.ll	[AArch64][GlobalISel] Fix sub-64b stack parameter passing on Darwin.	2020-04-24 13:56:43 -07:00
arm64-fallback.ll	[SVE][CodeGen] At -O0 fallback to DAG ISel when translating alloca with scalable types	2020-07-30 08:40:53 +01:00
arm64-irtranslator-fmuladd.ll	…
arm64-irtranslator-gep.ll	[GlobalISel][IRTranslator] Follow convention and put constant offset of getelementptr arithmetic on RHS.	2020-01-29 11:37:19 -08:00
arm64-irtranslator-stackprotect.ll	[GlobalISel] Set stack protector index when translating Intrinsic::stackprotector	2018-12-10 15:15:05 +00:00
arm64-irtranslator-switch.ll	Revert "[GISel]: Fix incorrect IRTranslation while translating null pointer types"	2020-03-30 19:30:42 -04:00
arm64-irtranslator.ll	[GlobalISel] Add G_INTRINSIC_LRINT and translate from llvm.lrint	2020-07-29 11:51:04 -07:00
arm64-regbankselect.mir	GlobalISel: Verify G_BITCAST changes the type	2020-07-08 17:16:27 -04:00
artifact-combine-unmerge.mir	[GlobalISel] LegalizationArtifactCombiner: Fix a bug in tryCombineMerges	2020-02-14 10:45:58 -08:00
call-lowering-const-bitcast-func.ll	[GlobalISel][CallLowering] Look through bitcasts from constant function pointers.	2020-02-07 15:32:54 -08:00
call-lowering-i128-on-stack.ll	[AArch64][GlobalISel] Fall back on attempts to allocate split types on the stack.	2019-09-11 23:53:23 +00:00
call-lowering-i256-crash.ll	[GlobalISel] Fix a crash when handling an invalid MVT during call lowering.	2019-04-12 22:05:46 +00:00
call-translator-cse.ll	[AArch64][GlobalISel] CallLowering: Don't generate new copies each time we need	2020-04-09 17:08:56 -07:00
call-translator-ios.ll	[AArch64][GlobalISel] CallLowering: Don't generate new copies each time we need	2020-04-09 17:08:56 -07:00
call-translator-musttail.ll	Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""	2020-02-13 10:16:06 -08:00
call-translator-tail-call-weak.ll	[AArch64] Provide Darwin variants of most calling conventions	2020-05-20 16:03:48 -07:00
call-translator-tail-call.ll	[AArch64] Provide Darwin variants of most calling conventions	2020-05-20 16:03:48 -07:00
call-translator-variadic-musttail.ll	[AArch64][GlobalISel] Select G_ADD_LOW into a MOVaddr pseudo.	2020-06-09 16:47:58 -07:00
call-translator.ll	AArch64/GlobalISel: Fix assert on call returning 0 sized type	2020-06-03 19:56:07 -04:00
combine-anyext-crash.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
combine-copy.mir	[GlobalISel] CombinerHelper: Fix a bug in matchCombineCopy	2019-12-02 12:05:09 -08:00
combine-ext-debugloc.mir	[AArch64][GlobalISel] Split G_GLOBAL_VALUE into ADRP + G_ADD_LOW and optimize.	2020-06-01 16:00:56 -07:00
combine-fconstant.mir	[AArch64PreLegalizerCombiner] Fix debug invariance issue in matchFConstantToConstant [13/14]	2020-04-22 17:03:41 -07:00
combine-mul-to-shl.mir	[GlobalISel] Add new combine to convert scalar G_MUL to G_SHL.	2020-01-29 13:39:00 -08:00
combine-sext-debugloc.mir	[GlobalISel] Assign the correct location when combining G_SEXT.	2020-05-12 15:32:18 -07:00
combine-sext-trunc-sextload.mir	[AArch64][GlobalISel] Add post-legalize combine for sext(trunc(sextload)) -> trunc/copy	2020-07-23 12:06:35 -07:00
combiner-load-store-indexing.ll	[GIsel][CombinerHelper] Fix for missed ElideBrByInvertingCond/CombineIndexedLoadStore combines [4/14]	2020-04-22 17:03:40 -07:00
const-0.ll	AArch64: bail instead of asserting on unexpected type in G_CONSTANT 0.	2019-08-06 13:34:08 +00:00
constant-dbg-loc.ll	[GlobalISel] Remove debug locations when emitting constants.	2020-04-27 11:27:08 -07:00
constant-mir-debugify.mir	[MachineDebugify] Insert synthetic DBG_VALUE instructions	2020-04-22 17:03:39 -07:00
contract-store.mir	[GlobalISel][AArch64] Fix contract cross-bank copies with SIMD instructions	2020-02-05 10:38:35 -08:00
darwin-tls-call-clobber.ll	[AArch64][GlobalISel] Fix TLS accesses clobbering registers incorrectly.	2020-07-21 16:01:17 -07:00
debug-cpp.ll	Revert "[DebugInfo] Remove some users of DBG_VALUEs IsIndirect field"	2020-02-06 14:41:40 +00:00
debug-insts.ll	[GlobalISel][test] Add REQUIRES: asserts after D76934	2020-06-11 13:50:56 -07:00
dynamic-alloca-lifetime.ll	[GlobalISel] Add ISel support for @llvm.lifetime.start and @llvm.lifetime.end	2019-01-28 19:22:29 +00:00
dynamic-alloca.ll	[Alignment][NFC] Convert MachineIRBuilder::buildDynStackAlloc to Align	2020-04-03 09:05:19 +00:00
fallback-nofastisel.ll	…
fconstant-dbg-loc.ll	[GlobalISel] Remove debug locations when emitting G_FCONSTANT.	2020-05-11 16:25:03 -07:00
fold-fp-select.mir	[AArch64][GlobalISel] Don't bail out of the select(cmp(a, b)) -> csel optimization with multiple users.	2020-01-28 10:09:03 -08:00
fold-select.mir	[AArch64][GlobalISel] Select immediate forms of compares by wiggling constants	2020-04-28 11:35:01 -07:00
fp16-copy-gpr.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
fp128-legalize-crash-pr35690.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
freeze.ll	[AArch64][GlobalISel] Add legalizer & selector support for G_FREEZE.	2020-05-18 16:25:33 -07:00
gisel-abort.ll	…
gisel-commandline-option-fastisel.ll	Rename ExpandISelPseudo->FinalizeISel, delay register reservation	2019-06-19 00:25:39 +00:00
gisel-commandline-option.ll	[AArch64][GlobalISel] Add a post-legalizer combiner with a very simple combine.	2020-05-21 18:47:32 -07:00
gisel-fail-intermediate-legalizer.ll	GlobalISel: Implement widenScalar for G_SITOFP/G_UITOFP sources	2019-10-01 01:06:48 +00:00
inline-asm.ll	…
inline-memcpy.mir	Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351	2019-12-24 15:57:33 -08:00
inline-memmove.mir	Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351	2019-12-24 15:57:33 -08:00
inline-memset.mir	[GlobalISel] Don't emit multiply by magic constant for zero memset values.	2020-06-15 14:42:14 -07:00
inline-small-memcpy.mir	[globalisel] Rename G_GEP to G_PTR_ADD	2019-11-05 10:31:17 -08:00
integration-shuffle-vector.ll	[AArch64] Provide Darwin variants of most calling conventions	2020-05-20 16:03:48 -07:00
irtranslator-atomic-metadata.ll	GlobalISel: Apply target MMO flags to atomics	2020-01-16 13:49:43 -05:00
irtranslator-bitcast.ll	…
irtranslator-block-order.ll	…
irtranslator-convert-fp16-intrinsics.ll	GlobalISel: Translate llvm.convert.{to|from}.fp16 intrinsics	2020-07-28 11:46:05 -04:00
irtranslator-dilocation.ll	…
irtranslator-duplicate-types-param.ll	…
irtranslator-exceptions.ll	[AArch64] Provide Darwin variants of most calling conventions	2020-05-20 16:03:48 -07:00
irtranslator-extends.ll	[globalisel] Add G_SEXT_INREG	2019-08-09 21:11:20 +00:00
irtranslator-fixed-point-intrinsics.ll	GlobalISel: Define mulfix/divfix opcodes	2020-07-24 20:02:20 -04:00
irtranslator-fp-min-max-intrinsics.ll	GlobalISel: Define the full family of FP min/max instructions	2019-07-10 16:31:15 +00:00
irtranslator-indirect-br-repeated-block.ll	[GlobalISel] Don't add duplicate successors to MBBs when translating indirectbr	2020-05-08 13:40:02 -07:00
irtranslator-inline-asm.ll	[GlobalISel][InlineAsm] Add register class ID to the flags of register input operands	2020-07-23 13:35:01 +02:00
irtranslator-load-metadata.ll	GlobalISel: Preserve load/store metadata in IRTranslator	2020-01-16 13:49:43 -05:00
irtranslator-max-address-space.ll	GlobalISel: Fix address space limit in LLT	2019-01-26 01:42:13 +00:00
irtranslator-memfunc-undef.ll	[GlobalISel] Translate memset/memmove/memcpy from undef ptrs into nops	2019-06-10 21:53:56 +00:00
irtranslator-no-op-intrinsics.ll	GlobalISel: Handle assorted no-op intrinsics	2020-07-29 21:26:20 -04:00
irtranslator-split-vector-arg.ll	[GISel][CallLowering] Enable vector support in argument lowering	2019-10-11 20:22:57 +00:00
irtranslator-stackprotect-check.ll	GlobalISel: Preserve load/store metadata in IRTranslator	2020-01-16 13:49:43 -05:00
irtranslator-store-metadata.ll	GlobalISel: Preserve load/store metadata in IRTranslator	2020-01-16 13:49:43 -05:00
irtranslator-tbaa.ll	Revert "[GISel]: Fix incorrect IRTranslation while translating null pointer types"	2020-03-30 19:30:42 -04:00
irtranslator-volatile-load-pr36018.ll	[AArch64][GlobalISel] Re-enable selection of volatile loads.	2018-12-05 00:03:09 +00:00
irtranslator-weird-alloca-size.ll	[IRTranslator] Use the alloc size instead of the store size when translating allocas	2019-05-03 01:23:56 +00:00
legalize-add.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-and.mir	…
legalize-atomicrmw.mir	[AArch64][GlobalISel] Make s8 and s16 G_CONSTANTs legal.	2019-06-21 16:43:50 +00:00
legalize-blockaddress.mir	[MachineVerifier][GlobalISel] Check that branches have a MBB operand or are declared indirect. Add missing properties to G_BRJT, G_BRINDIRECT	2020-06-15 11:17:09 +02:00
legalize-bswap.mir	[AArch64][GlobalISel] Tweak legalization rule for G_BSWAP to handle widening s16.	2019-09-25 04:52:42 +00:00
legalize-build-vector.mir	[AArch64][GlobalISel] Make <2 x p0> = G_BUILD_VECTOR legal.	2019-04-10 23:06:14 +00:00
legalize-ceil.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-cmp.mir	GlobalISel: Allow CSE of G_IMPLICIT_DEF	2020-02-05 17:47:21 -05:00
legalize-cmpxchg-with-success.mir	…
legalize-cmpxchg.mir	[AArch64][GlobalISel] Make s8 and s16 G_CONSTANTs legal.	2019-06-21 16:43:50 +00:00
legalize-combines.mir	GlobalISel: Combine g_extract with g_merge_values	2019-02-04 23:41:59 +00:00
legalize-concat-vectors.mir	[AArch64][GlobalISel] Add some support for G_CONCAT_VECTORS.	2019-03-14 22:48:15 +00:00
legalize-constant.mir	[AArch64][GlobalISel] Split G_GLOBAL_VALUE into ADRP + G_ADD_LOW and optimize.	2020-06-01 16:00:56 -07:00
legalize-cos.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-div.mir	[AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support.	2020-06-19 13:20:41 -07:00
legalize-dyn-alloca.mir	[update_mir_test_checks] Handle MI flags properly	2019-10-14 22:01:58 +00:00
legalize-exceptions.ll	…
legalize-exp.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-ext-cse.mir	[GISel]: Change how CSE is enabled by default for each pass	2019-01-24 23:11:25 +00:00
legalize-ext-csedebug-output.mir	[GlobalISel] Regex the opcodes in unit test to fix non-deterministic ordering	2019-02-10 19:53:43 +00:00
legalize-ext.mir	[AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support.	2020-06-19 13:20:41 -07:00
legalize-extload.mir	[AArch64][GlobalISel] Make extloads to i64 legal.	2019-06-04 21:51:34 +00:00
legalize-extract-vector-elt.mir	[GlobalISel] Restrict G_MERGE_VALUES capability and replace with new opcodes.	2018-12-10 18:44:58 +00:00
legalize-extracts.mir	[AArch64][GlobalISel] Add support for s128 loads, stores, extracts, truncs.	2019-07-23 22:05:13 +00:00
legalize-fcmp.mir	…
legalize-fexp2.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-fma.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-fp-arith.mir	[AArch64][GlobalISel] Add some missing vector support for FP arithmetic ops.	2019-01-28 02:28:22 +00:00
legalize-fptoi.mir	[AArch64][GlobalISel] Add some vector support for fp <-> int conversions.	2019-01-28 02:27:59 +00:00
legalize-freeze.mir	[AArch64][GlobalISel] Add legalizer & selector support for G_FREEZE.	2020-05-18 16:25:33 -07:00
legalize-frint.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-global.mir	[AArch64][GlobalISel] Split G_GLOBAL_VALUE into ADRP + G_ADD_LOW and optimize.	2020-06-01 16:00:56 -07:00
legalize-ignore-non-generic.mir	…
legalize-inserts.mir	[AArch64][GlobalISel] Add support for s128 loads, stores, extracts, truncs.	2019-07-23 22:05:13 +00:00
legalize-intrinsic-round.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-intrinsic-trunc.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-inttoptr-xfail-1.mir	Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""	2020-02-13 10:16:06 -08:00
legalize-inttoptr-xfail-2.mir	Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""	2020-02-13 10:16:06 -08:00
legalize-itofp.mir	[AArch64][GlobalISel] Promote G_UITOFP vector operands to same elt size as result.	2020-07-24 17:00:50 -07:00
legalize-load-store-fewerElts.mir	[AArch64][GlobalISel] Flesh out vector load/store support for more types.	2019-04-11 20:40:01 +00:00
legalize-load-store-vector-of-ptr-debugloc.mir	[AArch64][GlobalISel] Add more specific debug info tests for 613f12dd8e.	2020-07-09 17:13:16 -07:00
legalize-load-store-vector-of-ptr.mir	[AArch64][GlobalISel] Set the current debug loc when missing in some cases.	2020-04-23 01:34:57 -07:00
legalize-load-store.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-load-trunc.mir	[GlobalISel] combine trunc(trunc) pattern	2020-04-08 11:58:28 +02:00
legalize-log.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-log2.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-log10.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-memcpy-et-al.mir	[AArch64] Fix GlobalISel tests on non-darwin platforms	2020-05-20 16:26:58 -07:00
legalize-memcpy-with-debug-info.mir	[AArch64] Fix GlobalISel tests on non-darwin platforms	2020-05-20 16:26:58 -07:00
legalize-memlib-debug-loc.mir	[AArch64][GlobalISel] Add more specific debug info tests for 613f12dd8e.	2020-07-09 17:13:16 -07:00
legalize-merge-values.mir	[Legalizer] Making artifact combining order-independent	2019-12-13 15:45:18 -08:00
legalize-mul.mir	…
legalize-nearbyint.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-non-pow2-load-store.mir	[GlobalISel] Use G_ZEXTLOAD instead of an anyextending load for non-pow-2 legalization.	2020-02-06 14:36:36 -08:00
legalize-or.mir	…
legalize-phi-insertpt-decrement.mir	[MachineDebugify] Insert synthetic DBG_VALUE instructions	2020-04-22 17:03:39 -07:00
legalize-phi.mir	GlobalISel: Allow CSE of G_IMPLICIT_DEF	2020-02-05 17:47:21 -05:00
legalize-pow.mir	[AArch64] Fix GlobalISel tests on non-darwin platforms	2020-05-20 16:26:58 -07:00
legalize-property.mir	…
legalize-ptr-add.mir	[AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support.	2020-06-19 13:20:41 -07:00
legalize-rem.mir	[AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support.	2020-06-19 13:20:41 -07:00
legalize-s128-div.mir	[AArch64] Provide Darwin variants of most calling conventions	2020-05-20 16:03:48 -07:00
legalize-select.mir	GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC	2020-05-09 16:14:32 -04:00
legalize-sext-128.ll	[GlobalISel][NFC] Regression test cases for aarch64 legalizer (s128 sext+icmp).	2019-09-01 00:45:28 +00:00
legalize-sext-128.mir	[GlobalISel][NFC] Regression test cases for aarch64 legalizer (s128 sext+icmp).	2019-09-01 00:45:28 +00:00
legalize-sext-copy.mir	…
legalize-sext-zext-128.mir	[GlobalISel] Enable artifact combiner to combine starting from a G_MERGE_VALUES.	2020-04-15 10:34:13 -07:00
legalize-sext.mir	[AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support.	2020-06-19 13:20:41 -07:00
legalize-sextload.mir	…
legalize-shift-imm-promote-dloc.mir	[AArch64][GlobalISel] Add more specific debug info tests for 613f12dd8e.	2020-07-09 17:13:16 -07:00
legalize-shift.mir	[AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support.	2020-06-19 13:20:41 -07:00
legalize-shuffle-vector.mir	[AArch64][GlobalISel] Make <8 x s16> and <16 x s8> legal types for G_SHUFFLE_VECTOR and G_IMPLICIT_DEF.	2020-07-26 00:48:09 -07:00
legalize-simple.mir	GlobalISel: Verify G_BITCAST changes the type	2020-07-08 17:16:27 -04:00
legalize-sin.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-sqrt.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-sub.mir	…
legalize-undef.mir	[AArch64][GlobalISel] Make <8 x s16> and <16 x s8> legal types for G_SHUFFLE_VECTOR and G_IMPLICIT_DEF.	2020-07-26 00:48:09 -07:00
legalize-unmerge-values.mir	[GlobalISel] Combine scalar unmerge(trunc)	2020-06-02 08:56:18 +02:00
legalize-vaarg.mir	[AArch64][GlobalISel] Add more specific debug info tests for 613f12dd8e.	2020-07-09 17:13:16 -07:00
legalize-vector-icmp.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
legalize-vector-shift.mir	[AArch64][GlobalISel] Make <4 x s32> G_ASHR and G_LSHR legal.	2019-09-21 09:21:10 +00:00
legalize-xor.mir	…
legalize-zextload.mir	…
legalizer-combiner-zext-trunc-crash.mir	[Legalizer] Making artifact combining order-independent	2019-12-13 15:45:18 -08:00
legalizer-combiner.mir	[GlobalISel] Enable artifact combiner to combine starting from a G_MERGE_VALUES.	2020-04-15 10:34:13 -07:00
legalizer-info-validation.mir	GlobalISel: Handle llvm.roundeven	2020-07-29 20:01:12 -04:00
lit.local.cfg	…
load-addressing-modes.mir	[AArch64][GlobalISel] Don't reconvert to p0 in convertPtrAddToAdd().	2020-02-03 11:50:22 -08:00
load-wro-addressing-modes.mir	[AArch64][GlobalISel] Avoid copies to target register bank for subregister copies	2020-03-05 11:13:02 -08:00
localizer-arm64-tti.ll	[AArch64][GlobalISel] Don't localize TLS G_GLOBAL_VALUEs on Darwin.	2020-03-24 13:35:50 -07:00
localizer-in-O0-pipeline.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
localizer.mir	[AArch64][GlobalISel] Split G_GLOBAL_VALUE into ADRP + G_ADD_LOW and optimize.	2020-06-01 16:00:56 -07:00
machine-cse-mid-pipeline.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
memcpy_chk_no_tail.ll	Add an operand to memory intrinsics to denote the "tail" marker.	2019-09-28 05:33:21 +00:00
no-neon-no-fp.ll	Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""	2020-02-13 10:16:06 -08:00
no-regclass.mir	…
non-pow-2-extload-combine.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
observer-change-crash.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
opt-and-tbnz-tbz.mir	[AArch64][GlobalISel] Fix TBNZ/TBZ opcode selection	2020-01-29 13:11:18 -08:00
opt-fold-and-tbz-tbnz.mir	[AArch64][GlobalISel] Avoid copies to target register bank for subregister copies	2020-03-05 11:13:02 -08:00
opt-fold-compare.mir	[AArch64][GlobalISel] When generating SUBS for compares, don't write to wzr/xzr.	2020-05-23 22:59:49 -07:00
opt-fold-ext-tbz-tbnz.mir	[AArch64][GlobalISel] Avoid copies to target register bank for subregister copies	2020-03-05 11:13:02 -08:00
opt-fold-shift-tbz-tbnz.mir	[AArch64][GlobalISel] Avoid copies to target register bank for subregister copies	2020-03-05 11:13:02 -08:00
opt-fold-trunc-tbz-tbnz.mir	[AArch64][GlobalISel] Walk through G_TRUNC in getTestBitReg	2020-01-31 11:09:55 -08:00
opt-fold-xor-tbz-tbnz.mir	[AArch64][GlobalISel] Fold G_XOR into TB(N)Z bit calculation	2020-02-03 15:22:24 -08:00
opt-shifted-reg-compare.mir	[AArch64][GlobalISel] Fold shifts into G_ICMP	2020-05-05 18:35:39 -07:00
phi-mir-debugify.mir	[MachineDebugify] Insert synthetic DBG_VALUE instructions	2020-04-22 17:03:39 -07:00
postlegalizer-combiner-ext.mir	[AArch64][GlobalISel] Add G_EXT and select ext using it	2020-06-15 12:20:59 -07:00
postlegalizer-combiner-rev.mir	[AArch64][GlobalISel] Add selection support for rev16, rev32, and rev64	2020-06-03 15:30:30 -07:00
postlegalizer-combiner-shuffle-splat.mir	[AArch64][GlobalISel] Port buildvector -> dup pattern from AArch64ISelLowering	2020-06-25 14:19:06 -07:00
postlegalizer-combiner-store-undef.mir	[AArch64][GlobalISel] Add a post-legalizer combiner with a very simple combine.	2020-05-21 18:47:32 -07:00
postlegalizer-combiner-trn.mir	[AArch64][GlobalISel] Select trn1 and trn2	2020-06-09 10:55:19 -07:00
postlegalizer-combiner-uzp.mir	[AArch64][GlobalISel] Select uzp1 and uzp2	2020-06-03 15:09:41 -07:00
postlegalizer-combiner-zip.mir	NFC: Remove disabled rule from postlegalizer-combiner-zip.mir test	2020-06-15 13:15:02 -07:00
postlegalizercombiner-extending-loads.mir	[AArch64][GlobalISel] Enable extending loads combines post-legalization.	2020-05-28 22:48:20 -07:00
prelegalizercombiner-binop-same-val.mir	[GlobalISel] Implement identity transforms for x op x -> x	2020-03-30 18:22:37 -07:00
prelegalizercombiner-br.mir	[GIsel][CombinerHelper] Fix for missed ElideBrByInvertingCond/CombineIndexedLoadStore combines [4/14]	2020-04-22 17:03:40 -07:00
prelegalizercombiner-concat-vectors.mir	[GISel][CombinerHelper] Add concat_vectors(build_vector, build_vector) => build_vector	2019-10-17 00:34:32 +00:00
prelegalizercombiner-copy-prop-disabled.mir	[gicombiner] Allow disable-rule option to disable all-except-...	2020-06-16 16:57:16 -07:00
prelegalizercombiner-extending-loads-cornercases.mir	Add -debugify-and-strip-all to add debug info before a pass and remove it after	2020-04-10 16:36:07 -07:00
prelegalizercombiner-extending-loads-s1.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
prelegalizercombiner-extending-loads.mir	[globalisel] Fix iterator invalidation in the extload combines	2019-06-17 20:56:31 +00:00
prelegalizercombiner-not-really-equiv-insts.mir	[GlobalISel] Don't combine instructions which are fed by memory instructions.	2020-05-27 12:48:58 -07:00
prelegalizercombiner-ptradd-chain.mir	[AArch64][GlobalISel] Fold a chain of two G_PTR_ADDs of constant offsets.	2020-01-07 14:12:42 -08:00
prelegalizercombiner-select.mir	[GlobalISel] Fix equality for copies from physregs in matchEqualDefs	2020-03-27 17:52:21 -07:00
prelegalizercombiner-shuffle-vector.mir	[GlobalISel] Change representation of shuffle masks in MachineOperand.	2020-01-13 16:55:41 -08:00
prelegalizercombiner-simplify-add.mir	[GlobalISel] Simplify G_ADD when it has (0-X) on the LHS or RHS	2020-06-15 09:43:24 -07:00
prelegalizercombiner-trivial-arith.mir	[GlobalISel] Look through extends etc in CombinerHelper::matchConstantOp	2020-06-15 16:34:25 -07:00
prelegalizercombiner-undef.mir	[GlobalISel] Port some basic shufflevector undef combines from the DAGCombiner	2020-03-19 16:46:06 -07:00
preselect-process-phis.mir	[AArch64][GlobalISel] Fixup <32b heterogeneous regbanks of G_PHIs just before selection.	2020-02-26 14:10:32 -08:00
reg-bank-128bit.mir	…
regbank-ceil.ll	[GlobalISel][AArch64] Add G_FCEIL to isPreISelGenericFloatingPointOpcode	2018-12-20 21:14:15 +00:00
regbank-dup.mir	[AArch64][GlobalISel] Move dup optimization into post-legalizer combiner	2020-06-05 17:46:28 -07:00
regbank-extract-vector-elt.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
regbank-extract.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
regbank-fma.mir	[update_mir_test_checks] Handle MI flags properly	2019-10-14 22:01:58 +00:00
regbank-fp-use-def.mir	[GlobalISel][AArch64] Save a copy on G_SELECT by fixing condition to GPR	2019-07-23 21:39:50 +00:00
regbank-inlineasm.mir	[GlobalISel][InlineAsm] Add support for basic output operand constraints	2020-05-06 10:06:13 +02:00
regbank-insert-vector-elt.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
regbank-intrinsic-round.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
regbank-intrinsic-trunc.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
regbank-nearbyint.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
regbank-select.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
regbank-shift-imm-64.mir	[AArch64][GlobalISel] Overhaul legalization & isel or shifts to select immediate forms.	2019-07-03 01:49:06 +00:00
regbank-trunc-s128.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
regbankselect-build-vector.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
regbankselect-dbg-value.mir	…
regbankselect-default.mir	GlobalISel: Enforce operand types for constants	2019-02-04 23:29:31 +00:00
regbankselect-reg_sequence.mir	GlobalISel: Fix RegBankSelect for REG_SEQUENCE	2019-03-21 20:45:36 +00:00
regbankselect-unmerge-vec.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
ret-1x-vec.ll	[GlobalISel] Handle <1 x T> vector return types properly.	2019-05-06 19:41:01 +00:00
ret-vec-promote.ll	[GlobalISel][AArch64] Allow CallLowering to handle types which are normally	2019-04-09 21:22:33 +00:00
retry-artifact-combine.mir	[Legalizer] Making artifact combining order-independent	2019-12-13 15:45:18 -08:00
select-arith-extended-reg.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-arith-immed-compare.mir	[AArch64][GlobalISel] Do not modify predicate when optimizing G_ICMP	2020-05-26 17:51:08 -07:00
select-arith-shifted-reg.mir	[AArch64][GlobalISel] Select patterns which use shifted register operands	2019-08-20 22:18:06 +00:00
select-atomic-load-store.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-atomicrmw.mir	[GlobalISel] Import patterns containing SUBREG_TO_REG	2019-08-28 20:12:31 +00:00
select-binop.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-bitcast-bigendian.mir	…
select-bitcast.mir	GlobalISel: Verify G_BITCAST changes the type	2020-07-08 17:16:27 -04:00
select-blockaddress.mir	[MachineVerifier][GlobalISel] Check that branches have a MBB operand or are declared indirect. Add missing properties to G_BRJT, G_BRINDIRECT	2020-06-15 11:17:09 +02:00
select-br.mir	…
select-bswap.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-build-vector.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-cbz.mir	[AArch64][GlobalISel] Select immediate forms of compares by wiggling constants	2020-04-28 11:35:01 -07:00
select-ceil.mir	[GlobalISel][AArch64] Add isel support for FP16 vector @llvm.ceil	2019-01-24 22:00:41 +00:00
select-cmp.mir	[AArch64][GlobalISel] When generating SUBS for compares, don't write to wzr/xzr.	2020-05-23 22:59:49 -07:00
select-cmpxchg.mir	[GlobalISel] Import patterns containing SUBREG_TO_REG	2019-08-28 20:12:31 +00:00
select-concat-vectors.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-const-vector.mir	[AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads.	2020-06-23 19:23:47 -07:00
select-constant.mir	Revert "[GISel]: Fix incorrect IRTranslation while translating null pointer types"	2020-03-30 19:30:42 -04:00
select-ctlz.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-dbg-value.mir	…
select-dup.mir	[AArch64][GlobalISel] Allow G_DUP for elements smaller than 32 B.	2020-06-12 09:40:34 -07:00
select-ext.mir	[AArch64][GlobalISel] Add G_EXT and select ext using it	2020-06-15 12:20:59 -07:00
select-extload.mir	…
select-extract-vector-elt.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-extract.mir	[AArch64][GlobalISel] Add support for s128 loads, stores, extracts, truncs.	2019-07-23 22:05:13 +00:00
select-fabs.mir	[GlobalISel][AArch64] Select G_FABS	2019-01-30 22:54:21 +00:00
select-fcmp.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-floor.mir	[GlobalISel][AArch64] Select G_FFLOOR	2019-02-11 17:22:58 +00:00
select-fma.mir	…
select-fp-casts.mir	[AArch64][GlobalISel] Add isel support for a couple vector exts/truncs	2019-02-11 18:56:39 +00:00
select-frameaddr.ll	Revert "Revert rG6078f2fedcac5797ac39ee5ef3fd7a35ef1202d5 - "[AArch64][GlobalISel]: Support @llvm.{return,frame}address selection.""	2020-01-15 10:13:11 -08:00
select-frint-nofp16.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-frint.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-gv-cmodel-large.mir	Describe stack-id as an enum	2019-06-17 09:13:29 +00:00
select-gv-cmodel-tiny.mir	Describe stack-id as an enum	2019-06-17 09:13:29 +00:00
select-imm.mir	[AArch64][GlobalISel] Emit constant pool loads for 64 bit fp immediates.	2020-06-15 20:53:09 -07:00
select-implicit-def.mir	…
select-insert-extract.mir	…
select-insert-vector-elt.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-int-ext.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-int-ptr-casts.mir	…
select-intrinsic-aarch64-hint.mir	…
select-intrinsic-aarch64-sdiv.mir	…
select-intrinsic-crypto-aesmc.mir	…
select-intrinsic-round.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-intrinsic-trunc.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-jump-table-brjt-constrain.mir	[AArch64][GlobalISel] Constrain reg operands in selectBrJT	2020-04-02 20:34:11 -07:00
select-jump-table-brjt.mir	[AArch64][GlobalISel] Avoid creating redundant ubfx when selecting G_ZEXT	2020-06-16 09:50:47 -07:00
select-ldaxr-intrin.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-ldxr-intrin.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-load-store-vector-of-ptr.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-load.mir	[globalisel] Rename G_GEP to G_PTR_ADD	2019-11-05 10:31:17 -08:00
select-logical-imm.mir	[AArch64][GlobalISel] Select logical_imm32 and logical_imm64 patterns	2019-08-20 22:31:25 +00:00
select-logical-shifted-reg.mir	[AArch64][GlobalISel] Select patterns which use shifted register operands	2019-08-20 22:18:06 +00:00
select-mul.mir	…
select-muladd.mir	…
select-nearbyint.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-neon-vcvtfxu2fp.mir	…
select-phi.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-pr32733.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-property.mir	…
select-ptr-add.mir	[AArch64][GlobalISel] Legalize vector G_PTR_ADD and enable selection.	2020-06-12 11:25:17 -07:00
select-redundant-zext-of-load.mir	[AArch64][GlobalISel] Eliminate redundant G_ZEXT when the source is implicitly zext-loaded.	2019-08-02 21:15:36 +00:00
select-redundant-zext.mir	GlobalISel: Verify G_BITCAST changes the type	2020-07-08 17:16:27 -04:00
select-returnaddr.ll	[AArch64][GlobalISel] Fix llvm.returnaddress(0) selection when LR is clobbered.	2020-01-21 22:53:32 -08:00
select-returnaddress-liveins.mir	[AArch64][GlobalISel] Make LR livein to entry in llvm.returnaddress selection	2020-05-11 11:32:12 -07:00
select-rev.mir	[AArch64][GlobalISel] Set hasSideEffects = 0 on custom shuffle opcodes	2020-06-12 09:39:46 -07:00
select-scalar-merge.mir	Fix build errors introduced by r349712 on aarch64 bots.	2018-12-20 03:27:42 +00:00
select-scalar-shift-imm.mir	[GlobalISel] Import patterns containing SUBREG_TO_REG	2019-08-28 20:12:31 +00:00
select-select.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-sextload.mir	…
select-shuffle-to-duplane.mir	[AArch64][GlobalISel] Selection support for vector DUP[X]lane instructions.	2020-07-29 11:41:37 -07:00
select-shuffle-vector.mir	[AArch64][GlobalISel] Selection support for vector DUP[X]lane instructions.	2020-07-29 11:41:37 -07:00
select-shufflevec-undef-mask-elt.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-sqrt.mir	[GlobalISel][AArch64] Add instruction selection support for @llvm.sqrt	2019-01-30 21:03:52 +00:00
select-stlxr-intrin.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-store.mir	[AArch64][GlobalISel] Look through constants when selection stores of 0	2020-07-24 22:46:14 -07:00
select-stx.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-trap.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-trn.mir	[AArch64][GlobalISel] Set hasSideEffects = 0 on custom shuffle opcodes	2020-06-12 09:39:46 -07:00
select-trunc.mir	[AArch64][GlobalISel] Add support for s128 loads, stores, extracts, truncs.	2019-07-23 22:05:13 +00:00
select-uaddo.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-unmerge.mir	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing	2019-09-11 11:16:48 +00:00
select-uzp.mir	[AArch64][GlobalISel] Select uzp1 and uzp2	2020-06-03 15:09:41 -07:00
select-vector-icmp.mir	[AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads.	2020-06-23 19:23:47 -07:00
select-vector-shift.mir	[AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads.	2020-06-23 19:23:47 -07:00
select-with-no-legality-check.mir	[AArch64] Fix over-eager fusing of NEON SIMD MUL/ADD	2019-12-03 15:48:37 +00:00
select-xor.mir	…
select-zextload.mir	[AArch64][GlobalISel] Eliminate redundant G_ZEXT when the source is implicitly zext-loaded.	2019-08-02 21:15:36 +00:00
select-zip.mir	[AArch64][GlobalISel] Select zip1 and zip2	2020-06-02 18:57:11 -07:00
select.mir	[AArch64][GlobalISel] Legalize vector G_PTR_ADD and enable selection.	2020-06-12 11:25:17 -07:00
sext-inreg-ldrow-16b.mir	[AArch64][GlobalISel] Fix extended shift addressing mode selection not handling sxth.	2020-06-25 17:24:32 -07:00
store-addressing-modes.mir	[globalisel] Rename G_GEP to G_PTR_ADD	2019-11-05 10:31:17 -08:00
store-wro-addressing-modes.mir	[GlobalISel][AArch64] Import + select LDR*roW and STR*roW patterns	2020-01-09 12:15:56 -08:00
subreg-copy.mir	[AArch64][GlobalISel] Avoid copies to target register bank for subregister copies	2020-03-05 11:13:02 -08:00
swifterror.ll	Revert "Revert "[GlobalISel][Localizer] Enable intra-block localization of already-local uses.""	2020-03-06 21:35:08 -08:00
swiftself.ll	GlobalISel: support swiftself attribute	2019-08-02 14:09:49 +00:00
tail-call-no-save-fp-lr.ll	llc: Don't overwrite frame-pointer attribute	2020-01-15 20:56:46 -05:00
tbnz-slt.mir	[AArch64][GlobalISel] When generating SUBS for compares, don't write to wzr/xzr.	2020-05-23 22:59:49 -07:00
tbz-sgt.mir	[AArch64][GlobalISel] When generating SUBS for compares, don't write to wzr/xzr.	2020-05-23 22:59:49 -07:00
translate-constant-dag.ll	Revert "Revert "[GlobalISel][Localizer] Enable intra-block localization of already-local uses.""	2020-03-06 21:35:08 -08:00
translate-gep.ll	Revert "[GISel]: Fix incorrect IRTranslation while translating null pointer types"	2020-03-30 19:30:42 -04:00
unknown-intrinsic.ll	…
varargs-ios-translator.ll	GlobalISel: Fix creating MMOs with align 0	2019-01-31 01:38:47 +00:00
vastart.ll	GlobalISel: Fix creating MMOs with align 0	2019-01-31 01:38:47 +00:00
vec-s16-param.ll	[GlobalISel][AArch64] Allow CallLowering to handle types which are normally	2019-04-09 21:22:33 +00:00
widen-narrow-tbz-tbnz.mir	[AArch64][GlobalISel] Properly implement widening for TB(N)Z	2020-02-12 09:24:58 -08:00
xro-addressing-mode-constant.mir	[AArch64][GlobalISel] Select XRO addressing mode with wide immediates	2020-07-29 11:02:10 -07:00