forked from OSchip/llvm-project
220 lines
5.1 KiB
YAML
220 lines
5.1 KiB
YAML
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @test_and_regs() { ret void }
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define void @test_and_imm() { ret void }
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define void @test_bfc() { ret void }
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define void @test_no_bfc_bad_mask() { ret void }
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define void @test_mvn() { ret void }
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define void @test_bic() { ret void }
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define void @test_orn() { ret void }
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...
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---
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name: test_and_regs
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# CHECK-LABEL: name: test_and_regs
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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%0(s32) = COPY $r0
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; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
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%1(s32) = COPY $r1
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; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
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%2(s32) = G_AND %0, %1
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; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ANDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGRES]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_and_imm
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# CHECK-LABEL: name: test_and_imm
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
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%1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
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%2(s32) = G_AND %0, %1
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; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ANDri [[VREGX]], 786444, 14, $noreg, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGRES]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_bfc
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# CHECK-LABEL: name: test_bfc
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
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%1(s32) = G_CONSTANT i32 -65529 ; 0xFFFF0007
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%2(s32) = G_AND %0, %1
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; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2BFC [[VREGX]], -65529, 14, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGRES]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_no_bfc_bad_mask
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# CHECK-LABEL: name: test_no_bfc_bad_mask
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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%1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
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%2(s32) = G_AND %0, %1
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; CHECK-NOT: t2BFC
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_mvn
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# CHECK-LABEL: name: test_mvn
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
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%1(s32) = G_CONSTANT i32 -1
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%2(s32) = G_XOR %0, %1
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; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MVNr [[VREGX]], 14, $noreg, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGRES]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_bic
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# CHECK-LABEL: name: test_bic
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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; CHECK-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
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; CHECK-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
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%2(s32) = G_CONSTANT i32 -1
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%3(s32) = G_XOR %1, %2
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%4(s32) = G_AND %0, %3
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; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2BICrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
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$r0 = COPY %4(s32)
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; CHECK: $r0 = COPY [[VREGRES]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_orn
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# CHECK-LABEL: name: test_orn
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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; CHECK-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
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; CHECK-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
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%2(s32) = G_CONSTANT i32 -1
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%3(s32) = G_XOR %1, %2
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%4(s32) = G_OR %0, %3
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; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ORNrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
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$r0 = COPY %4(s32)
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; CHECK: $r0 = COPY [[VREGRES]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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