forked from OSchip/llvm-project
217 lines
8.2 KiB
LLVM
217 lines
8.2 KiB
LLVM
; RUN: llc < %s -mcpu=cortex-a9 -verify-coalescing | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
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target triple = "thumbv7-apple-ios0.0.0"
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; CHECK: f
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; The vld2 and vst2 are not aligned wrt each other, the second Q loaded is the
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; first one stored.
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; The coalescer must find a super-register larger than QQ to eliminate the copy
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; setting up the vst2 data.
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; CHECK: vld2
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; CHECK-NOT: vorr
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; CHECK-NOT: vmov
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; CHECK: vst2
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define void @f(float* %p, i32 %c) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
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%vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
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%add.ptr = getelementptr inbounds float* %p, i32 8
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%1 = bitcast float* %add.ptr to i8*
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tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> undef, i32 4)
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ret void
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}
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; CHECK: f1
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; FIXME: This function still has copies.
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define void @f1(float* %p, i32 %c) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
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%vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
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%add.ptr = getelementptr inbounds float* %p, i32 8
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%1 = bitcast float* %add.ptr to i8*
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%vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4)
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%vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0
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tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> %vld2215, i32 4)
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ret void
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}
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; CHECK: f2
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; FIXME: This function still has copies.
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define void @f2(float* %p, i32 %c) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
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%vld224 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
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br label %do.body
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do.body: ; preds = %do.body, %entry
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%qq0.0.1.0 = phi <4 x float> [ %vld224, %entry ], [ %vld2216, %do.body ]
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%c.addr.0 = phi i32 [ %c, %entry ], [ %dec, %do.body ]
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%p.addr.0 = phi float* [ %p, %entry ], [ %add.ptr, %do.body ]
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%add.ptr = getelementptr inbounds float* %p.addr.0, i32 8
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%1 = bitcast float* %add.ptr to i8*
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%vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4)
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%vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0
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%vld2216 = extractvalue { <4 x float>, <4 x float> } %vld22, 1
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tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %qq0.0.1.0, <4 x float> %vld2215, i32 4)
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%dec = add nsw i32 %c.addr.0, -1
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %do.end, label %do.body
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do.end: ; preds = %do.body
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ret void
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}
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declare { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8*, i32) nounwind readonly
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declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind
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; CHECK: f3
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; This function has lane insertions that span basic blocks.
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; The trivial REG_SEQUENCE lowering can't handle that, but the coalescer can.
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;
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; void f3(float *p, float *q) {
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; float32x2_t x;
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; x[1] = p[3];
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; if (q)
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; x[0] = q[0] + q[1];
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; else
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; x[0] = p[2];
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; vst1_f32(p+4, x);
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; }
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;
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; CHECK-NOT: vmov
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; CHECK-NOT: vorr
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define void @f3(float* %p, float* %q) nounwind ssp {
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entry:
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%arrayidx = getelementptr inbounds float* %p, i32 3
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%0 = load float* %arrayidx, align 4
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%vecins = insertelement <2 x float> undef, float %0, i32 1
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%tobool = icmp eq float* %q, null
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br i1 %tobool, label %if.else, label %if.then
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if.then: ; preds = %entry
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%1 = load float* %q, align 4
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%arrayidx2 = getelementptr inbounds float* %q, i32 1
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%2 = load float* %arrayidx2, align 4
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%add = fadd float %1, %2
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%vecins3 = insertelement <2 x float> %vecins, float %add, i32 0
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br label %if.end
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if.else: ; preds = %entry
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%arrayidx4 = getelementptr inbounds float* %p, i32 2
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%3 = load float* %arrayidx4, align 4
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%vecins5 = insertelement <2 x float> %vecins, float %3, i32 0
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%x.0 = phi <2 x float> [ %vecins3, %if.then ], [ %vecins5, %if.else ]
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%add.ptr = getelementptr inbounds float* %p, i32 4
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%4 = bitcast float* %add.ptr to i8*
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tail call void @llvm.arm.neon.vst1.v2f32(i8* %4, <2 x float> %x.0, i32 4)
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ret void
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}
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declare void @llvm.arm.neon.vst1.v2f32(i8*, <2 x float>, i32) nounwind
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declare <2 x float> @llvm.arm.neon.vld1.v2f32(i8*, i32) nounwind readonly
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; CHECK: f4
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; This function inserts a lane into a fully defined vector.
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; The destination lane isn't read, so the subregs can coalesce.
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; CHECK-NOT: vmov
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; CHECK-NOT: vorr
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define void @f4(float* %p, float* %q) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld1 = tail call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %0, i32 4)
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%tobool = icmp eq float* %q, null
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br i1 %tobool, label %if.end, label %if.then
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if.then: ; preds = %entry
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%1 = load float* %q, align 4
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%arrayidx1 = getelementptr inbounds float* %q, i32 1
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%2 = load float* %arrayidx1, align 4
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%add = fadd float %1, %2
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%vecins = insertelement <2 x float> %vld1, float %add, i32 1
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br label %if.end
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if.end: ; preds = %entry, %if.then
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%x.0 = phi <2 x float> [ %vecins, %if.then ], [ %vld1, %entry ]
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tail call void @llvm.arm.neon.vst1.v2f32(i8* %0, <2 x float> %x.0, i32 4)
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ret void
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}
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; CHECK: f5
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; Coalesce vector lanes through phis.
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; CHECK: vmov.f32 {{.*}}, #1.0
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; CHECK-NOT: vmov
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; CHECK-NOT: vorr
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; CHECK: %if.end
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; We may leave the last insertelement in the if.end block.
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; It is inserting the %add value into a dead lane, but %add causes interference
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; in the entry block, and we don't do dead lane checks across basic blocks.
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define void @f5(float* %p, float* %q) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld1 = tail call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %0, i32 4)
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%vecext = extractelement <4 x float> %vld1, i32 0
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%vecext1 = extractelement <4 x float> %vld1, i32 1
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%vecext2 = extractelement <4 x float> %vld1, i32 2
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%vecext3 = extractelement <4 x float> %vld1, i32 3
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%add = fadd float %vecext3, 1.000000e+00
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%tobool = icmp eq float* %q, null
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br i1 %tobool, label %if.end, label %if.then
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if.then: ; preds = %entry
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%arrayidx = getelementptr inbounds float* %q, i32 1
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%1 = load float* %arrayidx, align 4
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%add4 = fadd float %vecext, %1
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%2 = load float* %q, align 4
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%add6 = fadd float %vecext1, %2
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%arrayidx7 = getelementptr inbounds float* %q, i32 2
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%3 = load float* %arrayidx7, align 4
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%add8 = fadd float %vecext2, %3
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br label %if.end
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if.end: ; preds = %entry, %if.then
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%a.0 = phi float [ %add4, %if.then ], [ %vecext, %entry ]
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%b.0 = phi float [ %add6, %if.then ], [ %vecext1, %entry ]
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%c.0 = phi float [ %add8, %if.then ], [ %vecext2, %entry ]
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%vecinit = insertelement <4 x float> undef, float %a.0, i32 0
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%vecinit9 = insertelement <4 x float> %vecinit, float %b.0, i32 1
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%vecinit10 = insertelement <4 x float> %vecinit9, float %c.0, i32 2
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%vecinit11 = insertelement <4 x float> %vecinit10, float %add, i32 3
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tail call void @llvm.arm.neon.vst1.v4f32(i8* %0, <4 x float> %vecinit11, i32 4)
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ret void
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}
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declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
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declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
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; CHECK: pr13999
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define void @pr13999() nounwind readonly {
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entry:
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br i1 true, label %outer_loop, label %loop.end
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outer_loop:
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%d = phi double [ 0.0, %entry ], [ %add, %after_inner_loop ]
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%0 = insertelement <2 x double> <double 0.0, double 0.0>, double %d, i32 0
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br i1 undef, label %after_inner_loop, label %inner_loop
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inner_loop:
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br i1 true, label %after_inner_loop, label %inner_loop
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after_inner_loop:
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%1 = phi <2 x double> [ %0, %outer_loop ], [ <double 0.0, double 0.0>,
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%inner_loop ]
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%2 = extractelement <2 x double> %1, i32 1
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%add = fadd double 1.0, %2
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br i1 false, label %loop.end, label %outer_loop
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loop.end:
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%d.end = phi double [ 0.0, %entry ], [ %add, %after_inner_loop ]
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ret void
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}
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