Vasileios Kalintiris 974d409259 [mips] Added support for the ERETNC instruction. ... Summary: This required adding the instruction predicate HasMips32r5. Patch by Scott Egerton. Reviewers: dsanders, vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11136 llvm-svn: 242666		2015-07-20 12:28:56 +00:00
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AArch64	[AArch64] Fix problems in decoding generic MSR instructions	2015-07-15 08:10:30 +00:00
ARM	[ARM] Add v8.1a "Privileged Access Never" extension	2015-04-16 11:34:25 +00:00
Hexagon	[Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly.	2015-06-10 16:52:32 +00:00
Mips	[mips] Added support for the ERETNC instruction.	2015-07-20 12:28:56 +00:00
PowerPC	[PPC] Disassemble little endian ppc instructions in the right byte order	2015-07-15 12:56:19 +00:00
Sparc	Sparc: Support PSR, TBR, WIM read/write instructions.	2015-05-18 16:38:47 +00:00
SystemZ	[SystemZ] Add z13 vector facility and MC support	2015-05-05 19:23:40 +00:00
X86	[X86]: Correctly sign-extend 16-bit immediate in CALL instruction.	2015-06-26 16:58:59 +00:00
XCore	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00