forked from OSchip/llvm-project
6f4922ccc9
Summary: We generate s_xor to lower add of i1s in general cases, and s_not to lower add with a one-bit imm of -1 (true). Reviewers: rampitec Differential Revision: https://reviews.llvm.org/D52518 llvm-svn: 343030 |
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AArch64 | ||
AMDGPU | ||
ARC | ||
ARM | ||
AVR | ||
BPF | ||
Generic | ||
Hexagon | ||
Inputs | ||
Lanai | ||
MIR | ||
MSP430 | ||
Mips | ||
NVPTX | ||
Nios2 | ||
PowerPC | ||
RISCV | ||
SPARC | ||
SystemZ | ||
Thumb | ||
Thumb2 | ||
WebAssembly | ||
WinCFGuard | ||
WinEH | ||
X86 | ||
XCore |