llvm-project/llvm/test/CodeGen
Changpeng Fang 6f4922ccc9 AMDGPU: Add Selection patterns to support add of one bit.
Summary:
  We generate s_xor to lower add of i1s in general cases, and s_not to
lower add with a one-bit imm of -1 (true).

Reviewers:
  rampitec

Differential Revision:
  https://reviews.llvm.org/D52518

llvm-svn: 343030
2018-09-25 21:21:18 +00:00
..
AArch64 Re-submitting changes in D51550 because it failed to patch. 2018-09-24 20:47:12 +00:00
AMDGPU AMDGPU: Add Selection patterns to support add of one bit. 2018-09-25 21:21:18 +00:00
ARC
ARM [ARM] Do not fuse VADD and VMUL on the Cortex-M4 and Cortex-M33 2018-09-24 12:02:50 +00:00
AVR [AVR] Redefine the 'LSL' instruction as an alias of 'ADD' 2018-09-01 12:23:00 +00:00
BPF [bpf] Test case for symbol information in object file 2018-09-22 17:31:01 +00:00
Generic Re-submitting changes in D51550 because it failed to patch. 2018-09-24 20:47:12 +00:00
Hexagon [MachineVerifier] Relax checkLivenessAtDef regarding dead subreg defs 2018-09-20 06:59:18 +00:00
Inputs
Lanai
MIR add IR flags to MI 2018-09-11 21:35:32 +00:00
MSP430 [DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks) 2018-08-29 11:18:14 +00:00
Mips [Mips][FastISel] Fix selectBranch on icmp i1 2018-09-24 14:14:19 +00:00
NVPTX [NVPTX] Implement isLegalToVectorizeLoadChain 2018-08-27 17:29:43 +00:00
Nios2
PowerPC [Power9] [LLVM] Add __float128 exponent GET and SET builtins 2018-09-24 18:14:13 +00:00
RISCV [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A 2018-09-19 10:54:22 +00:00
SPARC [Sparc] Use ANDN instead of AND if constant can be encoded more efficiently 2018-08-30 14:05:26 +00:00
SystemZ [DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks) 2018-08-29 11:18:14 +00:00
Thumb Revert "[ConstHoist] Do not rebase single (or few) dependent constant" 2018-09-25 18:41:40 +00:00
Thumb2 [ARM] Do not fuse VADD and VMUL on the Cortex-M4 and Cortex-M33 2018-09-24 12:02:50 +00:00
WebAssembly [WebAssembly] SIMD sqrt 2018-09-25 03:39:28 +00:00
WinCFGuard [COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables 2018-09-19 09:58:30 +00:00
WinEH
X86 [x86] avoid 256-bit andnp that requires insert/extract with AVX1 (PR37449) 2018-09-25 19:09:34 +00:00
XCore