llvm-project/llvm/test/CodeGen/AMDGPU
Mircea Trofin b470630913 [NFC] Removed unused prefixes from CodeGen/AMDGPU
All the 'l'-starting tests.

Differential Revision: https://reviews.llvm.org/D94151
2021-01-06 09:34:11 -08:00
..
GlobalISel AMDGPU/GlobalISel: Update fdiv lowering for denormal/ulp interaction 2021-01-06 12:32:01 -05:00
32-bit-local-address-space.ll Fix 64-bit copy to SCC 2020-08-09 20:50:30 +02:00
InlineAsmCrash.ll [AMDGPU] Control num waves per EU for implicit work-group size 2020-07-01 22:53:52 -04:00
README
SRSRC-GIT-clobber-check.mir [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
aa-points-to-constant-memory.ll AMDGPU: Skip GetUnderlyingObject check in pointsToConstantMemory 2020-05-09 16:00:08 -04:00
accvgpr-copy.mir AMDGPU: Don't kill super-register with overlapping copy 2020-10-16 09:34:35 -04:00
add-debug.ll
add.i16.ll [AMDGPU][MC] Corrected decoding of 16-bit literals 2020-07-22 17:20:43 +03:00
add.ll
add.v2i16.ll [AMDGPU][MC] Corrected decoding of 16-bit literals 2020-07-22 17:20:43 +03:00
add3.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
add_i1.ll
add_i64.ll
add_i128.ll
add_shl.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
addrspacecast-captured.ll
addrspacecast-constantexpr.ll [IR] Make nosync, nofree and willreturn default for intrinsics. 2020-10-20 11:57:19 +02:00
addrspacecast-initializer-unsupported.ll Support addrspacecast initializers with isNoopAddrSpaceCast 2020-07-31 10:42:43 -04:00
addrspacecast-initializer.ll Support addrspacecast initializers with isNoopAddrSpaceCast 2020-07-31 10:42:43 -04:00
addrspacecast.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
adjust-writemask-invalid-copy.ll
agpr-register-count.ll
agpr-remat.ll AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32 2020-07-01 18:58:59 -04:00
alignbit-pat.ll
alloca.ll AllocaInst should store Align instead of MaybeAlign. 2020-05-16 14:53:16 -07:00
always-uniform.ll
amd.endpgm.ll [amdgpu] Add `llvm.amdgcn.endpgm` support. 2020-11-05 19:06:50 -05:00
amdgcn-ieee.ll [AMDGPU] Fix ieee mode default value 2020-11-04 12:25:38 +01:00
amdgcn-load-offset-from-reg.ll AMDGPU: Convert some tests to use new buffer intrinsics 2020-07-30 10:30:43 -04:00
amdgcn.bitcast.ll [AMDGPU] Fix crash when dag-combining bitcast 2020-08-13 10:23:13 +08:00
amdgcn.private-memory.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdgpu-alias-analysis.ll [NewPM][AMDGPU] Make amdgpu-aa work with NewPM 2021-01-04 12:36:27 -08:00
amdgpu-codegenprepare-fdiv.ll AMDGPU: Remove denormal subtarget features 2020-04-02 17:17:12 -04:00
amdgpu-codegenprepare-fold-binop-select.ll [ConstantFold] Fold more operations to poison 2020-11-29 21:19:48 +09:00
amdgpu-codegenprepare-i16-to-i32.ll AMDGPU: Generate test checks 2020-01-20 20:03:45 -05:00
amdgpu-codegenprepare-idiv.ll [AMDGPU] Don't cluster stores 2020-09-14 13:40:17 +01:00
amdgpu-codegenprepare-mul24.ll
amdgpu-function-calls-option.ll
amdgpu-inline.ll
amdgpu-mul24-knownbits.ll [AMDGPU] simplifyI24 - replace GetDemandedBits with SimplifyMultipleUseDemandedBits 2020-02-20 12:03:08 +00:00
amdgpu-reloc-const.ll [llvm-readobj] - For SHT_REL relocations, don't display an addend. 2020-12-14 12:03:00 +03:00
amdgpu-shader-calling-convention.ll
amdgpu-unroll-threshold.ll [BasicAA] Rename deprecated -basicaa to -basic-aa 2020-06-26 20:41:37 -07:00
amdgpu.private-memory.ll Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access"" 2020-11-11 14:40:14 +00:00
amdgpu.work-item-intrinsics.deprecated.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdhsa-trap-num-sgprs.ll [AMDGPU/MemOpsCluster] Clean-up fixme's around mem ops clustering logic 2020-07-30 21:41:13 +05:30
amdpal-callable.ll [AMDGPU] Mark amdgpu_gfx functions as module entry function 2020-12-14 10:43:39 +01:00
amdpal-cs.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-elf.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
amdpal-es.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-gs.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-hs.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-ls.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-cs.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-default.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-denormal.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-dx10-clamp.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-es.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-gs.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-hs.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-ieee.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-ls.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-ps.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-psenable.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-vs.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-ps.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-psenable.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-vs.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal.ll [AMDGPU] Emit new pal metadata by default 2020-10-26 10:16:17 +01:00
amdpal_scratch_mergedshader.ll
and-gcn.ll
and.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
and_or.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
andorbitset.ll AMDGPU: Fix verifier error with undef source producing s_bitset* 2020-08-05 14:42:20 -04:00
andorn2.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
andorxorinvimm.ll
annotate-kernel-features-hsa-call.ll AMDGPU: Add IntrWillReturn to intrinsic definitions 2020-06-18 15:38:10 -04:00
annotate-kernel-features-hsa.ll AMDGPU: Add IntrWillReturn to intrinsic definitions 2020-06-18 15:38:10 -04:00
annotate-kernel-features.ll
annotate-noclobber.ll AMDGPU: Annotate amdgpu.noclobber for global loads only 2021-01-05 14:47:19 -08:00
anonymous-gv.ll
any_extend_vector_inreg.ll
anyext.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
are-loads-from-same-base-ptr.ll
array-ptr-calc-i32.ll [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions 2020-03-19 15:35:16 -04:00
array-ptr-calc-i64.ll
ashr.v2i16.ll [AMDGPU] fixed divergence driven shift operations selection 2020-01-31 20:49:56 +03:00
asm-printer-check-vcc.mir [AMDGPU] Fix offset for REL32_HI relocs 2020-09-02 10:55:55 +01:00
at-least-one-def-value-assert.mir [AMDGPU] Define 16 bit VGPR subregs 2020-03-31 11:49:06 -07:00
atomic_cmp_swap_local.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
atomic_load_add.ll
atomic_load_local.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
atomic_load_sub.ll
atomic_optimizations_buffer.ll [AMDGPU] Move WQM Pass after MI Scheduler 2020-10-27 10:25:53 +09:00
atomic_optimizations_global_pointer.ll [AMDGPU] Move WQM Pass after MI Scheduler 2020-10-27 10:25:53 +09:00
atomic_optimizations_local_pointer.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
atomic_optimizations_pixelshader.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
atomic_optimizations_raw_buffer.ll [AMDGPU] Move WQM Pass after MI Scheduler 2020-10-27 10:25:53 +09:00
atomic_optimizations_struct_buffer.ll [AMDGPU] Move WQM Pass after MI Scheduler 2020-10-27 10:25:53 +09:00
atomic_store_local.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
atomicrmw-nand.ll
attr-amdgpu-flat-work-group-size-v3.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
attr-amdgpu-flat-work-group-size-vgpr-limit.ll [AMDGPU] Fix getEUsPerCU for gfx10 in CU mode 2020-03-27 20:36:49 +00:00
attr-amdgpu-flat-work-group-size.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
attr-amdgpu-num-sgpr.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
attr-amdgpu-num-vgpr.ll
attr-amdgpu-waves-per-eu.ll
attr-unparseable.ll
barrier-elimination.ll [AMDGPU][GlobalISel] Eliminate barrier if workgroup size is not greater than wavefront size 2020-08-26 13:47:51 +01:00
basic-branch.ll [AMDGPU] Use lowercase for subtarget feature names in RUN lines 2020-10-13 09:02:09 +01:00
basic-call-return.ll
basic-loop.ll
bfe-combine.ll
bfe-patterns.ll [AMDGPU] Make bfe patterns divergence-aware 2020-10-05 09:55:10 +01:00
bfe_uint.ll
bfi_int.ll [AMDGPU] Add alignment check for v3 to v4 load type promotion 2020-11-01 12:05:34 +05:30
bfm.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
big_alu.ll
bitcast-constant-to-vector.ll [MachineScheduler] Reduce reordering due to mem op clustering 2020-01-14 19:19:02 +00:00
bitcast-v4f16-v4i16.ll AMDGPU: Fix some more incorrect check lines 2020-02-26 14:37:22 +00:00
bitcast-vector-extract.ll
bitreverse-inline-immediates.ll
bitreverse.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
br_cc.f16.ll
branch-condition-and.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
branch-relax-bundle.ll
branch-relax-spill.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
branch-relaxation-debug-info.mir AMDGPU: Convert test to MIR 2020-09-01 11:01:02 -04:00
branch-relaxation-gfx10-branch-offset-bug.ll AMDGPU: Increase branch size estimate with offset bug 2020-10-23 10:34:24 -04:00
branch-relaxation-inst-size-gfx10.ll
branch-relaxation.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
branch-uniformity.ll [AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU. 2020-04-06 09:05:58 -04:00
break-smem-soft-clauses.mir [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
break-vmem-soft-clauses.mir [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
bswap.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
buffer-intrinsics-mmo-offsets.ll [AMDGPU] Add default 1 glc operand to rtn atomics 2020-11-05 10:41:59 -08:00
buffer-schedule.ll
bug-sdag-scheduler-cycle.ll SelectionDAG: Fix bug in ClusterNeighboringLoads 2020-02-12 09:12:55 +01:00
bug-vopc-commute.ll
build-vector-insert-elt-infloop.ll
build-vector-packed-partial-undef.ll [AMDGPU] Add ISD::FSHR -> ALIGNBIT support 2020-03-12 20:16:57 +00:00
build_vector.ll
bundle-latency.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
bypass-div.ll [AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM 2020-07-08 19:14:49 +01:00
byval-frame-setup.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
call-argument-types.ll OpaquePtr: Update more tests to use typed sret 2020-11-20 20:08:43 -05:00
call-constant.ll AMDGPU: Don't assume call targets are registers 2020-07-28 20:46:06 -04:00
call-constexpr.ll Ensure SplitEdge to return the new block between the two given blocks 2020-12-18 17:37:17 +00:00
call-encoding.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
call-graph-register-usage.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
call-preserved-registers.ll [AMDGPU] Omit buffer resource with flat scratch. 2020-11-09 08:05:20 -08:00
call-return-types.ll AMDGPU: Improve <2 x i24> arguments and return value handling 2020-09-16 11:21:56 -04:00
call-skip.ll Resubmit: [AMDGPU] Invert the handling of skip insertion. 2020-01-22 13:18:32 +09:00
call-to-kernel-undefined.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
call-to-kernel.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
call-waitcnt.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
call-waw-waitcnt.mir
call_fs.ll
callee-frame-setup.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
callee-special-input-sgprs-fixed-abi.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
callee-special-input-sgprs.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
callee-special-input-vgprs.ll OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00
calling-conventions.ll AMDGPU: Allow i16 shader arguments 2020-01-27 06:55:32 -08:00
captured-frame-index.ll [AMDGPU] Fix offset for REL32_HI relocs 2020-09-02 10:55:55 +01:00
carryout-selection.ll AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
cayman-loop-bug.ll
cc-sgpr-limit.ll
cc-sgpr-over-limit.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
cc-update.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
cf-loop-on-constant.ll [AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU. 2020-04-06 09:05:58 -04:00
cf-stack-bug.ll
cf_end.ll
cgp-addressing-modes-flat.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
cgp-addressing-modes-gfx908.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
cgp-addressing-modes-gfx1030.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
cgp-addressing-modes.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
cgp-bitfield-extract.ll [AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU. 2020-04-06 09:05:58 -04:00
chain-hi-to-lo.ll [AMDGPU] Support unaligned flat scratch in TLI 2020-12-22 16:12:31 -08:00
clamp-modifier.ll [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed 2021-01-04 14:44:10 -06:00
clamp-omod-special-case.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
clamp.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
cluster-flat-loads-postra.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
cluster-flat-loads.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
cluster_stores.ll [AMDGPU] Don't cluster stores 2020-09-14 13:40:17 +01:00
cmp_shrink.mir [AMDGPU] Avoid using s_cmpk when src0 is not register 2020-07-14 09:05:53 +01:00
cndmask-no-def-vcc.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
coalesce-identity-copies-undef-subregs.mir RegisterCoalescer: Remove phi-only subranges when erasing identity copies 2020-12-15 17:36:32 -05:00
coalescer-extend-pruned-subrange.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
coalescer-identical-values-undef.mir
coalescer-removepartial-extend-undef-subrange.mir [RegisterCoalescer] Pass Undefs to extendToIndices() 2020-09-29 08:14:24 +08:00
coalescer-subranges-another-copymi-not-live.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
coalescer-subranges-another-prune-error.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
coalescer-subranges-prune-kill-copy.mir
coalescer-subreg-join.mir AMDGPU: Move MIMG MMO check to verifier 2020-05-29 20:58:23 -04:00
coalescer-subregjoin-fullcopy.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
coalescer-with-subregs-bad-identical.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
coalescer_distribute.ll
coalescer_remat.ll
coalescing-subreg-was-undef-but-became-def.mir [AMDGPU] Add the test from D49097. 2020-05-20 14:34:51 +01:00
coalescing-with-subregs-in-loop-bug.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
coalescing_makes_lanes_undef.mir [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining 2020-09-24 17:37:03 +03:00
code-object-v3.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
codegen-prepare-addrmode-sext.ll
collapse-endcf-broken.mir
collapse-endcf.ll [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions 2020-03-19 15:35:16 -04:00
collapse-endcf.mir [AMDGPU] Remove fix up operand from SI_ELSE 2020-10-20 19:15:21 +09:00
collapse-endcf2.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
combine-and-sext-bool.ll
combine-cond-add-sub.ll
combine-ftrunc.ll
combine_vloads.ll
comdat.ll
commute-compares.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
commute-shifts.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
commute_modifiers.ll
complex-folding.ll
computeKnownBits-scalar-to-vector-crash.ll
computeNumSignBits-mul.ll
concat_vectors.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
constant-address-space-32bit.ll
constant-fold-imm-immreg.mir [AMDGPU] More codegen patterns for v2i16/v2f16 build_vector 2020-09-22 10:41:38 +01:00
constant-fold-mi-operands.ll
control-flow-fastregalloc.ll [AMDGPU] Remove fix up operand from SI_ELSE 2020-10-20 19:15:21 +09:00
control-flow-optnone.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
convergent-inlineasm.ll Resubmit: [AMDGPU] Invert the handling of skip insertion. 2020-01-22 13:18:32 +09:00
copy-illegal-type.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
copy-overlap-vgpr-kill.mir AMDGPU: Don't kill super-register with overlapping copy 2020-10-16 09:34:35 -04:00
copy-to-reg.ll
couldnt-join-subrange-3.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
cross-block-use-is-not-abi-copy.ll [AMDGPU] Use pseudo instructions for readlane/writelane 2020-10-29 16:00:53 +00:00
cse-phi-incoming-val.ll Resubmit: [AMDGPU] Invert the handling of skip insertion. 2020-01-22 13:18:32 +09:00
csr-gfx10.ll [AMDGPU] Use pseudo instructions for readlane/writelane 2020-10-29 16:00:53 +00:00
csr-sgpr-spill-live-ins.mir AMDGPU: Add spilled CSR SGPRs to entry block live ins 2020-12-22 21:55:59 -05:00
ctlz.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
ctlz_zero_undef.ll Fix 64-bit copy to SCC 2020-08-09 20:50:30 +02:00
ctpop.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
ctpop16.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
ctpop64.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
cttz_zero_undef.ll [AMDGPU/MemOpsCluster] Clean-up fixme's around mem ops clustering logic 2020-07-30 21:41:13 +05:30
cube.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
cvt_f32_ubyte.ll [AMDGPU] Optimize waitcnt insertion for flat memory operations 2020-10-20 22:55:12 +00:00
cvt_flr_i32_f32.ll
cvt_rpi_i32_f32.ll
dag-divergence.ll
dagcomb-shuffle-vecextend-non2.ll
dagcombine-reassociate-bug.ll
dagcombine-select.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
dagcombine-setcc-select.ll
dagcombiner-bug-illegal-vec4-int-to-fp.ll
dbg-value-ends-sched-region.mir ScheduleDAGInstrs: Skip debug instructions at end of scheduling region 2020-10-22 10:16:45 -04:00
dce-disjoint-intervals.mir
dead-lane.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
dead-machine-elim-after-dead-lane.ll [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. 2020-01-14 19:26:15 -05:00
dead_copy.mir
debug-value-scheduler-crash.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
debug-value.ll AMDGPU: Remove denormal subtarget features 2020-04-02 17:17:12 -04:00
debug-value2.ll
debug.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
default-fp-mode.ll AMDGPU: Add some tests for exotic denormal mode combinations 2020-04-02 17:17:12 -04:00
detect-dead-lanes.mir
directive-amdgcn-target.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
disable_form_clauses.ll AMDGPU: Remove SIFixupVectorISel pass 2020-08-15 12:11:51 -04:00
disconnected-predset-break-bug.ll
div_i128.ll AMDGPU: Have a few selection failure tests check both paths 2020-08-24 17:46:31 -04:00
diverge-extra-formal-args.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
diverge-interp-mov-lower.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
diverge-switch-default.ll [InstCombine] fix operands of shouldChangeType() for casted phi transform 2020-02-04 07:45:48 -05:00
divergence-at-use.ll
divergent-branch-uniform-condition.ll [AMDGPU] add generated checks for some LIT tests 2020-03-03 11:47:05 +05:30
divrem24-assume.ll [AMDGPU] Fix some tests that did not specify -mcpu 2020-02-17 14:02:32 +00:00
dpp_combine.ll
dpp_combine.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
drop-mem-operand-move-smrd.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
ds-combine-large-stride.ll
ds-combine-with-dependence.ll [amdgpu] Enable use of AA during codegen. 2020-10-27 09:46:23 -04:00
ds-negative-offset-addressing-mode-loop.ll
ds-sub-offset.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
ds_read2.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
ds_read2_offset_order.ll AMDGPU/SILoadStoreOptimizer: Improve merging of out of order offsets 2020-01-24 19:45:56 -08:00
ds_read2_superreg.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
ds_read2st64.ll AMDGPU: Match global saddr addressing mode 2020-08-17 15:28:14 -04:00
ds_write2.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
ds_write2st64.ll AMDGPU: Match global saddr addressing mode 2020-08-17 15:28:14 -04:00
dynamic_stackalloc.ll
early-if-convert-cost.ll
early-if-convert.ll AMDGPU: Fix backwards s_cselect_* operands 2020-05-27 09:26:09 -04:00
early-inline-alias.ll
early-inline.ll
early-tailduplicator-nophis.mir
elf-header-flags-mach.ll [AMDGPU] Add gfx1033 target 2020-11-03 16:27:48 +00:00
elf-header-flags-sram-ecc.ll
elf-header-flags-xnack.ll
elf-header-osabi.ll
elf-notes.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
elf.ll [Object] Change ELFObjectFile<ELFT>::getFileFormatName() to use BFD names 2020-03-16 07:42:04 -07:00
elf.metadata.ll
elf.r600.ll [Object] Change ELFObjectFile<ELFT>::getFileFormatName() to use BFD names 2020-03-16 07:42:04 -07:00
else.ll Resubmit: [AMDGPU] Invert the handling of skip insertion. 2020-01-22 13:18:32 +09:00
empty-function.ll
enable-no-signed-zeros-fp-math.ll
endcf-loop-header.ll
endpgm-dce.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
enqueue-kernel.ll OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00
exceed-max-sgprs.ll
expand-scalar-carry-out-select-user.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
expand-si-indirect.mir [AMDGPU] Add new pseudos for indirect addressing with VGPR Indexing 2020-12-08 12:24:12 -08:00
extend-bit-ops-i16.ll
extload-align.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
extload-private.ll [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions 2020-03-19 15:35:16 -04:00
extload.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
extra-sroa-after-unroll.ll [NFC][AMDGPU] Clean up some lit test prefixes 2020-11-11 17:12:37 +00:00
extract-load-i1.ll [DAGCombine] Fix bug in load scalarization 2020-11-04 19:02:40 +00:00
extract-lowbits.ll [AMDGPU] fixed divergence driven shift operations selection 2020-01-31 20:49:56 +03:00
extract-subvector-equal-length.ll
extract-subvector.ll [AMDGPU] Fixed selection error for 64 bit extract_subvector 2020-05-18 14:17:59 -07:00
extract-vector-elt-build-vector-combine.ll
extract_subvector_vec4_vec3.ll Revert "Revert "[MIR] Target specific MIR formating and parsing"" 2020-01-08 20:03:29 -08:00
extract_vector_dynelt.ll [AMDGPU] Select s_cselect 2020-06-25 10:38:23 +02:00
extract_vector_elt-f16.ll
extract_vector_elt-f64.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
extract_vector_elt-i8.ll
extract_vector_elt-i16.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
extract_vector_elt-i64.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
extractelt-to-trunc.ll Fix 64-bit copy to SCC 2020-08-09 20:50:30 +02:00
fabs.f16.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
fabs.f64.ll
fabs.ll Revert "[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel." 2020-09-18 09:48:33 -04:00
fadd-fma-fmul-combine.ll [AMDGPU] Add gfx1030 target 2020-06-15 16:18:05 -07:00
fadd.f16.ll [AMDGPU] Precommit some scheduler related test updates 2020-02-28 11:20:58 +00:00
fadd.ll
fadd64.ll
fail-select-buffer-atomic-fadd.ll [AMDGPU] Unify intrinsic ret/nortn interface 2020-09-15 15:26:42 -07:00
fast-ra-kills-vcc.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
fast-regalloc-bundles.mir [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fast-unaligned-load-store.global.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fast-unaligned-load-store.private.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fastregalloc-illegal-subreg-physreg.mir Reapply "RegAllocFast: Rewrite and improve" 2020-09-30 10:35:25 -04:00
fastregalloc-self-loop-heuristic.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
fcanonicalize-elimination.ll AMDGPU: Match global saddr addressing mode 2020-08-17 15:28:14 -04:00
fcanonicalize.f16.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
fcanonicalize.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
fceil.ll
fceil64.ll Fix 64-bit copy to SCC 2020-08-09 20:50:30 +02:00
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.f16.ll [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics 2020-07-17 11:02:13 +01:00
fcmp.ll
fcmp64.ll
fconst64.ll
fcopysign.f16.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fcopysign.f32.ll
fcopysign.f64.ll
fdiv-nofpexcept.ll [AMDGPU] Allow some modifiers on VOP3B instructions 2020-10-28 21:54:14 +00:00
fdiv.f16.ll AMDGPU: Match global saddr addressing mode 2020-08-17 15:28:14 -04:00
fdiv.f64.ll
fdiv.ll [DAGCombiner] Require ninf for division estimation 2020-06-14 22:58:22 +08:00
fdiv32-to-rcp-folding.ll [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed 2021-01-04 14:44:10 -06:00
fdot2.ll AMDGPU: Remove denormal subtarget features 2020-04-02 17:17:12 -04:00
fence-barrier.ll
fence-lds-read2-write2.ll AMDGPU: Break read2/write2 search range on a memory fence 2020-04-24 15:53:30 -04:00
fetch-limits.r600.ll
fetch-limits.r700+.ll
fexp.ll
ffloor.f64.ll
ffloor.ll
fix-frame-ptr-reg-copy-livein.ll [AMDGPU] Enable base pointer. 2020-05-17 16:13:55 +05:30
fix-sgpr-copies.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
fix-vgpr-copies.mir
fix-wwm-vgpr-copy.ll AMDGPU: Convert some tests to use new buffer intrinsics 2020-07-30 10:30:43 -04:00
flat-address-space.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
flat-error-unsupported-gpu-hsa.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
flat-for-global-subtarget-feature.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
flat-load-clustering.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
flat-offset-bug.ll [llvm] Fix missing FileCheck directive colons 2020-04-06 09:59:08 -06:00
flat-scratch-fold-fi.mir [AMDGPU] Folding of FI operand with flat scratch 2020-12-22 10:48:04 -08:00
flat-scratch-reg.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
flat-scratch.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
flat_atomics.ll AMDGPU: Add some missing atomics tests 2020-04-26 15:09:35 -04:00
flat_atomics_i64.ll AMDGPU: Add some missing atomics tests 2020-04-26 15:09:35 -04:00
floor.ll
fma-combine.ll [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed 2021-01-04 14:44:10 -06:00
fma.f64.ll
fma.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
fmac.sdwa.ll
fmad-formation-fmul-distribute-denormal-mode.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fmad.ll
fmax.ll
fmax3.f64.ll
fmax3.ll
fmax_legacy.f16.ll
fmax_legacy.f64.ll [AMDGPU] Optimize waitcnt insertion for flat memory operations 2020-10-20 22:55:12 +00:00
fmax_legacy.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fmaxnum.f64.ll
fmaxnum.ll AMDGPU: Remove denormal subtarget features 2020-04-02 17:17:12 -04:00
fmaxnum.r600.ll
fmed3.ll
fmin.ll
fmin3.ll
fmin_fmax_legacy.amdgcn.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fmin_legacy.f16.ll
fmin_legacy.f64.ll [AMDGPU] Optimize waitcnt insertion for flat memory operations 2020-10-20 22:55:12 +00:00
fmin_legacy.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fminnum.f64.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fminnum.ll AMDGPU: Remove denormal subtarget features 2020-04-02 17:17:12 -04:00
fminnum.r600.ll
fmul-2-combine-multi-use.ll AMDGPU: Remove denormal subtarget features 2020-04-02 17:17:12 -04:00
fmul.f16.ll
fmul.ll
fmul64.ll
fmuladd.f16.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fmuladd.f32.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fmuladd.f64.ll [NFC][AMDGPU] Improve fused fmul+fadd tests. 2020-07-31 04:00:09 +03:00
fmuladd.v2f16.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fnearbyint.ll
fneg-combines.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fneg-combines.si.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fneg-fabs.f16.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fneg-fabs.f64.ll
fneg-fabs.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fneg-fold-legalize-dag-increase-insts.ll DAG: Stop trying to fold FP -(x-y) -> y-x in getNode with nsz 2019-12-31 22:49:51 -05:00
fneg.f16.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
fneg.f64.ll
fneg.ll
fold-cndmask-wave32.mir [amdgpu] Fix a crash case when `V_CNDMASK` could be simplified. 2020-12-14 13:08:13 -05:00
fold-cndmask.mir
fold-fi-mubuf.mir [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions 2020-03-19 15:35:16 -04:00
fold-fi-operand-shrink.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
fold-fmul-to-neg-abs.ll
fold-imm-copy.mir AMDGPU: Fix visiting physreg dest users when folding immediate copies 2020-08-10 13:46:51 -04:00
fold-imm-f16-f32.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
fold-immediate-operand-shrink-with-carry.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
fold-immediate-operand-shrink.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
fold-immediate-output-mods.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
fold-implicit-operand.mir
fold-multiple.mir
fold-operands-order.mir
fold-operands-remove-m0-redef.mir
fold-over-exec.mir
fold-readlane.mir
fold-reload-into-exec.mir AMDGPU: Remove SGPRSpillVGPRDefinedSet hack 2020-12-16 21:33:35 -05:00
fold-reload-into-m0.mir AMDGPU: Remove SGPRSpillVGPRDefinedSet hack 2020-12-16 21:33:35 -05:00
fold-sgpr-copy.mir
fold-sgpr-multi-imm.mir AMDGPU: Fix using unencodable instructions in tests 2020-06-04 16:50:19 -04:00
fold-vgpr-copy.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
fold_16bit_imm.mir CodeGen: Require SSA to run PeepholeOptimizer 2020-09-11 18:03:04 -04:00
fold_acc_copy_into_valu.mir
force-alwaysinline-lds-global-address-codegen.ll
force-alwaysinline-lds-global-address.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fp-atomic-to-s_denormmode.mir [AMDGPU] Add default 1 glc operand to rtn atomics 2020-11-05 10:41:59 -08:00
fp-classify.ll
fp16_to_fp32.ll
fp16_to_fp64.ll
fp32_to_fp16.ll
fp_to_sint.f64.ll
fp_to_sint.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fp_to_uint.f64.ll
fp_to_uint.ll Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC" 2020-05-22 05:36:15 -06:00
fpext-free.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fpext.f16.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fpext.ll
fpow.ll [AMDGPU] Remove dubious logic in bidirectional list scheduler 2020-02-28 21:35:34 +00:00
fptosi.f16.ll AMDGPU: Simplify f16 to i64 custom lowering 2020-07-22 10:32:14 +02:00
fptoui.f16.ll AMDGPU: Simplify f16 to i64 custom lowering 2020-07-22 10:32:14 +02:00
fptrunc.f16.ll [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed 2021-01-04 14:44:10 -06:00
fptrunc.ll AMDGPU: Fix some incorrect FUNC-LABEL checks 2020-02-26 09:43:13 +00:00
fract.f64.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fract.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
frame-index-elimination.ll [AMDGPU] Folding of FI operand with flat scratch 2020-12-22 10:48:04 -08:00
frame-lowering-entry-all-sgpr-used.mir [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions 2020-03-19 15:35:16 -04:00
frame-lowering-fp-adjusted.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
frem.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fshl.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fshr.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fsqrt.f64.ll
fsqrt.ll AMDGPU/EG,CM: Implement fsqrt using recip(rsqrt(x)) instead of x * rsqrt(x) 2020-02-05 00:24:07 -05:00
fsub.f16.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fsub.ll
fsub64.ll
ftrunc.f64.ll
ftrunc.ll
function-args.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
function-call-relocs.ll [AMDGPU] Fix offset for REL32_HI relocs 2020-09-02 10:55:55 +01:00
function-returns.ll OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
gds-atomic.ll
gep-address-space.ll
gfx-callable-argument-types.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
gfx-callable-preserved-registers.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
gfx10-vop-literal.ll AMDGPU: Fix some more incorrect check lines 2020-02-26 14:37:22 +00:00
gfx902-without-xnack.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
global-atomics-fp.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
global-constant.ll [AMDGPU] Fix offset for REL32_HI relocs 2020-09-02 10:55:55 +01:00
global-directive.ll
global-extload-i16.ll
global-saddr-atomics.gfx908.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
global-saddr-atomics.gfx1030.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
global-saddr-atomics.ll [AMDGPU] Avoid inserting noops during scheduling 2020-10-20 17:11:36 -07:00
global-saddr-load.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
global-saddr-store.ll AMDGPU: Match global saddr addressing mode 2020-08-17 15:28:14 -04:00
global-smrd-unknown.ll
global-variable-relocs.ll [AMDGPU] Fix offset for REL32_HI relocs 2020-09-02 10:55:55 +01:00
global_atomics.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
global_atomics_i64.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
global_smrd.ll [amdgpu] Enable use of AA during codegen. 2020-10-27 09:46:23 -04:00
global_smrd_cfg.ll [AA] Split up LocationSize::unknown() 2020-11-26 18:39:55 +01:00
greedy-broken-ssa-verifier-error.mir RegAlloc: Clear isSSA 2020-10-28 12:02:16 -04:00
gv-const-addrspace.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
gv-offset-folding.ll
gws-hazards.mir [AMDGPU] Remove gds operand from ds_gws_* MachineInstrs 2020-10-29 15:04:23 +00:00
half.ll [AMDGPU] Don't cluster stores 2020-09-14 13:40:17 +01:00
hard-clauses.mir [AMDGPU] Fix assertion failure in SIInsertHardClauses 2020-05-15 15:49:52 +01:00
hazard-buffer-store-v-interp.mir [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
hazard-hidden-bundle.mir [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
hazard-in-bundle.mir [AMDGPU] Fix inserting combined s_nop in bundles 2020-10-28 14:34:04 -07:00
hazard-inlineasm.mir
hazard-kill.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
hazard-pass-ordering.mir [AMDGPU] Run hazard recognizer pass later 2020-10-16 12:15:51 -07:00
hazard-recognizer-meta-insts.mir AMDGPU: Skip all meta instructions in hazard recognizer 2020-09-09 19:45:40 -04:00
hazard.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
hip.extern.shared.array.ll [amdgpu] Add codegen support for HIP dynamic shared memory. 2020-08-20 21:29:18 -04:00
hoist-cond.ll Resubmit: [AMDGPU] Invert the handling of skip insertion. 2020-01-22 13:18:32 +09:00
hsa-default-device.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
hsa-fp-mode.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
hsa-func-align.ll [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
hsa-func.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
hsa-globals.ll [AMDGPU] Corrected directive to use for ELF weak refs 2020-09-16 18:51:26 +03:00
hsa-group-segment.ll
hsa-metadata-deduce-ro-arg-v3.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
hsa-metadata-deduce-ro-arg.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
hsa-metadata-enqueue-kernel-v3.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
hsa-metadata-enqueue-kernel.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
hsa-metadata-from-llvm-ir-full-v3.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
hsa-metadata-from-llvm-ir-full.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
hsa-metadata-hidden-args-v3.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
hsa-metadata-hidden-args.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
hsa-metadata-hostcall-absent-v3.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
hsa-metadata-hostcall-absent.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
hsa-metadata-hostcall-present-v3.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
hsa-metadata-hostcall-present.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
hsa-metadata-images-v3.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
hsa-metadata-images.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
hsa-metadata-invalid-ocl-version-1-v3.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
hsa-metadata-invalid-ocl-version-1.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
hsa-metadata-invalid-ocl-version-2-v3.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
hsa-metadata-invalid-ocl-version-2.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
hsa-metadata-invalid-ocl-version-3-v3.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
hsa-metadata-invalid-ocl-version-3.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
hsa-metadata-kernel-code-props-v3.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
hsa-metadata-kernel-code-props.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
hsa-metadata-wavefrontsize.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
hsa-note-no-func.ll [AMDGPU] Add gfx1033 target 2020-11-03 16:27:48 +00:00
hsa.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
huge-number-operand-folds.mir AMDGPU: Fix failures from overflowing uint8_t number of operands 2020-07-23 15:39:33 -04:00
huge-private-buffer.ll
i1-copies-rpo.mir
i1-copy-from-loop.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
i1-copy-implicit-def.ll
i1-copy-phi-uniform-branch.ll [AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU. 2020-04-06 09:05:58 -04:00
i1-copy-phi.ll
i1_copy_phi_with_phi_incoming_value.mir AMDGPU: Fix using unencodable instructions in tests 2020-06-04 16:50:19 -04:00
i8-to-double-to-float.ll
icmp-select-sete-reverse-args.ll
icmp.i16.ll
icmp64.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
idiv-licm.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
idot2.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
idot4s.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
idot4u.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
idot8s.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
idot8u.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
illegal-sgpr-to-vgpr-copy.ll [llvm] Fix missing FileCheck directive colons 2020-04-06 09:59:08 -06:00
image-attributes.ll
image-load-d16-tfe.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
image-resource-id.ll
image-sample-waterfall.ll AMDGPU: Implement waterfall loop for MIMG instructions with 256-bit SRsrc 2020-08-18 16:27:36 -07:00
image-schedule.ll
image_ls_mipmap_zero.ll
img-nouse-adjust.ll
imm.ll [AMDGPU] Regenerate immediate constant tests 2020-02-19 18:58:44 +00:00
imm16.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
immv216.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
implicit-def-muse.ll
indirect-addressing-si-gfx9.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
indirect-addressing-si-noopt.ll
indirect-addressing-si-pregfx9.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
indirect-addressing-si.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
indirect-addressing-term.ll [AMDGPU] Add new pseudos for indirect addressing with VGPR Indexing 2020-12-08 12:24:12 -08:00
indirect-call.ll [AMDGPU] Add amdgpu_gfx calling convention 2020-11-09 16:51:44 +01:00
indirect-private-64.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
infer-addrpace-pipeline.ll [NewPM] Port infer-address-spaces 2020-12-28 19:58:12 -08:00
infer-uniform-load-shader.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
infinite-loop-evergreen.ll
infinite-loop.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
inline-asm.ll AMDGPU: Analyze divergence of inline asm 2020-02-03 12:42:16 -08:00
inline-attr.ll AMDGPU: Stop setting attributes based on TargetOptions 2020-03-27 13:13:43 -07:00
inline-calls.ll
inline-constraints.ll [AMDGPU][CODEGEN] Added support of new inline assembler constraints 2020-07-02 17:20:15 +03:00
inline-maxbb.ll
inlineasm-16.ll
inlineasm-illegal-type.ll
inlineasm-packed.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
input-mods.ll
insert-branch-w32.mir [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
insert-skip-from-vcc.mir [AMDGPU] Translate s_and/s_andn2 to s_mov in vcc optimisation 2020-07-17 11:48:57 +09:00
insert-skips-flat-vmem.mir Resubmit: [AMDGPU] Invert the handling of skip insertion. 2020-01-22 13:18:32 +09:00
insert-skips-gws.mir [AMDGPU] Remove gds operand from ds_gws_* MachineInstrs 2020-10-29 15:04:23 +00:00
insert-skips-ignored-insts.mir Resubmit: [AMDGPU] Invert the handling of skip insertion. 2020-01-22 13:18:32 +09:00
insert-skips-kill-uncond.mir [AMDGPU] Unify early PS termination blocks 2020-07-03 09:58:05 +09:00
insert-subvector-unused-scratch.ll [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag 2020-08-21 12:26:31 +02:00
insert-waitcnts-callee.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
insert-waitcnts-exp.mir
insert_subreg.ll
insert_vector_dynelt.ll [AMDGPU] Make bfi patterns divergence-aware 2020-09-28 10:16:51 +01:00
insert_vector_elt.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
insert_vector_elt.v2i16.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
insert_vector_elt.v2i16.subtest-nosaddr.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
insert_vector_elt.v2i16.subtest-saddr.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
inserted-wait-states.mir [AMDGPU] Allow some modifiers on VOP3B instructions 2020-10-28 21:54:14 +00:00
internalize.ll [NewPM][AMDGPU] Run InternalizePass when -amdgpu-internalize-symbols 2021-01-04 11:34:40 -08:00
invalid-addrspacecast.ll AMDGPU: Lower addrspacecast to 32-bit constant 2020-05-08 10:46:00 -04:00
invalid-alloca.ll Infer alignment of unmarked loads in IR/bitcode parsing. 2020-05-14 13:03:50 -07:00
invariant-load-no-alias-store.ll
invert-br-undef-vcc.mir
ipra-regmask.ll [AMDGPU] Introduce more scratch registers in the ABI. 2020-05-05 23:02:58 +05:30
ipra.ll [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions 2020-03-19 15:35:16 -04:00
jump-address.ll
kcache-fold.ll
kernarg-stack-alignment.ll
kernel-args.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
kernel-argument-dag-lowering.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
kill-infinite-loop.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
known-never-nan.ll
known-never-snan.ll [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed 2021-01-04 14:44:10 -06:00
knownbits-recursion.ll
large-alloca-compute.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
large-alloca-graphics.ll [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions 2020-03-19 15:35:16 -04:00
large-constant-initializer.ll
large-work-group-promote-alloca.ll
lcssa-optnone.ll
lds-alignment.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
lds-bounds.ll AMDGPU: Fix some more incorrect check lines 2020-02-26 14:37:22 +00:00
lds-branch-vmem-hazard.mir
lds-global-non-entry-func.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
lds-initializer.ll MCContext::reportError: don't call report_fatal_error 2020-12-20 23:23:12 -08:00
lds-m0-init-in-loop.ll
lds-misaligned-bug.ll [AMDGPU] Resolve issues when picking between ds_read/write and ds_read2/write2 2020-12-10 12:40:49 +01:00
lds-oqap-crash.ll
lds-output-queue.ll
lds-relocs.ll [llvm-readobj] - For SHT_REL relocations, don't display an addend. 2020-12-14 12:03:00 +03:00
lds-size.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
lds-zero-initializer.ll MCContext::reportError: don't call report_fatal_error 2020-12-20 23:23:12 -08:00
lds_atomic_f32.ll [AMDGPU] Make ds fp atomics overloadable 2020-09-23 11:39:50 -07:00
legalize-fp-load-invariant.ll
legalizedag-bug-expand-setcc.ll
limit-coalesce.mir
lit.local.cfg
literals.ll
liveness.mir
llvm.amdgcn.alignb.ll
llvm.amdgcn.atomic.csub.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
llvm.amdgcn.atomic.dec.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
llvm.amdgcn.atomic.fadd.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
llvm.amdgcn.atomic.inc.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
llvm.amdgcn.ballot.i32.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.ballot.i64.ll [AMDGPU][GlobalISel] Select llvm.amdgcn.ballot 2020-07-13 12:14:43 +02:00
llvm.amdgcn.buffer.atomic.ll [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics 2020-07-17 11:02:13 +01:00
llvm.amdgcn.buffer.load.dwordx3.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
llvm.amdgcn.buffer.load.format.d16.ll [AMDGPU] Add v3f16/v3i16 support to SDag 2020-09-16 17:20:27 +02:00
llvm.amdgcn.buffer.load.format.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
llvm.amdgcn.buffer.load.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
llvm.amdgcn.buffer.store.dwordx3.ll
llvm.amdgcn.buffer.store.format.d16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.buffer.store.format.ll AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests 2021-01-06 11:37:00 -05:00
llvm.amdgcn.buffer.store.ll
llvm.amdgcn.buffer.wbinvl1.ll
llvm.amdgcn.buffer.wbinvl1.sc.ll
llvm.amdgcn.buffer.wbinvl1.vol.ll AMDGPU: Remove mayLoad/mayStore from some side effecting intrinsics 2020-06-18 14:12:19 -04:00
llvm.amdgcn.class.f16.ll
llvm.amdgcn.class.ll
llvm.amdgcn.cos.f16.ll
llvm.amdgcn.cos.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.cubeid.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.cubema.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.cubesc.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.cubetc.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.cvt.pk.i16.ll
llvm.amdgcn.cvt.pk.u16.ll
llvm.amdgcn.cvt.pknorm.i16.ll
llvm.amdgcn.cvt.pknorm.u16.ll
llvm.amdgcn.cvt.pkrtz.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.dispatch.id.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
llvm.amdgcn.dispatch.ptr.ll [amdgpu] Add the late codegen preparation pass. 2020-10-27 14:07:59 -04:00
llvm.amdgcn.div.fixup.f16.ll
llvm.amdgcn.div.fixup.ll
llvm.amdgcn.div.fmas.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
llvm.amdgcn.div.scale.ll [AMDGPU] Allow some modifiers on VOP3B instructions 2020-10-28 21:54:14 +00:00
llvm.amdgcn.ds.append.ll AMDGPU/GlobalISel: Fix not constraining ds_append/consume operands 2020-07-26 10:17:36 -04:00
llvm.amdgcn.ds.bpermute.ll AMDGPU: Fix some incorrect FUNC-LABEL checks 2020-02-26 09:43:13 +00:00
llvm.amdgcn.ds.consume.ll AMDGPU/GlobalISel: Fix not constraining ds_append/consume operands 2020-07-26 10:17:36 -04:00
llvm.amdgcn.ds.gws.barrier-fastregalloc.ll [FastRA] Fix handling of bundled MIs 2020-12-21 02:10:55 -05:00
llvm.amdgcn.ds.gws.barrier.ll [AMDGPU] Remove gds operand from ds_gws_* MachineInstrs 2020-10-29 15:04:23 +00:00
llvm.amdgcn.ds.gws.init.ll AMDGPU/GlobalISel: Select DS GWS intrinsics 2020-01-16 11:25:10 -05:00
llvm.amdgcn.ds.gws.sema.br.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.ds.gws.sema.p.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.ds.gws.sema.release.all.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.ds.gws.sema.v.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.ds.ordered.add.gfx10.ll AMDGPU: Fix some incorrect FUNC-LABEL checks 2020-02-26 09:43:13 +00:00
llvm.amdgcn.ds.ordered.add.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
llvm.amdgcn.ds.ordered.swap.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
llvm.amdgcn.ds.permute.ll
llvm.amdgcn.ds.swizzle.ll AMDGPU: Fix some incorrect FUNC-LABEL checks 2020-02-26 09:43:13 +00:00
llvm.amdgcn.exp.compr.ll
llvm.amdgcn.exp.ll [AMDGPU] Fix scheduling of exp pos4 2020-11-12 19:57:14 +00:00
llvm.amdgcn.exp.prim.ll
llvm.amdgcn.fcmp.ll
llvm.amdgcn.fdiv.fast.ll
llvm.amdgcn.fdot2.ll
llvm.amdgcn.fma.legacy.ll [AMDGPU] Handle v_fmac_legacy_f32 in SIFoldOperands 2021-01-05 11:55:33 +00:00
llvm.amdgcn.fmad.ftz.f16.ll AMDGPU: Remove denormal subtarget features 2020-04-02 17:17:12 -04:00
llvm.amdgcn.fmad.ftz.ll [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed 2021-01-04 14:44:10 -06:00
llvm.amdgcn.fmed3.f16.ll
llvm.amdgcn.fmed3.ll
llvm.amdgcn.fmul.legacy.ll [AMDGPU] Only enable mad/mac legacy f32 patterns if denormals may be flushed 2020-10-09 17:08:38 +01:00
llvm.amdgcn.fract.f16.ll
llvm.amdgcn.fract.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.frexp.exp.f16.ll
llvm.amdgcn.frexp.exp.ll
llvm.amdgcn.frexp.mant.f16.ll
llvm.amdgcn.frexp.mant.ll
llvm.amdgcn.groupstaticsize.ll AMDGPU/GlobalISel: Select llvm.amdgcn.groupstaticsize 2020-08-18 09:28:01 -04:00
llvm.amdgcn.icmp.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
llvm.amdgcn.image.a16.dim.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.a16.encode.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.atomic.dim.ll AMDGPU: Add/Fix tests for image atomic intrinsic. 2020-03-05 12:18:15 -05:00
llvm.amdgcn.image.d16.dim.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.image.dim.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.gather4.a16.dim.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.gather4.d16.dim.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.image.gather4.dim.ll [AMDGPU] Use v3f32 type in image instructions 2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.gather4.o.dim.ll [AMDGPU] Use v3f32 type in image instructions 2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.getlod.dim.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
llvm.amdgcn.image.load.a16.d16.ll [AMDGPU] Add a16 feature to gfx10 2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.load.a16.ll [AMDGPU] Add a16 feature to gfx10 2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.msaa.load.ll [AMDGPU] Add gfx1030 target 2020-06-15 16:18:05 -07:00
llvm.amdgcn.image.nsa.ll [AMDGPU] Use v3f32 type in image instructions 2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.sample.a16.dim.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.sample.d16.dim.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.sample.dim.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.sample.g16.encode.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.sample.g16.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.sample.ltolz.ll [AMDGPU] Use v3f32 type in image instructions 2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.sample.o.dim.ll [AMDGPU] Use v3f32 type in image instructions 2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.store.a16.d16.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.store.a16.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
llvm.amdgcn.implicit.buffer.ptr.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
llvm.amdgcn.implicitarg.ptr.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
llvm.amdgcn.init.exec.ll
llvm.amdgcn.init.exec.wave32.ll
llvm.amdgcn.interp.f16.ll
llvm.amdgcn.interp.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.intersect_ray.ll [AMDGPU] gfx1030 RT support 2020-09-16 11:40:58 -07:00
llvm.amdgcn.is.private.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
llvm.amdgcn.is.shared.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
llvm.amdgcn.kernarg.segment.ptr.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
llvm.amdgcn.kill.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
llvm.amdgcn.ldexp.f16.ll
llvm.amdgcn.ldexp.ll
llvm.amdgcn.lerp.ll
llvm.amdgcn.log.clamp.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.mbcnt.ll
llvm.amdgcn.mfma.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
llvm.amdgcn.mov.dpp.ll [AMDGPU] Add Reset function to GCNHazardRecognizer 2020-10-28 16:32:32 -07:00
llvm.amdgcn.mov.dpp8.ll
llvm.amdgcn.mqsad.pk.u16.u8.ll
llvm.amdgcn.mqsad.u32.u8.ll
llvm.amdgcn.msad.u8.ll
llvm.amdgcn.mul.i24.ll
llvm.amdgcn.mul.u24.ll
llvm.amdgcn.permlane.ll AMDGPU/GlobalISel: Select permlane16/permlanex16 2020-01-29 17:55:31 -05:00
llvm.amdgcn.ps.live.ll [AMDGPU] Move WQM Pass after MI Scheduler 2020-10-27 10:25:53 +09:00
llvm.amdgcn.qsad.pk.u16.u8.ll
llvm.amdgcn.queue.ptr.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
llvm.amdgcn.raw.buffer.atomic.fadd.ll [AMDGPU] Unify intrinsic ret/nortn interface 2020-09-15 15:26:42 -07:00
llvm.amdgcn.raw.buffer.atomic.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.raw.buffer.load.format.d16.ll [AMDGPU] Add v3f16/v3i16 support to SDag 2020-09-16 17:20:27 +02:00
llvm.amdgcn.raw.buffer.load.format.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.raw.buffer.load.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.raw.buffer.store.format.d16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.raw.buffer.store.format.ll
llvm.amdgcn.raw.buffer.store.ll
llvm.amdgcn.raw.tbuffer.load.d16.ll [AMDGPU] Add v3f16/v3i16 support to SDag 2020-09-16 17:20:27 +02:00
llvm.amdgcn.raw.tbuffer.load.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
llvm.amdgcn.raw.tbuffer.store.d16.ll [AMDGPU] Add v3f16/v3i16 support to SDag 2020-09-16 17:20:27 +02:00
llvm.amdgcn.raw.tbuffer.store.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.rcp.f16.ll
llvm.amdgcn.rcp.legacy.ll
llvm.amdgcn.rcp.ll AMDGPU: Remove denormal subtarget features 2020-04-02 17:17:12 -04:00
llvm.amdgcn.readfirstlane.ll
llvm.amdgcn.readlane.ll
llvm.amdgcn.rsq.clamp.ll
llvm.amdgcn.rsq.f16.ll
llvm.amdgcn.rsq.legacy.ll
llvm.amdgcn.rsq.ll
llvm.amdgcn.s.barrier.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.s.buffer.load.ll AMDGPU: Fix broken check lines 2020-04-02 18:52:49 -04:00
llvm.amdgcn.s.dcache.inv.ll
llvm.amdgcn.s.dcache.inv.vol.ll
llvm.amdgcn.s.dcache.wb.ll
llvm.amdgcn.s.dcache.wb.vol.ll
llvm.amdgcn.s.decperflevel.ll
llvm.amdgcn.s.get.waveid.in.workgroup.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
llvm.amdgcn.s.getpc.ll
llvm.amdgcn.s.getreg.ll AMDGPU/GlobalISel: Fix selecting llvm.amdgcn.s.getreg 2020-07-28 21:34:50 -04:00
llvm.amdgcn.s.incperflevel.ll
llvm.amdgcn.s.memrealtime.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.s.memtime.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.s.setreg.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.s.sleep.ll
llvm.amdgcn.s.waitcnt.ll
llvm.amdgcn.sad.hi.u8.ll
llvm.amdgcn.sad.u8.ll
llvm.amdgcn.sad.u16.ll
llvm.amdgcn.sbfe.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.sdot2.ll
llvm.amdgcn.sdot4.ll [AMDGPU] gfx1031 target 2020-08-05 12:36:26 -07:00
llvm.amdgcn.sdot8.ll [AMDGPU] gfx1031 target 2020-08-05 12:36:26 -07:00
llvm.amdgcn.sendmsg.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.set.inactive.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.sffbh.ll AMDGPU: Fix some incorrect FUNC-LABEL checks 2020-02-26 09:43:13 +00:00
llvm.amdgcn.sin.f16.ll
llvm.amdgcn.sin.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.softwqm.ll [AMDGPU] Move WQM Pass after MI Scheduler 2020-10-27 10:25:53 +09:00
llvm.amdgcn.sqrt.f16.ll AMDGPU: Add llvm.amdgcn.sqrt intrinsic 2020-06-26 15:07:07 -04:00
llvm.amdgcn.sqrt.ll AMDGPU: Add llvm.amdgcn.sqrt intrinsic 2020-06-26 15:07:07 -04:00
llvm.amdgcn.struct.buffer.atomic.fadd.ll [AMDGPU] Unify intrinsic ret/nortn interface 2020-09-15 15:26:42 -07:00
llvm.amdgcn.struct.buffer.atomic.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.buffer.load.format.d16.ll [AMDGPU] Add v3f16/v3i16 support to SDag 2020-09-16 17:20:27 +02:00
llvm.amdgcn.struct.buffer.load.format.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.buffer.load.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.buffer.store.format.d16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.buffer.store.format.ll [AMDGPU] Allow struct.buffer.*.format intrinsics to accept i32 2020-03-11 08:20:32 +09:00
llvm.amdgcn.struct.buffer.store.ll
llvm.amdgcn.struct.tbuffer.load.d16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.tbuffer.load.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
llvm.amdgcn.struct.tbuffer.store.d16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.tbuffer.store.ll [AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier 2020-07-24 16:41:03 +03:00
llvm.amdgcn.tbuffer.load.d16.ll AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests 2021-01-06 11:37:00 -05:00
llvm.amdgcn.tbuffer.load.dwordx3.ll AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests 2021-01-06 11:37:00 -05:00
llvm.amdgcn.tbuffer.load.ll AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests 2021-01-06 11:37:00 -05:00
llvm.amdgcn.tbuffer.store.d16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.tbuffer.store.dwordx3.ll AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests 2021-01-06 11:37:00 -05:00
llvm.amdgcn.tbuffer.store.ll AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests 2021-01-06 11:37:00 -05:00
llvm.amdgcn.trig.preop.ll
llvm.amdgcn.ubfe.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.udot2.ll
llvm.amdgcn.udot4.ll
llvm.amdgcn.udot8.ll
llvm.amdgcn.unreachable.ll
llvm.amdgcn.update.dpp.ll [AMDGPU] Avoid inserting noops during scheduling 2020-10-20 17:11:36 -07:00
llvm.amdgcn.wave.barrier.ll
llvm.amdgcn.wavefrontsize.ll [NewPM][AMDGPU] Pass TargetMachine to AMDGPUSimplifyLibCallsPass 2021-01-04 13:48:09 -08:00
llvm.amdgcn.workgroup.id.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.workitem.id.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.wqm.vote.ll AMDGPU/GlobalISel: Select llvm.amdgcn.wqm.vote 2020-01-07 10:15:29 -05:00
llvm.amdgcn.writelane.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.ceil.f16.ll
llvm.cos.f16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.cos.ll
llvm.dbg.value.ll
llvm.exp2.f16.ll
llvm.exp2.ll
llvm.floor.f16.ll
llvm.fma.f16.ll [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics 2020-07-17 11:02:13 +01:00
llvm.fmuladd.f16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.log.f16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.log.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.log2.f16.ll
llvm.log2.ll
llvm.log10.f16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.log10.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.maxnum.f16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.memcpy.ll [ANDGPU] getMemOperandsWithOffset: support BUF non-stack-access instructions with resource but no vaddr 2020-02-03 22:49:30 +00:00
llvm.minnum.f16.ll [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics 2020-07-17 11:02:13 +01:00
llvm.mulo.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.pow.ll
llvm.powi.ll AMDGPU: Fix promoting f16 fpowi with legal f16 2020-07-17 11:29:05 -04:00
llvm.r600.cube.ll
llvm.r600.dot4.ll
llvm.r600.group.barrier.ll
llvm.r600.read.local.size.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.r600.recipsqrt.clamped.ll
llvm.r600.recipsqrt.ieee.ll
llvm.r600.tex.ll
llvm.rint.f16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.rint.f64.ll [llvm] Fix missing FileCheck directive colons 2020-04-06 09:59:08 -06:00
llvm.rint.ll
llvm.round.f64.ll [NFC][Test] Format the test with script update_llc_test_checks.py 2020-08-07 10:22:38 +00:00
llvm.round.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.sin.f16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.sin.ll [AMDGPU] Propagate fast-math flags when lowering FSIN and FCOS 2020-05-31 05:21:55 +01:00
llvm.sqrt.f16.ll
llvm.trunc.f16.ll
lo16-32bit-physreg-copy.mir [AMDGPU] fix copies between 32 and 16 bit 2020-05-04 08:54:22 -07:00
lo16-hi16-illegal-copy.mir [AMDGPU] Drop 16 bit subreg suffixes on print 2020-05-06 08:14:10 -07:00
lo16-hi16-physreg-copy.mir [AMDGPU] copyPhysReg() for 16 bit SGPR subregs 2020-04-17 11:59:39 -07:00
lo16-lo16-physreg-copy-agpr.mir [AMDGPU] Define AGPR subregs 2020-04-28 15:30:43 -07:00
lo16-lo16-physreg-copy-sgpr.mir [AMDGPU] copyPhysReg() for 16 bit SGPR subregs 2020-04-17 11:59:39 -07:00
load-constant-f32.ll
load-constant-f64.ll
load-constant-i1.ll
load-constant-i8.ll
load-constant-i16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
load-constant-i32.ll
load-constant-i64.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
load-global-f32.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
load-global-f64.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
load-global-i1.ll
load-global-i8.ll
load-global-i16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
load-global-i32.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
load-global-i64.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
load-hi16.ll OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00
load-input-fold.ll
load-lo16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
load-local-f32-no-ds128.ll
load-local-f32.ll [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag 2020-08-21 12:26:31 +02:00
load-local-f64.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
load-local-i1.ll
load-local-i8.ll [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag 2020-08-21 12:26:31 +02:00
load-local-i16.ll [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag 2020-08-21 12:26:31 +02:00
load-local-i32.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
load-local-i64.ll AMDGPU: Use 128-bit DS operations by default 2020-04-02 17:17:47 -04:00
load-local-redundant-copies.ll [AMDGPU] Prefer SplitVectorLoad/Store over expandUnalignedLoad/Store 2020-10-08 10:17:15 +02:00
load-local.96.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
load-local.128.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
load-select-ptr.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
load-weird-sizes.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
local-64.ll AMDGPU: Use 128-bit DS operations by default 2020-04-02 17:17:47 -04:00
local-atomics-fp.ll
local-atomics.ll
local-atomics64.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
local-memory.amdgcn.ll [AMDGPU] Don't cluster stores 2020-09-14 13:40:17 +01:00
local-memory.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
local-memory.r600.ll
local-stack-alloc-block-sp-reference.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
local-stack-slot-offset.ll
loop-address.ll
loop-idiom.ll [BasicAA] Rename deprecated -basicaa to -basic-aa 2020-06-26 20:41:37 -07:00
loop-prefetch.ll [AMDGPU] Add gfx1030 target 2020-06-15 16:18:05 -07:00
loop_break.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
loop_exit_with_xor.ll AMDGPU: Update tests to use modern buffer intrinsics 2020-01-16 13:49:43 -05:00
loop_header_nopred.mir
lower-control-flow-other-terminators.mir [AMDGPU] Remove fix up operand from SI_ELSE 2020-10-20 19:15:21 +09:00
lower-kernargs.ll Use unary CreateShuffleVector if possible 2020-12-30 22:36:08 +09:00
lower-mem-intrinsics-threshold.ll AMDGPU: Add flag to control mem intrinsic expansion 2020-02-03 14:26:01 -08:00
lower-mem-intrinsics.ll AMDGPU: Implement getMemcpyLoopLoweringType 2020-03-30 22:21:01 +01:00
lower-range-metadata-intrinsic-call.ll
lower-term-opcodes.mir [AMDGPU] Fix lowering of S_MOV_{B32,B64}_term 2020-11-10 12:16:31 +09:00
lshl64-to-32.ll [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics 2020-07-17 11:02:13 +01:00
lshr.v2i16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
machine-cse-commute-target-flags.mir AMDGPU: Support commuting register and global operand 2020-07-01 13:59:13 -04:00
machinelicm-convergent.mir Prevent LICM and machineLICM from hoisting convergent operations 2020-11-06 10:26:39 -08:00
macro-fusion-cluster-vcc-uses.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
mad-combine.ll [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed 2021-01-04 14:44:10 -06:00
mad-mix-hi.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
mad-mix-lo.ll AMDGPU: Remove denormal subtarget features 2020-04-02 17:17:12 -04:00
mad-mix.ll [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed 2021-01-04 14:44:10 -06:00
mad.u16.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
mad24-get-global-id.ll
mad_64_32.ll [AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler" 2020-02-25 14:51:42 +00:00
mad_int24.ll
mad_uint24.ll Fix 64-bit copy to SCC 2020-08-09 20:50:30 +02:00
madak-inline-constant.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
madak.ll AMDGPU: Match global saddr addressing mode 2020-08-17 15:28:14 -04:00
madmk.ll [AMDGPU] Add gfx1030 target 2020-06-15 16:18:05 -07:00
mai-hazards.mir [HazardRec] Allow inserting multiple wait-states simultaneously 2020-10-20 17:03:47 -07:00
mai-inline.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
max-literals.ll
max-sgprs.ll
max.i16.ll [AMDGPU] Optimize waitcnt insertion for flat memory operations 2020-10-20 22:55:12 +00:00
max.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
max3.ll
mcp-overlap-after-propagation.mir [AMDGPU] Add a16 feature to gfx10 2020-02-10 09:04:23 +01:00
med3-no-simplify.ll
mem-builtins.ll [AMDGPU] Fix offset for REL32_HI relocs 2020-09-02 10:55:55 +01:00
memcpy-fixed-align.ll [AMDGPU] Enable multi-dword flat scratch load/stores 2020-11-12 13:38:56 -08:00
memcpy-inline-fails.ll Revert "Disable memcpy-inline-fails.ll for windows" 2020-03-16 16:03:39 +01:00
memory-legalizer-atomic-insert-end.mir llc: Change behavior of -mcpu with existing attribute 2020-01-07 10:10:25 -05:00
memory-legalizer-fence.ll [AMDGPU] Use MUBUF instructions for global address space access 2020-12-24 10:13:04 +00:00
memory-legalizer-flat-agent.ll [AMDGPU] Extend and reorganize memory legalizer tests 2020-12-03 19:36:33 +00:00
memory-legalizer-flat-nontemporal.ll [AMDGPU] Extend and reorganize memory legalizer tests 2020-12-03 19:36:33 +00:00
memory-legalizer-flat-singlethread.ll [AMDGPU] Extend and reorganize memory legalizer tests 2020-12-03 19:36:33 +00:00
memory-legalizer-flat-system.ll [AMDGPU] Extend and reorganize memory legalizer tests 2020-12-03 19:36:33 +00:00
memory-legalizer-flat-wavefront.ll [AMDGPU] Extend and reorganize memory legalizer tests 2020-12-03 19:36:33 +00:00
memory-legalizer-flat-workgroup.ll [AMDGPU] Extend and reorganize memory legalizer tests 2020-12-03 19:36:33 +00:00
memory-legalizer-global-agent.ll [AMDGPU] Use MUBUF instructions for global address space access 2020-12-24 10:13:04 +00:00
memory-legalizer-global-nontemporal.ll [AMDGPU] Use MUBUF instructions for global address space access 2020-12-24 10:13:04 +00:00
memory-legalizer-global-singlethread.ll [AMDGPU] Use MUBUF instructions for global address space access 2020-12-24 10:13:04 +00:00
memory-legalizer-global-system.ll [AMDGPU] Use MUBUF instructions for global address space access 2020-12-24 10:13:04 +00:00
memory-legalizer-global-wavefront.ll [AMDGPU] Use MUBUF instructions for global address space access 2020-12-24 10:13:04 +00:00
memory-legalizer-global-workgroup.ll [AMDGPU] Use MUBUF instructions for global address space access 2020-12-24 10:13:04 +00:00
memory-legalizer-invalid-addrspace.mir
memory-legalizer-invalid-syncscope.ll
memory-legalizer-local-agent.ll [AMDGPU] Use MUBUF instructions for global address space access 2020-12-24 10:13:04 +00:00
memory-legalizer-local-nontemporal.ll [AMDGPU] Use MUBUF instructions for global address space access 2020-12-24 10:13:04 +00:00
memory-legalizer-local-singlethread.ll [AMDGPU] Use MUBUF instructions for global address space access 2020-12-24 10:13:04 +00:00
memory-legalizer-local-system.ll [AMDGPU] Use MUBUF instructions for global address space access 2020-12-24 10:13:04 +00:00
memory-legalizer-local-wavefront.ll [AMDGPU] Use MUBUF instructions for global address space access 2020-12-24 10:13:04 +00:00
memory-legalizer-local-workgroup.ll [AMDGPU] Use MUBUF instructions for global address space access 2020-12-24 10:13:04 +00:00
memory-legalizer-local.mir
memory-legalizer-multiple-mem-operands-atomics.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
memory-legalizer-private-nontemporal.ll [AMDGPU] Use MUBUF instructions for global address space access 2020-12-24 10:13:04 +00:00
memory-legalizer-region.mir
memory-legalizer-store-infinite-loop.ll
memory_clause.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
memory_clause.mir [AMDGPU] Add default 1 glc operand to rtn atomics 2020-11-05 10:41:59 -08:00
merge-image-load-gfx10.mir SILoadStoreOptimizer: add support for GFX10 image instructions 2020-07-08 19:15:46 +01:00
merge-image-load.mir [AMDGPU] Fix formatting in MIR tests 2020-07-02 10:27:34 +01:00
merge-image-sample-gfx10.mir SILoadStoreOptimizer: add support for GFX10 image instructions 2020-07-08 19:15:46 +01:00
merge-image-sample.mir AMDGPU: Move MIMG MMO check to verifier 2020-05-29 20:58:23 -04:00
merge-load-store-physreg.mir
merge-load-store-vreg.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
merge-load-store.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
merge-m0.mir [AMDGPU] Remove gds operand from ds_gws_* MachineInstrs 2020-10-29 15:04:23 +00:00
merge-out-of-order-ldst.ll [AMDGPU] Fix crash in SILoadStoreOptimizer 2020-04-02 10:26:47 -07:00
merge-out-of-order-ldst.mir [AMDGPU] Fix crash in SILoadStoreOptimizer 2020-04-02 10:26:47 -07:00
merge-store-crash.ll AMDGPU: Convert some tests to use new buffer intrinsics 2020-07-30 10:30:43 -04:00
merge-store-usedef.ll AMDGPU: Convert some tests to use new buffer intrinsics 2020-07-30 10:30:43 -04:00
merge-stores.ll [AMDGPU] Add alignment check for v3 to v4 load type promotion 2020-11-01 12:05:34 +05:30
merge-tbuffer.mir Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC" 2020-05-22 05:36:15 -06:00
mesa3d.ll [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions 2020-03-19 15:35:16 -04:00
mesa_regression.ll
mfma-loop.ll [AMDGPU] Added label to test. NFC. 2020-04-03 11:36:32 -07:00
min.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
min3.ll
mir-print-dead-csr-fi.mir [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions 2020-03-19 15:35:16 -04:00
misched-killflags.mir [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions 2020-03-19 15:35:16 -04:00
missing-store.ll
mixed-wave32-wave64.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
mixed_wave32_wave64.ll
mode-register.mir [AMDGPU] Avoid redundant mode register writes 2020-06-24 14:11:29 +01:00
move-addr64-rsrc-dead-subreg-writes.ll
move-to-valu-atomicrmw.ll
move-to-valu-worklist.ll
movreld-bug.ll [AMDGPU] Make movreld-bug test case more robust 2020-09-11 10:25:29 +01:00
movrels-bug.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
mubuf-legalize-operands.ll Reapply "RegAllocFast: Rewrite and improve" 2020-09-30 10:35:25 -04:00
mubuf-legalize-operands.mir AMDGPU: Implement waterfall loop for MIMG instructions with 256-bit SRsrc 2020-08-18 16:27:36 -07:00
mubuf-offset-private.ll [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions 2020-03-19 15:35:16 -04:00
mubuf-shader-vgpr.ll AMDGPU: Update tests to use modern buffer intrinsics 2020-01-16 13:49:43 -05:00
mubuf.ll AMDGPU: Convert some tests to use new buffer intrinsics 2020-07-30 10:30:43 -04:00
mul.i16.ll
mul.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
mul24-pass-ordering.ll [AMDGPU] Use pseudo instructions for readlane/writelane 2020-10-29 16:00:53 +00:00
mul_int24.ll
mul_uint24-amdgcn.ll [AMDGPU] Fix bundle scheduling 2020-01-09 15:56:36 -08:00
mul_uint24-r600.ll
multi-divergent-exit-region.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
multi-dword-vgpr-spill.ll [AMDGPU] Use multi-dword flat scratch for spilling 2020-12-14 14:19:29 -08:00
multilevel-break.ll [AMDGPU] Enable structurizer workarounds by default 2020-06-09 13:14:15 +05:30
nand.ll
nested-calls.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
nested-loop-conditions.ll [AMDGPU] Fix and extend vccz workarounds 2020-11-18 15:26:06 +00:00
no-bundle-asm.ll AMDGPU: Do not bundle inline asm 2020-06-14 13:24:50 -04:00
no-hsa-graphics-shaders.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
no-initializer-constant-addrspace.ll [llvm-readobj] - For SHT_REL relocations, don't display an addend. 2020-12-14 12:03:00 +03:00
no-remat-indirect-mov.mir AMDGPU: Don't run indexing mode switches with exec = 0 2020-06-02 13:47:48 -04:00
no-shrink-extloads.ll
non-entry-alloca.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
noop-shader-O0.ll
nop-data.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
nor.ll
not-scalarize-volatile-load.ll
nsa-reassign.ll [AMDGPU] Precommit some scheduler related test updates 2020-02-28 11:20:58 +00:00
nsa-vmem-hazard.mir AMDGPU: Move MIMG MMO check to verifier 2020-05-29 20:58:23 -04:00
nullptr.ll AMDGPU: Fix wrong null value for private address space 2020-05-26 16:35:13 -04:00
occupancy-levels.ll [AMDGPU] Add occupancy level tests for GFX10.3. NFC. 2020-12-08 14:15:01 +00:00
offset-split-flat.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
offset-split-global.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
omod-nsz-flag.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
omod.ll AMDGPU: Remove denormal subtarget features 2020-04-02 17:17:12 -04:00
opencl-image-metadata.ll
opencl-printf-no-hostcall.ll
opencl-printf.ll [NewPM][AMDGPU] Port amdgpu-printf-runtime-binding 2021-01-04 12:25:50 -08:00
operand-folding.ll [AMDGPU] Add gfx1030 target 2020-06-15 16:18:05 -07:00
operand-spacing.ll
opt-pipeline.ll [AMDGPU] Actually fully update opt-pipeline.ll test to account for -loop-idiom vs -indvars switch 2020-11-25 19:39:32 +03:00
opt-sgpr-to-vgpr-copy.mir
optimize-exec-copies-extra-insts-after-copy.mir AMDGPU: Optimize copies to exec with other insts after exec def 2020-07-28 21:34:50 -04:00
optimize-exec-mask-pre-ra-loop-phi.mir AMDGPU: Check for other defs when folding conditions into s_andn2_b64 2020-07-28 16:36:23 -04:00
optimize-exec-masking-pre-ra.mir [AMDGPU] Propagate dead flag during pre-RA exec mask optimizations 2020-07-14 12:53:43 +09:00
optimize-exec-masking-strip-terminator-bits.mir AMDGPU: Don't assume there is only one terminator copy 2020-07-28 20:22:38 -04:00
optimize-if-exec-masking.mir
optimize-negated-cond-exec-masking-wave32.mir [AMDGPU] Propagate dead flag during pre-RA exec mask optimizations 2020-07-14 12:53:43 +09:00
optimize-negated-cond-exec-masking.mir [AMDGPU] Propagate dead flag during pre-RA exec mask optimizations 2020-07-14 12:53:43 +09:00
optimize-negated-cond.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
or.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
or3.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
pack.v2f16.ll AMDGPU: Fix a few more tests with old denormal subtarget features 2020-04-03 23:42:13 -04:00
pack.v2i16.ll AMDGPU: Fix a few more tests with old denormal subtarget features 2020-04-03 23:42:13 -04:00
packed-op-sel.ll [AMDGPU] Fix bundle scheduling 2020-01-09 15:56:36 -08:00
packetizer.ll
pal-userdata-regs.ll [AMDGPU] Fixed incorrect PAL metadata register naming 2020-05-21 22:13:19 +01:00
parallelandifcollapse.ll
parallelorifcollapse.ll
partial-sgpr-to-vgpr-spills.ll Reapply "RegAllocFast: Rewrite and improve" 2020-09-30 10:35:25 -04:00
partial-shift-shrink.ll
partially-dead-super-register-immediate.ll
peephole-opt-regseq-removal.mir
pei-build-spill-partial-agpr.mir [AMDGPU] Use multi-dword flat scratch for spilling 2020-12-14 14:19:29 -08:00
pei-build-spill.mir [AMDGPU] Use multi-dword flat scratch for spilling 2020-12-14 14:19:29 -08:00
pei-reg-scavenger-position.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
pei-scavenge-sgpr-carry-out.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
pei-scavenge-sgpr-gfx9.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
pei-scavenge-sgpr.mir [AMDGPU] Enable base pointer. 2020-05-17 16:13:55 +05:30
pei-scavenge-vgpr-spill.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
perfhint.ll [AMDGPU] Add some missing check prefixes and tweak test 2020-07-17 12:57:47 +01:00
permute.ll [AMDGPU] Add ISD::FSHR -> ALIGNBIT support 2020-03-12 20:16:57 +00:00
phi-elimination-assertion.mir
phi-elimination-end-cf.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
phi-vgpr-input-moveimm.mir [AMDGPU] Fix formatting in MIR tests 2020-07-02 10:27:34 +01:00
pk_max_f16_literal.ll
post-ra-sched-kill-bundle-use-inst.mir [AMDGPU] Remove gds operand from ds_gws_* MachineInstrs 2020-10-29 15:04:23 +00:00
post-ra-sched-reset.mir [AMDGPU] Add Reset function to GCNHazardRecognizer 2020-10-28 16:32:32 -07:00
postra-bundle-memops.mir AMDGPU: Move MIMG MMO check to verifier 2020-05-29 20:58:23 -04:00
postra-machine-sink.mir [AMDGPU] Fixed lane mask in test. NFC. 2020-04-15 15:26:53 -07:00
postra-norename.mir
power-sched-no-instr-sunit.mir [AMDGPU] Avoid inserting noops during scheduling 2020-10-20 17:11:36 -07:00
predicate-dp4.ll
predicates.ll
preserve-hi16.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
print-mir-custom-pseudo.ll
private-access-no-objects.ll [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions 2020-03-19 15:35:16 -04:00
private-element-size.ll [amdgpu] Enable use of AA during codegen. 2020-10-27 09:46:23 -04:00
private-memory-atomics.ll
private-memory-r600.ll
promote-alloca-addrspacecast.ll
promote-alloca-array-aggregate.ll
promote-alloca-array-allocation.ll
promote-alloca-bitcast-function.ll
promote-alloca-calling-conv.ll
promote-alloca-globals.ll
promote-alloca-invariant-markers.ll
promote-alloca-lifetime.ll
promote-alloca-mem-intrinsics.ll
promote-alloca-no-opts.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
promote-alloca-padding-size-estimate.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
promote-alloca-pointer-array.ll [AMDGPU] Fixed promote alloca with ptr/int casts 2020-06-10 11:46:57 -07:00
promote-alloca-stored-pointer-value.ll
promote-alloca-to-lds-constantexpr-use.ll AMDGPU: Account for the size of LDS globals used through constant 2020-07-29 11:40:42 -04:00
promote-alloca-to-lds-icmp.ll
promote-alloca-to-lds-phi.ll [NFC] GetUnderlyingObject -> getUnderlyingObject 2020-07-30 21:08:24 -07:00
promote-alloca-to-lds-select.ll [ValueTracking, BasicAA] Don't simplify instructions 2020-06-21 16:31:07 +02:00
promote-alloca-unhandled-intrinsic.ll
promote-alloca-vector-to-vector.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
promote-alloca-volatile.ll
promote-constOffset-to-imm-gfx10.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
promote-constOffset-to-imm.ll [AMDGPU/MemOpsCluster] Clean-up fixme's around mem ops clustering logic 2020-07-30 21:41:13 +05:30
promote-constOffset-to-imm.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
promote-vect3-load.ll [AMDGPU] Add alignment check for v3 to v4 load type promotion 2020-11-01 12:05:34 +05:30
propagate-attributes-bitcast-function.ll [AMDGPU] Fix offset for REL32_HI relocs 2020-09-02 10:55:55 +01:00
propagate-attributes-clone.ll [NewPM][AMDGPU] Port amdgpu-propagate-attributes-early/late 2021-01-04 11:53:37 -08:00
propagate-attributes-flat-work-group-size.ll [NewPM][AMDGPU] Port amdgpu-propagate-attributes-early/late 2021-01-04 11:53:37 -08:00
propagate-attributes-single-set.ll [NewPM][AMDGPU] Port amdgpu-propagate-attributes-early/late 2021-01-04 11:53:37 -08:00
ptrmask.ll DAG: Use correct pointer size for llvm.ptrmask 2020-05-18 16:46:11 -04:00
pv-packing.ll
pv.ll
r600-constant-array-fixup.ll [llvm-readobj] - For SHT_REL relocations, don't display an addend. 2020-12-14 12:03:00 +03:00
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600-legalize-umax-bug.ll
r600.add.ll
r600.alu-limits.ll
r600.amdgpu-alias-analysis.ll
r600.bitcast.ll Regenerate bitcast test for upcoming patch. 2020-02-02 18:27:44 +00:00
r600.extract-lowbits.ll
r600.func-alignment.ll
r600.global_atomics.ll
r600.private-memory.ll
r600.sub.ll
r600.work-item-intrinsics.ll
r600cfg.ll
rcp-pattern.ll [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed 2021-01-04 14:44:10 -06:00
rcp_iflag.ll AMDGPU: Remove denormal subtarget features 2020-04-02 17:17:12 -04:00
read-register-invalid-subtarget.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
read-register-invalid-type-i32.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
read-register-invalid-type-i64.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
read_register.ll AMDGPU: Adjust test so it will work with GlobalISel 2019-12-27 19:37:39 -05:00
readcyclecounter.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
readlane_exec0.mir
reassoc-scalar.ll [AMDGPU] Fix offset for REL32_HI relocs 2020-09-02 10:55:55 +01:00
reduce-build-vec-ext-to-ext-build-vec.ll
reduce-load-width-alignment.ll
reduce-saveexec.mir
reduce-store-width-alignment.ll
reduction.ll DAG: Combine extract_vector_elt of concat_vectors 2020-04-06 09:26:29 -04:00
reg-coalescer-sched-crash.ll
regbank-reassign-wave64.mir [AMDGPU] Use lowercase for subtarget feature names in RUN lines 2020-10-13 09:02:09 +01:00
regbank-reassign.mir [AMDGPU] Avoid sorting stalls in regbank-reassign 2020-08-21 11:49:41 -07:00
regcoal-subrange-join-seg.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
regcoal-subrange-join.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
regcoalesce-cannot-join-failures.mir
regcoalesce-dbg.mir
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
regcoalesce-prune.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
regcoalescing-remove-partial-redundancy-assert.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
register-count-comments.ll
rel32.ll [AMDGPU] Fix offset for REL32_HI relocs 2020-09-02 10:55:55 +01:00
remove-short-exec-branches-gpr-idx-mode.mir AMDGPU: Fix using unencodable instructions in tests 2020-06-04 16:50:19 -04:00
remove-short-exec-branches-special-instructions.mir AMDGPU: Fix missing writelane cases to skip with exec=0 2020-10-30 11:15:11 -04:00
rename-disconnected-bug.ll
rename-independent-subregs-mac-operands.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
rename-independent-subregs.mir [AMDGPU] Define 16 bit SGPR subregs 2020-04-16 10:31:39 -07:00
reorder-stores.ll AMDGPU: Use 128-bit DS operations by default 2020-04-02 17:17:47 -04:00
reqd-work-group-size.ll [NewPM][AMDGPU] Port amdgpu-lower-kernel-attributes 2020-12-29 10:26:06 -08:00
reserve-vgpr-for-sgpr-spill.ll Reapply "RegAllocFast: Rewrite and improve" 2020-09-30 10:35:25 -04:00
ret.ll
ret_jump.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
return-with-successors.mir AMDGPU: Implement getNoPreservedMask 2020-10-22 10:17:31 -04:00
returnaddress.ll AMDGPU/GlobalISel: Select llvm.returnaddress 2020-08-04 17:14:38 -04:00
rewrite-out-arguments-address-space.ll Use unary CreateShuffleVector if possible 2020-12-30 22:36:08 +09:00
rewrite-out-arguments.ll Use unary CreateShuffleVector if possible 2020-12-30 22:36:08 +09:00
rotl.i64.ll
rotl.ll [AMDGPU] should expand ROTL i16 to shifts. 2020-09-17 17:34:33 +03:00
rotr.i64.ll
rotr.ll [AMDGPU] should expand ROTL i16 to shifts. 2020-09-17 17:34:33 +03:00
rsq.ll [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed 2021-01-04 14:44:10 -06:00
rv7x0_count3.ll
s_add_co_pseudo_lowering.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
s_addk_i32.ll
s_code_end.ll [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
s_movk_i32.ll
s_mulk_i32.ll
sad.ll [EarlyCSE] Remove unnecessary operand swap. 2020-09-11 02:14:04 -04:00
saddo.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
saddsat.ll [DAG][AMDGPU][X86] Add SimplifyMultipleUseDemandedBits handling for SIGN/ZERO_EXTEND + SIGN/ZERO_EXTEND_VECTOR_INREG 2020-07-29 18:10:59 +01:00
salu-to-valu.ll [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics 2020-07-17 11:02:13 +01:00
sampler-resource-id.ll
scalar-branch-missing-and-exec.ll
scalar-store-cache-flush.mir Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
scalar_to_vector.ll [AMDGPU] Add ISD::FSHR -> ALIGNBIT support 2020-03-12 20:16:57 +00:00
scalar_to_vector_v2x16.ll
sched-assert-dead-def-subreg-use-other-subreg.mir [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics 2020-07-17 11:02:13 +01:00
sched-assert-onlydbg-value-empty-region.mir [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics 2020-07-17 11:02:13 +01:00
sched-crash-dbg-value.mir [AMDGPU] Allow some modifiers on VOP3B instructions 2020-10-28 21:54:14 +00:00
sched-handleMoveUp-subreg-def-across-subreg-def.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
sched-prefer-non-mfma.mir [AMDGPU] prefer non-mfma in post-RA schedule 2020-07-29 12:17:50 -07:00
schedule-barrier-fpmode.mir AMDGPU: Add missing test for s_denorm_mode scheduling 2020-05-28 11:07:22 -04:00
schedule-barrier.mir
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-global-loads.ll
schedule-if-2.ll
schedule-if.ll
schedule-ilp.ll
schedule-kernel-arg-loads.ll
schedule-regpressure-limit-clustering.ll [AMDGPU] Fix not rescheduling without clustering 2020-08-07 11:15:58 -07:00
schedule-regpressure-limit.ll [amdgpu] Enable use of AA during codegen. 2020-10-27 09:46:23 -04:00
schedule-regpressure-limit2.ll [amdgpu] Enable use of AA during codegen. 2020-10-27 09:46:23 -04:00
schedule-regpressure-limit3.ll [amdgpu] Enable use of AA during codegen. 2020-10-27 09:46:23 -04:00
schedule-regpressure.mir
schedule-vs-if-nested-loop-failure.ll
schedule-vs-if-nested-loop.ll
schedule-xdl-resource.ll [AMDGPU] Add XDL resource to scheduling model 2020-09-14 13:48:54 -07:00
scheduler-handle-move-bundle.mir [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
scheduler-subrange-crash.ll AMDGPU: Convert some tests to use new buffer intrinsics 2020-07-30 10:30:43 -04:00
scratch-buffer.ll [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions 2020-03-19 15:35:16 -04:00
scratch-simple.ll [llvm-readobj] - For SHT_REL relocations, don't display an addend. 2020-12-14 12:03:00 +03:00
sdiv.ll Fix 64-bit copy to SCC 2020-08-09 20:50:30 +02:00
sdiv64.ll [Sink] Optimize/simplify sink candidate finding with nearest common dominator 2020-08-30 22:51:00 -07:00
sdivrem24.ll
sdivrem64.r600.ll AMDGPU: Enable integer division bypass 2020-02-19 17:50:19 -05:00
sdwa-gfx9.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
sdwa-op64-test.ll AMDGPU: Match global saddr addressing mode 2020-08-17 15:28:14 -04:00
sdwa-ops.mir AMDGPU: Correct definitions for global saddr instructions 2020-08-15 12:11:57 -04:00
sdwa-peephole-instr-gfx10.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
sdwa-peephole-instr.mir [AMDGPU] Corrected declaration of VOPC instructions with SDWA addressing mode. 2020-11-05 11:15:50 -05:00
sdwa-peephole.ll [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics 2020-07-17 11:02:13 +01:00
sdwa-preserve.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
sdwa-scalar-ops.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
sdwa-stack.mir [AMDGPU] Inhibit SDWA if target instruction has FI 2020-08-13 11:34:28 -07:00
sdwa-vop2-64bit.mir
select-constant-cttz.ll [AMDGPU] Fix typos in performCtlz_CttzCombine() 2020-07-14 10:18:18 +01:00
select-fabs-fneg-extract-legacy.ll
select-fabs-fneg-extract.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
select-i1.ll [AMDGPU] Select s_cselect 2020-06-25 10:38:23 +02:00
select-opt.ll Fix 64-bit copy to SCC 2020-08-09 20:50:30 +02:00
select-undef.ll
select-vectors.ll Fix 64-bit copy to SCC 2020-08-09 20:50:30 +02:00
select.f16.ll [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics 2020-07-17 11:02:13 +01:00
select.ll
select64.ll Fix 64-bit copy to SCC 2020-08-09 20:50:30 +02:00
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll [FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder. 2020-08-03 10:22:25 -05:00
selectcc.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
sendmsg-m0-hazard.mir
set-dx10.ll [FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder. 2020-08-03 10:22:25 -05:00
set-gpr-idx-peephole.mir AMDGPU: Don't run indexing mode switches with exec = 0 2020-06-02 13:47:48 -04:00
setcc-equivalent.ll
setcc-fneg-constant.ll
setcc-limit-load-shrink.ll
setcc-opt.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
setcc-sext.ll
setcc.ll [Sink] Optimize/simplify sink candidate finding with nearest common dominator 2020-08-30 22:51:00 -07:00
setcc64.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
seto.ll
setuo.ll
sext-divergence-driven-isel.ll [AMDGPU] Enable SEXT divergence driven selection. 2020-03-17 17:30:11 +03:00
sext-eliminate.ll
sext-in-reg-failure-r600.ll
sext-in-reg.ll AMDGPU: Match global saddr addressing mode 2020-08-17 15:28:14 -04:00
sgpr-control-flow.ll [NFC][Test] Format the test with script update_llc_test_checks.py 2020-08-07 10:22:38 +00:00
sgpr-copy-duplicate-operand.ll
sgpr-copy-local-cse.ll [PeepholeOptimizer] Enhance the redundant COPY elimination. 2020-09-22 10:11:37 -04:00
sgpr-copy.ll [AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU. 2020-04-06 09:05:58 -04:00
sgpr-phys-copy.mir [AMDGPU] Minimize number of s_mov generated by copyPhysReg 2020-10-15 22:35:02 +09:00
sgpr-spill-partially-undef.mir AMDGPU: Remove SGPRSpillVGPRDefinedSet hack 2020-12-16 21:33:35 -05:00
sgpr-spill-wrong-stack-id.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
sgpr-spill.mir [AMDGPU] Use flat scratch instructions where available 2020-10-26 14:40:42 -07:00
sgprcopies.ll
shader-addr64-nonuniform.ll
shared-op-cycle.ll
shift-and-i64-ubfe.ll
shift-and-i128-ubfe.ll
shift-i64-opts.ll [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics 2020-07-17 11:02:13 +01:00
shift-i128.ll Revert "[AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size" 2020-07-17 12:20:37 +05:30
shift-select.ll [AMDGPU] fixed divergence driven shift operations selection 2020-01-31 20:49:56 +03:00
shl-add-to-add-shl.ll
shl.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
shl.v2i16.ll [AMDGPU] Optimize waitcnt insertion for flat memory operations 2020-10-20 22:55:12 +00:00
shl_add.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
shl_add_constant.ll AMDGPU: Fix some incorrect FUNC-LABEL checks 2020-02-26 09:43:13 +00:00
shl_add_ptr.ll [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions 2020-03-19 15:35:16 -04:00
shl_add_ptr_csub.ll AMDGPU: Handle intrinsics in performMemSDNodeCombine 2020-08-12 10:04:53 -04:00
shl_add_ptr_global.ll [AMDGPU] Unify intrinsic ret/nortn interface 2020-09-15 15:26:42 -07:00
shl_or.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
shrink-add-sub-constant.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
shrink-carry.mir AMDGPU: Fix using unencodable instructions in tests 2020-06-04 16:50:19 -04:00
shrink-instructions-flags.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
shrink-instructions-implicit-vcclo.mir [AMDGPU] Preserve vcc_lo when shrinking V_CNDMASK 2020-08-27 10:22:50 +02:00
shrink-insts-scalar-bit-ops.mir AMDGPU: Fix verifier error with undef source producing s_bitset* 2020-08-05 14:42:20 -04:00
shrink-vop3-carry-out.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
si-annotate-cf-noloop.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
si-annotate-cf-unreachable.ll
si-annotate-cf.ll [AMDGPU] Fix and extend vccz workarounds 2020-11-18 15:26:06 +00:00
si-annotate-cfg-loop-assert.ll [AMDGPU] Fix and extend vccz workarounds 2020-11-18 15:26:06 +00:00
si-annotatecfg-multiple-backedges.ll AMDGPU: Fix extra type mangling on llvm.amdgcn.if.break 2020-02-03 07:02:05 -08:00
si-fix-sgpr-copies.mir AMDGPU: Fix assert when checking for implicit operand legality 2020-12-22 20:56:24 -05:00
si-i1-copies.mir
si-instr-info-correct-implicit-operands.ll AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
si-lower-control-flow-kill.ll
si-lower-control-flow-unreachable-block.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
si-lower-control-flow.mir CodeGen: Fix livein calculation in MachineBasicBlock splitAt 2020-10-02 10:45:04 +09:00
si-lower-i1-copies.mir
si-lower-sgpr-spills.mir
si-scheduler.ll [llvm] Fix missing FileCheck directive colons 2020-04-06 09:59:08 -06:00
si-sgpr-spill.ll [AMDGPU] Avoid use of V_READLANE into EXEC in SGPR spills 2020-06-20 12:10:47 +09:00
si-spill-cf.ll
si-spill-sgpr-stack.ll [AMDGPU] Make SGPR spills exec mask agnostic 2020-06-03 12:34:26 +09:00
si-triv-disjoint-mem-access.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
si-vector-hang.ll
sibling-call.ll OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00
sign_extend.ll [AMDGPU] Add alignment check for v3 to v4 load type promotion 2020-11-01 12:05:34 +05:30
simplify-libcalls.ll [NewPM][AMDGPU] Port amdgpu-simplifylib/amdgpu-usenative 2020-12-28 10:38:51 -08:00
simplify-libcalls2.ll [NewPM][AMDGPU] Port amdgpu-simplifylib/amdgpu-usenative 2020-12-28 10:38:51 -08:00
simplifydemandedbits-recursion.ll
sint_to_fp.f64.ll Fix 64-bit copy to SCC 2020-08-09 20:50:30 +02:00
sint_to_fp.i64.ll
sint_to_fp.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
sitofp.f16.ll AMDGPU: Fix some incorrect FUNC-LABEL checks 2020-02-26 09:43:13 +00:00
skip-branch-taildup-ret.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
skip-branch-trap.ll Resubmit: [AMDGPU] Invert the handling of skip insertion. 2020-01-22 13:18:32 +09:00
skip-if-dead.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
smed3.ll
smem-no-clause-coalesced.mir
smem-war-hazard.mir [AMDGPU] Use pseudo instructions for readlane/writelane 2020-10-29 16:00:53 +00:00
sminmax.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
sminmax.v2i16.ll [AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler" 2020-02-25 14:51:42 +00:00
smrd-fold-offset.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
smrd-gfx10.ll
smrd-vccz-bug.ll [AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler" 2020-02-25 14:51:42 +00:00
smrd.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
smrd_vmem_war.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
sopk-compares.ll
speculative-execution-freecasts.ll SpeculativeExecution: fixed ingoring free execution 2020-02-20 14:45:02 +03:00
spill-agpr-partially-undef.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
spill-agpr.ll [AMDGPU] Annotate vgpr<->agpr spills in asm 2020-12-07 11:25:25 -08:00
spill-agpr.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
spill-alloc-sgpr-init-bug.ll
spill-before-exec.mir AMDGPU: Cleanup MIR test 2020-10-22 12:54:35 -04:00
spill-cfg-position.ll
spill-csr-frame-ptr-reg-copy.ll [AMDGPU] Introduce more scratch registers in the ABI. 2020-05-05 23:02:58 +05:30
spill-empty-live-interval.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
spill-m0.ll Reapply "RegAllocFast: Rewrite and improve" 2020-09-30 10:35:25 -04:00
spill-offset-calculation.ll [AMDGPU] Use multi-dword flat scratch for spilling 2020-12-14 14:19:29 -08:00
spill-reg-tuple-super-reg-use.mir AMDGPU: Remove SGPRSpillVGPRDefinedSet hack 2020-12-16 21:33:35 -05:00
spill-scavenge-offset.ll [AMDGPU] Use multi-dword flat scratch for spilling 2020-12-14 14:19:29 -08:00
spill-special-sgpr.mir [AMDGPU] Use pseudo instructions for readlane/writelane 2020-10-29 16:00:53 +00:00
spill-vgpr-to-agpr.ll [AMDGPU] Annotate vgpr<->agpr spills in asm 2020-12-07 11:25:25 -08:00
spill-wide-sgpr.ll [NFC][AMDGPU] Clean up some lit test prefixes 2020-11-11 17:12:37 +00:00
spill192.mir AMDGPU: Remove SGPRSpillVGPRDefinedSet hack 2020-12-16 21:33:35 -05:00
spill_more_than_wavesize_csr_sgprs.ll [AMDGPU] Use pseudo instructions for readlane/writelane 2020-10-29 16:00:53 +00:00
split-arg-dbg-value.ll [AMDGPU] Skip CFIInstructions in SIInsertWaitcnts 2020-06-17 12:41:03 -04:00
split-scalar-i64-add.ll
split-smrd.ll
split-vector-memoperand-offsets.ll AMDGPU: Use 128-bit DS operations by default 2020-04-02 17:17:47 -04:00
splitkit-copy-bundle.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
splitkit-copy-live-lanes.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
splitkit-getsubrangeformask.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
splitkit-nolivesubranges.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
splitkit.mir
sra.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
sram-ecc-default.ll
srem.ll [AMDGPU] Fix expansion of i16 MULH 2020-10-22 17:05:06 +02:00
srem64.ll [Sink] Optimize/simplify sink candidate finding with nearest common dominator 2020-08-30 22:51:00 -07:00
srl.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
sroa-before-unroll.ll [AMDGPU][NewPM] Port amdgpu-promote-alloca(-to-vector) 2020-12-28 17:52:31 -08:00
ssubo.ll
ssubsat.ll [DAG][AMDGPU][X86] Add SimplifyMultipleUseDemandedBits handling for SIGN/ZERO_EXTEND + SIGN/ZERO_EXTEND_VECTOR_INREG 2020-07-29 18:10:59 +01:00
stack-pointer-offset-relative-frameindex.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
stack-realign-kernel.ll AMDGPU: Assume f32 denormals are enabled by default 2020-04-02 17:17:12 -04:00
stack-realign.ll OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00
stack-size-overflow.ll AMDGPU: Lower the threshold reported for maximum stack size exceeded 2020-10-21 12:06:27 -04:00
stack-slot-color-sgpr-vgpr-spills.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
stale-livevar-in-twoaddr-pass.mir [AMDGPU] Update LiveVariables in convertToThreeAddress() 2020-10-13 08:12:20 +08:00
store-barrier.ll
store-clobbers-load.ll AMDGPU: Annotate amdgpu.noclobber for global loads only 2021-01-05 14:47:19 -08:00
store-global.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
store-hi16.ll OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00
store-local.96.ll [AMDGPU] Set DS alignment requirements to be more strict 2020-09-18 15:26:24 +02:00
store-local.128.ll [AMDGPU] Resolve issues when picking between ds_read/write and ds_read2/write2 2020-12-10 12:40:49 +01:00
store-local.ll [AMDGPU] Set DS alignment requirements to be more strict 2020-09-18 15:26:24 +02:00
store-private.ll
store-v3i64.ll AMDGPU: Use 128-bit DS operations by default 2020-04-02 17:17:47 -04:00
store-vector-ptrs.ll
store-weird-sizes.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
store_typed.ll
stress-calls.ll
strict_fadd.f16.ll AMDGPU: Select strict_fadd 2020-06-04 17:49:00 -04:00
strict_fadd.f32.ll [FPEnv] Allow fneg + strict_fadd -> strict_fsub in DAGCombiner 2020-08-27 08:17:01 -04:00
strict_fadd.f64.ll AMDGPU: Select strict_fadd 2020-06-04 17:49:00 -04:00
strict_fma.f16.ll AMDGPU: Select strict_fma 2020-06-04 17:49:00 -04:00
strict_fma.f32.ll AMDGPU: Select strict_fma 2020-06-04 17:49:00 -04:00
strict_fma.f64.ll AMDGPU: Select strict_fma 2020-06-04 17:49:00 -04:00
strict_fmul.f16.ll AMDGPU: Select strict_fmul 2020-06-04 17:49:00 -04:00
strict_fmul.f32.ll AMDGPU: Select strict_fmul 2020-06-04 17:49:00 -04:00
strict_fmul.f64.ll AMDGPU: Select strict_fmul 2020-06-04 17:49:00 -04:00
strict_fsub.f16.ll DAG: Handle expanding strict_fsub into fneg and strict_fadd 2020-07-21 16:17:10 -04:00
strict_fsub.f32.ll DAG: Handle expanding strict_fsub into fneg and strict_fadd 2020-07-21 16:17:10 -04:00
strict_fsub.f64.ll DAG: Handle expanding strict_fsub into fneg and strict_fadd 2020-07-21 16:17:10 -04:00
structurize.ll
structurize1.ll
sub-zext-cc-zext-cc.ll [AMDGPU] Extend macro fusion for ADDC and SUBB to SUBBREV 2020-03-11 17:59:21 +00:00
sub.i16.ll [AMDGPU][MC] Corrected decoding of 16-bit literals 2020-07-22 17:20:43 +03:00
sub.ll
sub.v2i16.ll [AMDGPU] Optimize waitcnt insertion for flat memory operations 2020-10-20 22:55:12 +00:00
sub_i1.ll
subreg-coalescer-crash.ll
subreg-coalescer-undef-use.ll Resubmit: [AMDGPU] Invert the handling of skip insertion. 2020-01-22 13:18:32 +09:00
subreg-eliminate-dead.ll
subreg-intervals.mir
subreg-split-live-in-error.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
subreg-undef-def-with-other-subreg-defs.mir [AMDGPU] Define AGPR subregs 2020-04-28 15:30:43 -07:00
subreg_interference.mir
subvector-test.mir [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions 2020-03-19 15:35:16 -04:00
switch-default-block-unreachable.ll [AMDGPU] Move LowerSwitch pass to CodeGenPrepare. 2020-07-11 16:33:38 +05:30
switch-unreachable.ll [AMDGPU] add generated checks for some LIT tests 2020-03-03 11:47:05 +05:30
swizzle-export.ll
syncscopes.ll
tail-call-cgp.ll
tail-dup-bundle.mir Process BUNDLE in tail duplication 2020-01-15 15:46:57 -08:00
tail-duplication-convergent.ll
target-cpu.ll
tex-clause-antidep.ll
texture-input-merge.ll
token-factor-inline-limit-test.ll [AMDGPU] Don't cluster stores 2020-09-14 13:40:17 +01:00
transform-block-with-return-to-epilog.ll [BPI] Improve static heuristics for "cold" paths. 2020-12-23 22:47:36 +07:00
trap.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
trunc-bitcast-vector.ll
trunc-cmp-constant.ll [AMDGPU] Fix CHECK lines 2020-04-03 10:07:21 +01:00
trunc-combine.ll [AMDGPU] Optimize waitcnt insertion for flat memory operations 2020-10-20 22:55:12 +00:00
trunc-store-f64-to-f16.ll
trunc-store-i1.ll
trunc-store-i64.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
trunc-store-vec-i16-to-i8.ll [AMDGPU] Expand vector trunc stores from i16 to i8 2020-04-07 21:47:45 -07:00
trunc-store.ll
trunc-vector-store-assertion-failure.ll
trunc.ll Fix 64-bit copy to SCC 2020-08-09 20:50:30 +02:00
tti-unroll-prefs.ll
twoaddr-fma.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
twoaddr-mad.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
uaddo.ll
uaddsat.ll [DAG][AMDGPU][X86] Add SimplifyMultipleUseDemandedBits handling for SIGN/ZERO_EXTEND + SIGN/ZERO_EXTEND_VECTOR_INREG 2020-07-29 18:10:59 +01:00
udiv.ll [AMDGPU] Add gfx1030 target 2020-06-15 16:18:05 -07:00
udiv64.ll Fix 64-bit copy to SCC 2020-08-09 20:50:30 +02:00
udivrem.ll Fix 64-bit copy to SCC 2020-08-09 20:50:30 +02:00
udivrem24.ll [llvm] Fix missing FileCheck directive colons 2020-04-06 09:59:08 -06:00
udivrem64.r600.ll AMDGPU: Cleanup and generate 64-bit div tests 2020-01-20 17:19:39 -05:00
uint_to_fp.f64.ll Fix 64-bit copy to SCC 2020-08-09 20:50:30 +02:00
uint_to_fp.i64.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
uint_to_fp.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
uitofp.f16.ll AMDGPU: Fix some incorrect FUNC-LABEL checks 2020-02-26 09:43:13 +00:00
umed3.ll
unaligned-load-store.ll [AMDGPU] Support unaligned flat scratch in TLI 2020-12-22 16:12:31 -08:00
undefined-physreg-sgpr-spill.mir
undefined-subreg-liverange.ll [amdgpu] Enable use of AA during codegen. 2020-10-27 09:46:23 -04:00
unexpected-reg-unit-state.mir [AMDGPU] Remove scratch rsrc from spill pseudos 2020-11-12 15:23:37 -08:00
unhandled-loop-condition-assertion.ll Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC" 2020-05-22 05:36:15 -06:00
uniform-branch-intrinsic-cond.ll AMDGPU: Update tests to use modern buffer intrinsics 2020-01-16 13:49:43 -05:00
uniform-cfg.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
uniform-crash.ll
uniform-loop-inside-nonuniform.ll [AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU. 2020-04-06 09:05:58 -04:00
uniform-work-group-attribute-missing.ll AMDGPU: Directly annotate functions if they have calls 2020-03-12 19:10:59 -04:00
uniform-work-group-nested-function-calls.ll AMDGPU: Directly annotate functions if they have calls 2020-03-12 19:10:59 -04:00
uniform-work-group-prevent-attribute-propagation.ll AMDGPU: Directly annotate functions if they have calls 2020-03-12 19:10:59 -04:00
uniform-work-group-propagate-attribute.ll AMDGPU: Directly annotate functions if they have calls 2020-03-12 19:10:59 -04:00
uniform-work-group-recursion-test.ll AMDGPU: Directly annotate functions if they have calls 2020-03-12 19:10:59 -04:00
uniform-work-group-test.ll AMDGPU: Directly annotate functions if they have calls 2020-03-12 19:10:59 -04:00
unify-metadata.ll [NewPM][AMDGPU] Port amdgpu-unify-metadata 2021-01-04 11:57:46 -08:00
unigine-liveness-crash.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
unknown-processor.ll
unpack-half.ll
unroll.ll [AMDGPU] Enable runtime unroll for LDS 2020-02-27 12:59:35 -08:00
unstructured-cfg-def-use-issue.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
unsupported-calls.ll [AMDGPU] Add amdgpu_gfx calling convention 2020-11-09 16:51:44 +01:00
unsupported-cc.ll
unsupported-image-a16.ll AMDGPU: Have a few selection failure tests check both paths 2020-08-24 17:46:31 -04:00
unsupported-image-g16.ll AMDGPU: Have a few selection failure tests check both paths 2020-08-24 17:46:31 -04:00
update-phi.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
urem.ll
urem64.ll [Sink] Optimize/simplify sink candidate finding with nearest common dominator 2020-08-30 22:51:00 -07:00
use-sgpr-multiple-times.ll
usubo.ll
usubsat.ll [DAG][AMDGPU][X86] Add SimplifyMultipleUseDemandedBits handling for SIGN/ZERO_EXTEND + SIGN/ZERO_EXTEND_VECTOR_INREG 2020-07-29 18:10:59 +01:00
v1i64-kernel-arg.ll
v1024.ll
v_cndmask.ll [AMDGPU] Use lowercase for subtarget feature names in RUN lines 2020-10-13 09:02:09 +01:00
v_cvt_pk_u8_f32.ll
v_mac.ll [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed 2021-01-04 14:44:10 -06:00
v_mac_f16.ll [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed 2021-01-04 14:44:10 -06:00
v_madak_f16.ll [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics 2020-07-17 11:02:13 +01:00
v_swap_b32.mir [AMDGPU] Fixed v_swap_b32 match 2020-10-21 10:14:24 -07:00
valu-i1.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
vccz-corrupt-bug-workaround.mir [AMDGPU] Fix and extend vccz workarounds 2020-11-18 15:26:06 +00:00
vcmpx-exec-war-hazard.mir [AMDGPU] Use lowercase for subtarget feature names in RUN lines 2020-10-13 09:02:09 +01:00
vcmpx-permlane-hazard.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
vector-alloca-addrspacecast.ll
vector-alloca-atomic.ll
vector-alloca-bitcast.ll [InstCombine] use poison as placeholder for undemanded elems 2020-12-28 08:58:15 +09:00
vector-alloca-limits.ll [AMDGPU] Limit promote alloca to vector with VGPR budget 2020-07-01 15:57:24 -07:00
vector-alloca.ll [AMDGPU][NewPM] Port amdgpu-promote-alloca(-to-vector) 2020-12-28 17:52:31 -08:00
vector-extract-insert.ll [AMDGPU] Add alignment check for v3 to v4 load type promotion 2020-11-01 12:05:34 +05:30
vector-legalizer-divergence.ll
vector_shuffle.packed.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
vectorize-buffer-fat-pointer.ll
vectorize-global-local.ll
vectorize-loads.ll [amdgpu] Add the late codegen preparation pass. 2020-10-27 14:07:59 -04:00
verify-constant-bus-violations.mir [AMDGPU] Consider all SGPR uses as unique in constant bus verify 2020-09-24 10:52:40 +09:00
verify-sop.mir Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
vertex-fetch-encoding.ll
vgpr-descriptor-waterfall-loop-idom-update.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
vgpr-spill-emergency-stack-slot-compute.ll AMDGPU: Update AMDHSA code object version handling 2020-10-14 13:04:27 -04:00
vgpr-spill-emergency-stack-slot.ll [CodeGen] Ensure callers of CreateStackTemporary use sensible alignments 2020-06-09 08:10:17 +01:00
vgpr-spill.mir AMDGPU: Remove SGPRSpillVGPRDefinedSet hack 2020-12-16 21:33:35 -05:00
vgpr-tuple-allocation.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
vi-removed-intrinsics.ll
virtregrewrite-undef-identity-copy.mir [AMDGPU] Introduce more scratch registers in the ABI. 2020-05-05 23:02:58 +05:30
visit-physreg-vgpr-imm-folding-bug.ll Revert "[AMDGPU] Insert waitcnt after returning from call" 2020-09-23 17:16:39 +02:00
vmem-to-salu-hazard.mir [AMDGPU] Add default 1 glc operand to rtn atomics 2020-11-05 10:41:59 -08:00
vmem-vcc-hazard.mir [HazardRec] Allow inserting multiple wait-states simultaneously 2020-10-20 17:03:47 -07:00
vop-shrink-frame-index.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
vop-shrink-non-ssa.mir AMDGPU: Rename add/sub with carry out instructions 2020-07-16 13:16:30 -04:00
vop-shrink.ll
vselect.ll Fix 64-bit copy to SCC 2020-08-09 20:50:30 +02:00
vselect64.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll [AMDGPU] Order pos exports before param exports 2020-05-12 23:02:23 +09:00
waitcnt-back-edge-loop.mir [AMDGPU] Optimize waitcnt insertion for flat memory operations 2020-10-20 22:55:12 +00:00
waitcnt-debug.mir
waitcnt-flat.ll
waitcnt-loop-irreducible.mir [AMDGPU] Add default 1 glc operand to rtn atomics 2020-11-05 10:41:59 -08:00
waitcnt-loop-single-basic-block.mir AMDGPU: Fix using unencodable instructions in tests 2020-06-04 16:50:19 -04:00
waitcnt-looptest.ll [AMDGPU] Optimize waitcnt insertion for flat memory operations 2020-10-20 22:55:12 +00:00
waitcnt-meta-instructions.mir AMDGPU: Fix inserting waitcnts before kill uses 2020-09-09 19:45:40 -04:00
waitcnt-no-redundant.mir
waitcnt-overflow.mir [AMDGPU] Control num waves per EU for implicit work-group size 2020-07-01 22:53:52 -04:00
waitcnt-permute.mir AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
waitcnt-preexisting.mir AMDGPU: Fix using unencodable instructions in tests 2020-06-04 16:50:19 -04:00
waitcnt-skip-meta.mir [AMDGPU] Skip CFIInstructions in SIInsertWaitcnts 2020-06-17 12:41:03 -04:00
waitcnt-vmem-waw.mir AMDGPU: Move MIMG MMO check to verifier 2020-05-29 20:58:23 -04:00
waitcnt-vscnt.ll [AMDGPU] Optimize waitcnt insertion for flat memory operations 2020-10-20 22:55:12 +00:00
waitcnt-vscnt.mir [AMDGPU] Add default 1 glc operand to rtn atomics 2020-11-05 10:41:59 -08:00
waitcnt.mir [AMDGPU] Optimize waitcnt insertion for flat memory operations 2020-10-20 22:55:12 +00:00
wave32.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
wave_dispatch_regs.ll [AMDGPU] Emit new pal metadata by default 2020-10-26 10:16:17 +01:00
widen-smrd-loads.ll [AMDGPU] Optimize waitcnt insertion for flat memory operations 2020-10-20 22:55:12 +00:00
widen-vselect-and-mask.ll
widen_extending_scalar_loads.ll Make IRBuilder automatically set alignment on load/store/alloca. 2020-04-13 13:43:14 -07:00
wqm.ll [AMDGPU] Move WQM Pass after MI Scheduler 2020-10-27 10:25:53 +09:00
wqm.mir [AMDGPU] SIWholeQuadMode fix mode insertion when SCC always defined 2020-11-08 11:14:57 +09:00
write-register-vgpr-into-sgpr.ll
write_register.ll AMDGPU: Split test function 2020-01-12 22:44:51 -05:00
wrong-transalu-pos-fix.ll
wwm-reserved.ll [AMDGPU] Fix insert of SIPreAllocateWWMRegs in FastRegAlloc 2020-10-28 12:15:15 +09:00
xfail.r600.bitcast.ll
xnor.ll
xor.ll
xor3-i1-const.ll
xor3.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
xor_add.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
zero_extend.ll Revert "[AMDGPU] Enable compare operations to be selected by divergence" 2020-06-24 11:21:30 -04:00
zext-i64-bit-operand.ll
zext-lid.ll

README

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.