forked from OSchip/llvm-project
153 lines
6.1 KiB
C++
153 lines
6.1 KiB
C++
//===-- ArchitectureArm.cpp -----------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "Plugins/Architecture/Arm/ArchitectureArm.h"
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#include "Plugins/Process/Utility/ARMDefines.h"
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#include "Plugins/Process/Utility/InstructionUtils.h"
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#include "lldb/Core/PluginManager.h"
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#include "lldb/Target/RegisterContext.h"
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#include "lldb/Target/Thread.h"
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#include "lldb/Utility/ArchSpec.h"
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using namespace lldb_private;
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using namespace lldb;
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LLDB_PLUGIN_DEFINE(ArchitectureArm)
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void ArchitectureArm::Initialize() {
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PluginManager::RegisterPlugin(GetPluginNameStatic(),
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"Arm-specific algorithms",
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&ArchitectureArm::Create);
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}
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void ArchitectureArm::Terminate() {
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PluginManager::UnregisterPlugin(&ArchitectureArm::Create);
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}
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std::unique_ptr<Architecture> ArchitectureArm::Create(const ArchSpec &arch) {
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if (arch.GetMachine() != llvm::Triple::arm)
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return nullptr;
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return std::unique_ptr<Architecture>(new ArchitectureArm());
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}
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void ArchitectureArm::OverrideStopInfo(Thread &thread) const {
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// We need to check if we are stopped in Thumb mode in a IT instruction and
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// detect if the condition doesn't pass. If this is the case it means we
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// won't actually execute this instruction. If this happens we need to clear
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// the stop reason to no thread plans think we are stopped for a reason and
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// the plans should keep going.
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//
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// We do this because when single stepping many ARM processes, debuggers
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// often use the BVR/BCR registers that says "stop when the PC is not equal
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// to its current value". This method of stepping means we can end up
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// stopping on instructions inside an if/then block that wouldn't get
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// executed. By fixing this we can stop the debugger from seeming like you
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// stepped through both the "if" _and_ the "else" clause when source level
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// stepping because the debugger stops regardless due to the BVR/BCR
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// triggering a stop.
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//
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// It also means we can set breakpoints on instructions inside an an if/then
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// block and correctly skip them if we use the BKPT instruction. The ARM and
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// Thumb BKPT instructions are unconditional even when executed in a Thumb IT
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// block.
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//
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// If your debugger inserts software traps in ARM/Thumb code, it will need to
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// use 16 and 32 bit instruction for 16 and 32 bit thumb instructions
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// respectively. If your debugger inserts a 16 bit thumb trap on top of a 32
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// bit thumb instruction for an opcode that is inside an if/then, it will
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// change the it/then to conditionally execute your
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// 16 bit trap and then cause your program to crash if it executes the
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// trailing 16 bits (the second half of the 32 bit thumb instruction you
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// partially overwrote).
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RegisterContextSP reg_ctx_sp(thread.GetRegisterContext());
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if (!reg_ctx_sp)
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return;
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const uint32_t cpsr = reg_ctx_sp->GetFlags(0);
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if (cpsr == 0)
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return;
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// Read the J and T bits to get the ISETSTATE
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const uint32_t J = Bit32(cpsr, 24);
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const uint32_t T = Bit32(cpsr, 5);
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const uint32_t ISETSTATE = J << 1 | T;
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if (ISETSTATE == 0) {
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// NOTE: I am pretty sure we want to enable the code below
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// that detects when we stop on an instruction in ARM mode that is conditional
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// and the condition doesn't pass. This can happen if you set a breakpoint on
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// an instruction that is conditional. We currently will _always_ stop on the
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// instruction which is bad. You can also run into this while single stepping
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// and you could appear to run code in the "if" and in the "else" clause
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// because it would stop at all of the conditional instructions in both. In
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// such cases, we really don't want to stop at this location.
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// I will check with the lldb-dev list first before I enable this.
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#if 0
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// ARM mode: check for condition on instruction
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const addr_t pc = reg_ctx_sp->GetPC();
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Status error;
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// If we fail to read the opcode we will get UINT64_MAX as the result in
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// "opcode" which we can use to detect if we read a valid opcode.
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const uint64_t opcode = thread.GetProcess()->ReadUnsignedIntegerFromMemory(pc, 4, UINT64_MAX, error);
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if (opcode <= UINT32_MAX)
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{
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const uint32_t condition = Bits32((uint32_t)opcode, 31, 28);
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if (!ARMConditionPassed(condition, cpsr))
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{
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// We ARE stopped on an ARM instruction whose condition doesn't
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// pass so this instruction won't get executed. Regardless of why
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// it stopped, we need to clear the stop info
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thread.SetStopInfo (StopInfoSP());
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}
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}
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#endif
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} else if (ISETSTATE == 1) {
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// Thumb mode
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const uint32_t ITSTATE = Bits32(cpsr, 15, 10) << 2 | Bits32(cpsr, 26, 25);
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if (ITSTATE != 0) {
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const uint32_t condition = Bits32(ITSTATE, 7, 4);
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if (!ARMConditionPassed(condition, cpsr)) {
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// We ARE stopped in a Thumb IT instruction on an instruction whose
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// condition doesn't pass so this instruction won't get executed.
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// Regardless of why it stopped, we need to clear the stop info
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thread.SetStopInfo(StopInfoSP());
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}
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}
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}
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}
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addr_t ArchitectureArm::GetCallableLoadAddress(addr_t code_addr,
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AddressClass addr_class) const {
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bool is_alternate_isa = false;
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switch (addr_class) {
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case AddressClass::eData:
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case AddressClass::eDebug:
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return LLDB_INVALID_ADDRESS;
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case AddressClass::eCodeAlternateISA:
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is_alternate_isa = true;
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break;
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default: break;
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}
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if ((code_addr & 2u) || is_alternate_isa)
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return code_addr | 1u;
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return code_addr;
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}
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addr_t ArchitectureArm::GetOpcodeLoadAddress(addr_t opcode_addr,
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AddressClass addr_class) const {
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switch (addr_class) {
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case AddressClass::eData:
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case AddressClass::eDebug:
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return LLDB_INVALID_ADDRESS;
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default: break;
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}
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return opcode_addr & ~(1ull);
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}
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