forked from OSchip/llvm-project
6747 lines
455 KiB
C++
6747 lines
455 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
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// Test host codegen.
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8
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// Test target codegen - host bc file has to be created first.
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16
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// Test host codegen.
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20
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// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22
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// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24
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// Test target codegen - host bc file has to be created first.
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28
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// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30
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// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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// We have 6 target regions
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// Check target registration is registered as a Ctor.
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template<typename tx>
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tx ftemplate(int n) {
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tx a = 0;
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#pragma omp target parallel num_threads(tx(20))
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{
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}
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short b = 1;
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#pragma omp target parallel num_threads(b)
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{
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a += b;
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}
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return a;
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}
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static
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int fstatic(int n) {
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#pragma omp target parallel num_threads(n)
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{
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}
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#pragma omp target parallel num_threads(32+n)
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{
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}
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return n+1;
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}
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struct S1 {
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double a;
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int r1(int n){
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int b = 1;
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#pragma omp target parallel num_threads(n-b)
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{
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this->a = (double)b + 1.5;
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}
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#pragma omp target parallel num_threads(1024)
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{
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this->a = 2.5;
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}
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return (int)a;
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}
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};
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int bar(int n){
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int a = 0;
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S1 S;
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a += S.r1(n);
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a += fstatic(n);
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a += ftemplate<int>(n);
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return a;
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}
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// Check that the offloading functions are emitted and that the parallel function
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// is appropriately guarded.
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#endif
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// CHECK1-LABEL: define {{[^@]+}}@_Z3bari
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// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
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// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
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// CHECK1-NEXT: store i32 0, i32* [[A]], align 4
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// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
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// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
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// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
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// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
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// CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4
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// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
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// CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
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// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
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// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
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// CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
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// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
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// CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
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// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
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// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
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// CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
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// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
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// CHECK1-NEXT: ret i32 [[TMP6]]
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
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// CHECK1-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
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// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8
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// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
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// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
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// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
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// CHECK1-NEXT: store i32 1, i32* [[B]], align 4
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// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK1-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1**
|
|
// CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double**
|
|
// CHECK1-NEXT: store double* [[A]], double** [[TMP9]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP10]], align 8
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1**
|
|
// CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double**
|
|
// CHECK1-NEXT: store double* [[A3]], double** [[TMP29]], align 8
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024)
|
|
// CHECK1-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
|
// CHECK1: omp_offload.failed7:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
|
// CHECK1: omp_offload.cont8:
|
|
// CHECK1-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8
|
|
// CHECK1-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32
|
|
// CHECK1-NEXT: ret i32 [[CONV10]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP7]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]])
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]]
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
|
// CHECK1: omp_offload.failed7:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
|
// CHECK1: omp_offload.cont8:
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1
|
|
// CHECK1-NEXT: ret i32 [[ADD9]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20)
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]])
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
|
|
// CHECK1: omp_offload.failed3:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]]
|
|
// CHECK1: omp_offload.cont4:
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: ret i32 [[TMP30]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
|
// CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
|
|
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
|
// CHECK1-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK1-NEXT: store double 2.500000e+00, double* [[A]], align 8
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
|
// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
|
// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
|
// CHECK1-SAME: () #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20)
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*))
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
|
// CHECK1-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK2-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK2-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1**
|
|
// CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double**
|
|
// CHECK2-NEXT: store double* [[A]], double** [[TMP9]], align 8
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP10]], align 8
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP15]], align 8
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP20]], align 8
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
|
|
// CHECK2-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK2: omp_offload.failed:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK2: omp_offload.cont:
|
|
// CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1**
|
|
// CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8
|
|
// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double**
|
|
// CHECK2-NEXT: store double* [[A3]], double** [[TMP29]], align 8
|
|
// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024)
|
|
// CHECK2-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
|
// CHECK2: omp_offload.failed7:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
|
// CHECK2: omp_offload.cont8:
|
|
// CHECK2-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8
|
|
// CHECK2-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32
|
|
// CHECK2-NEXT: ret i32 [[CONV10]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP7]], align 8
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]])
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK2: omp_offload.failed:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK2: omp_offload.cont:
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]]
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP20]], align 8
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
|
|
// CHECK2-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
|
// CHECK2: omp_offload.failed7:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
|
// CHECK2: omp_offload.cont8:
|
|
// CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1
|
|
// CHECK2-NEXT: ret i32 [[ADD9]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20)
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK2: omp_offload.failed:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK2: omp_offload.cont:
|
|
// CHECK2-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK2-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32
|
|
// CHECK2-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]])
|
|
// CHECK2-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
|
|
// CHECK2: omp_offload.failed3:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT4]]
|
|
// CHECK2: omp_offload.cont4:
|
|
// CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: ret i32 [[TMP30]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
|
// CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
|
|
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
|
|
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
|
// CHECK2-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK2-NEXT: store double 2.500000e+00, double* [[A]], align 8
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
|
// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
|
// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
|
// CHECK2-SAME: () #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20)
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*))
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
|
// CHECK2-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK3-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK3-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1**
|
|
// CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double**
|
|
// CHECK3-NEXT: store double* [[A]], double** [[TMP9]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP10]], align 4
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1**
|
|
// CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double**
|
|
// CHECK3-NEXT: store double* [[A2]], double** [[TMP29]], align 4
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024)
|
|
// CHECK3-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
|
|
// CHECK3: omp_offload.failed6:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT7]]
|
|
// CHECK3: omp_offload.cont7:
|
|
// CHECK3-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32
|
|
// CHECK3-NEXT: ret i32 [[CONV]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP7]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]])
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]]
|
|
// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
|
|
// CHECK3: omp_offload.failed6:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT7]]
|
|
// CHECK3: omp_offload.cont7:
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1
|
|
// CHECK3-NEXT: ret i32 [[ADD8]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20)
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]])
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]]
|
|
// CHECK3: omp_offload.failed2:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT3]]
|
|
// CHECK3: omp_offload.cont3:
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: ret i32 [[TMP30]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
|
// CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
|
|
// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
|
// CHECK3-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK3-NEXT: store double 2.500000e+00, double* [[A]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
|
// CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
|
// CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
|
// CHECK3-SAME: () #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20)
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*))
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
|
// CHECK3-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
|
|
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
|
|
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK4-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK4-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1**
|
|
// CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double**
|
|
// CHECK4-NEXT: store double* [[A]], double** [[TMP9]], align 4
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP10]], align 4
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP15]], align 4
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP20]], align 4
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
|
|
// CHECK4-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK4: omp_offload.failed:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK4: omp_offload.cont:
|
|
// CHECK4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1**
|
|
// CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4
|
|
// CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double**
|
|
// CHECK4-NEXT: store double* [[A2]], double** [[TMP29]], align 4
|
|
// CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP30]], align 4
|
|
// CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024)
|
|
// CHECK4-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
|
|
// CHECK4: omp_offload.failed6:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT7]]
|
|
// CHECK4: omp_offload.cont7:
|
|
// CHECK4-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32
|
|
// CHECK4-NEXT: ret i32 [[CONV]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP7]], align 4
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]])
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK4: omp_offload.failed:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK4: omp_offload.cont:
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]]
|
|
// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP20]], align 4
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
|
|
// CHECK4-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
|
|
// CHECK4: omp_offload.failed6:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT7]]
|
|
// CHECK4: omp_offload.cont7:
|
|
// CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1
|
|
// CHECK4-NEXT: ret i32 [[ADD8]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20)
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK4: omp_offload.failed:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK4: omp_offload.cont:
|
|
// CHECK4-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK4-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32
|
|
// CHECK4-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]])
|
|
// CHECK4-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]]
|
|
// CHECK4: omp_offload.failed2:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT3]]
|
|
// CHECK4: omp_offload.cont3:
|
|
// CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: ret i32 [[TMP30]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
|
// CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
|
|
// CHECK4-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK4-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
|
// CHECK4-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK4-NEXT: store double 2.500000e+00, double* [[A]], align 4
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
|
// CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
|
// CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
|
// CHECK4-SAME: () #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20)
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*))
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
|
// CHECK4-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
|
|
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
|
|
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK4-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK5-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK5-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK5-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
|
|
// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK5-NEXT: store double 2.500000e+00, double* [[A2]], align 8
|
|
// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8
|
|
// CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32
|
|
// CHECK5-NEXT: ret i32 [[CONV4]]
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]]
|
|
// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK5-NEXT: ret i32 [[ADD2]]
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK5-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK5-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
|
|
// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK6-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK6-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK6-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
|
|
// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK6-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK6-NEXT: store double 2.500000e+00, double* [[A2]], align 8
|
|
// CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8
|
|
// CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32
|
|
// CHECK6-NEXT: ret i32 [[CONV4]]
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]]
|
|
// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK6-NEXT: ret i32 [[ADD2]]
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK6-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK6-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
|
|
// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK7-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK7-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
|
|
// CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK7-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK7-NEXT: store double 2.500000e+00, double* [[A2]], align 4
|
|
// CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4
|
|
// CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32
|
|
// CHECK7-NEXT: ret i32 [[CONV4]]
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]]
|
|
// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK7-NEXT: ret i32 [[ADD2]]
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK7-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK7-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
|
|
// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK8-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK8-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK8-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
|
|
// CHECK8-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK8-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK8-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK8-NEXT: store double 2.500000e+00, double* [[A2]], align 4
|
|
// CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4
|
|
// CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32
|
|
// CHECK8-NEXT: ret i32 [[CONV4]]
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]]
|
|
// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK8-NEXT: ret i32 [[ADD2]]
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK8-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK8-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
|
|
// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK8-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
|
// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
|
|
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
|
// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
|
// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK9-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
|
|
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
|
|
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
|
// CHECK9-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK9-NEXT: store double 2.500000e+00, double* [[A]], align 8
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
|
// CHECK9-SAME: () #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20)
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
|
// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
|
|
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
|
|
// CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
|
|
// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
|
// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
|
|
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
|
// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
|
// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
|
|
// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
|
|
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
|
// CHECK10-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK10-NEXT: store double 2.500000e+00, double* [[A]], align 8
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
|
// CHECK10-SAME: () #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20)
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
|
// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
|
|
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
|
|
// CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
|
|
// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
|
// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
|
|
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
|
// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
|
// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
|
|
// CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
|
// CHECK11-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK11-NEXT: store double 2.500000e+00, double* [[A]], align 4
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
|
// CHECK11-SAME: () #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20)
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
|
// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
|
|
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
|
|
// CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
|
|
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
|
// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
|
|
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
|
// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
|
// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
|
|
// CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
|
// CHECK12-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK12-NEXT: store double 2.500000e+00, double* [[A]], align 4
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
|
// CHECK12-SAME: () #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20)
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
|
// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
|
|
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
|
|
// CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
|
|
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK13-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK13-NEXT: entry:
|
|
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
|
|
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
|
|
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
|
|
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK13-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK13-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK13-NEXT: entry:
|
|
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK13-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK13-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
|
|
// CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK13-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK13-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK13-NEXT: store double 2.500000e+00, double* [[A2]], align 8
|
|
// CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK13-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8
|
|
// CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32
|
|
// CHECK13-NEXT: ret i32 [[CONV4]]
|
|
//
|
|
//
|
|
// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK13-NEXT: entry:
|
|
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]]
|
|
// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK13-NEXT: ret i32 [[ADD2]]
|
|
//
|
|
//
|
|
// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK13-NEXT: entry:
|
|
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK13-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK13-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
|
|
// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK13-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
//
|
|
// CHECK14-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK14-NEXT: entry:
|
|
// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
|
|
// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
|
|
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
|
|
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK14-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK14-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK14-NEXT: entry:
|
|
// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK14-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK14-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
|
|
// CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK14-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK14-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK14-NEXT: store double 2.500000e+00, double* [[A2]], align 8
|
|
// CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK14-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8
|
|
// CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32
|
|
// CHECK14-NEXT: ret i32 [[CONV4]]
|
|
//
|
|
//
|
|
// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK14-NEXT: entry:
|
|
// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]]
|
|
// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK14-NEXT: ret i32 [[ADD2]]
|
|
//
|
|
//
|
|
// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK14-NEXT: entry:
|
|
// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK14-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK14-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
|
|
// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK14-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
//
|
|
// CHECK15-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK15-NEXT: entry:
|
|
// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
|
|
// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
|
|
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
|
|
// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK15-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK15-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK15-NEXT: entry:
|
|
// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK15-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK15-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
|
|
// CHECK15-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK15-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK15-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK15-NEXT: store double 2.500000e+00, double* [[A2]], align 4
|
|
// CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK15-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4
|
|
// CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32
|
|
// CHECK15-NEXT: ret i32 [[CONV4]]
|
|
//
|
|
//
|
|
// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK15-NEXT: entry:
|
|
// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]]
|
|
// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK15-NEXT: ret i32 [[ADD2]]
|
|
//
|
|
//
|
|
// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK15-NEXT: entry:
|
|
// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK15-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK15-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
|
|
// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK15-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
//
|
|
// CHECK16-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK16-NEXT: entry:
|
|
// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
|
|
// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
|
|
// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
|
|
// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK16-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK16-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK16-NEXT: entry:
|
|
// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK16-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK16-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
|
|
// CHECK16-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK16-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK16-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK16-NEXT: store double 2.500000e+00, double* [[A2]], align 4
|
|
// CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK16-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4
|
|
// CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32
|
|
// CHECK16-NEXT: ret i32 [[CONV4]]
|
|
//
|
|
//
|
|
// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK16-NEXT: entry:
|
|
// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]]
|
|
// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK16-NEXT: ret i32 [[ADD2]]
|
|
//
|
|
//
|
|
// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK16-NEXT: entry:
|
|
// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK16-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK16-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
|
|
// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK16-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK17-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK17-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1**
|
|
// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double**
|
|
// CHECK17-NEXT: store double* [[A]], double** [[TMP9]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP10]], align 8
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK17: omp_offload.failed:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK17: omp_offload.cont:
|
|
// CHECK17-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1**
|
|
// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8
|
|
// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double**
|
|
// CHECK17-NEXT: store double* [[A3]], double** [[TMP29]], align 8
|
|
// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024)
|
|
// CHECK17-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
|
// CHECK17: omp_offload.failed7:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
|
// CHECK17: omp_offload.cont8:
|
|
// CHECK17-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8
|
|
// CHECK17-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32
|
|
// CHECK17-NEXT: ret i32 [[CONV10]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP7]], align 8
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]])
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK17: omp_offload.failed:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK17: omp_offload.cont:
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]]
|
|
// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
|
// CHECK17: omp_offload.failed7:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
|
// CHECK17: omp_offload.cont8:
|
|
// CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1
|
|
// CHECK17-NEXT: ret i32 [[ADD9]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20)
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK17: omp_offload.failed:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK17: omp_offload.cont:
|
|
// CHECK17-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16*
|
|
// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16*
|
|
// CHECK17-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP13]], align 8
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP18]], align 8
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK17-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32
|
|
// CHECK17-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]])
|
|
// CHECK17-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
|
|
// CHECK17: omp_offload.failed3:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT4]]
|
|
// CHECK17: omp_offload.cont4:
|
|
// CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: ret i32 [[TMP30]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
|
// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
|
|
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
|
|
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
|
// CHECK17-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK17-NEXT: store double 2.500000e+00, double* [[A]], align 8
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
|
// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
|
// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
|
// CHECK17-SAME: () #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20)
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*))
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
|
// CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
|
|
// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11
|
|
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
|
|
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK17-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK18-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK18-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1**
|
|
// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double**
|
|
// CHECK18-NEXT: store double* [[A]], double** [[TMP9]], align 8
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP10]], align 8
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8
|
|
// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8
|
|
// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8
|
|
// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8
|
|
// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8
|
|
// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
|
|
// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK18: omp_offload.failed:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK18: omp_offload.cont:
|
|
// CHECK18-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1**
|
|
// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8
|
|
// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double**
|
|
// CHECK18-NEXT: store double* [[A3]], double** [[TMP29]], align 8
|
|
// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024)
|
|
// CHECK18-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
|
// CHECK18: omp_offload.failed7:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]]
|
|
// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
|
// CHECK18: omp_offload.cont8:
|
|
// CHECK18-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8
|
|
// CHECK18-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32
|
|
// CHECK18-NEXT: ret i32 [[CONV10]]
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP7]], align 8
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]])
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK18: omp_offload.failed:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]]
|
|
// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK18: omp_offload.cont:
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]]
|
|
// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4
|
|
// CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8
|
|
// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8
|
|
// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8
|
|
// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8
|
|
// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
|
|
// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
|
// CHECK18: omp_offload.failed7:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]]
|
|
// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
|
// CHECK18: omp_offload.cont8:
|
|
// CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1
|
|
// CHECK18-NEXT: ret i32 [[ADD9]]
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20)
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK18: omp_offload.failed:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]]
|
|
// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK18: omp_offload.cont:
|
|
// CHECK18-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16*
|
|
// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16*
|
|
// CHECK18-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP13]], align 8
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8
|
|
// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8
|
|
// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP18]], align 8
|
|
// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8
|
|
// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8
|
|
// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8
|
|
// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK18-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32
|
|
// CHECK18-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]])
|
|
// CHECK18-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
|
|
// CHECK18: omp_offload.failed3:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]]
|
|
// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT4]]
|
|
// CHECK18: omp_offload.cont4:
|
|
// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: ret i32 [[TMP30]]
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
|
// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
|
|
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
|
|
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
|
// CHECK18-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK18-NEXT: store double 2.500000e+00, double* [[A]], align 8
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
|
// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
|
// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
|
// CHECK18-SAME: () #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20)
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*))
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
|
// CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
|
|
// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11
|
|
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
|
|
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK18-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK19-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK19-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1**
|
|
// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double**
|
|
// CHECK19-NEXT: store double* [[A]], double** [[TMP9]], align 4
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP10]], align 4
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK19: omp_offload.failed:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK19: omp_offload.cont:
|
|
// CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1**
|
|
// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4
|
|
// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double**
|
|
// CHECK19-NEXT: store double* [[A2]], double** [[TMP29]], align 4
|
|
// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4
|
|
// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024)
|
|
// CHECK19-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
|
|
// CHECK19: omp_offload.failed6:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]]
|
|
// CHECK19: omp_offload.cont7:
|
|
// CHECK19-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32
|
|
// CHECK19-NEXT: ret i32 [[CONV]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP7]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]])
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK19: omp_offload.failed:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK19: omp_offload.cont:
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]]
|
|
// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
|
|
// CHECK19: omp_offload.failed6:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]]
|
|
// CHECK19: omp_offload.cont7:
|
|
// CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1
|
|
// CHECK19-NEXT: ret i32 [[ADD8]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20)
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK19: omp_offload.failed:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK19: omp_offload.cont:
|
|
// CHECK19-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
|
|
// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16*
|
|
// CHECK19-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP13]], align 4
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP18]], align 4
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK19-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32
|
|
// CHECK19-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]])
|
|
// CHECK19-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]]
|
|
// CHECK19: omp_offload.failed2:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT3]]
|
|
// CHECK19: omp_offload.cont3:
|
|
// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: ret i32 [[TMP30]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
|
// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
|
|
// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
|
// CHECK19-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK19-NEXT: store double 2.500000e+00, double* [[A]], align 4
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
|
// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
|
// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
|
// CHECK19-SAME: () #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20)
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*))
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
|
// CHECK19-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
|
|
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
|
|
// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11
|
|
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
|
|
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK19-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK20-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK20-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1**
|
|
// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double**
|
|
// CHECK20-NEXT: store double* [[A]], double** [[TMP9]], align 4
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP10]], align 4
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4
|
|
// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4
|
|
// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4
|
|
// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4
|
|
// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4
|
|
// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
|
|
// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK20: omp_offload.failed:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK20: omp_offload.cont:
|
|
// CHECK20-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1**
|
|
// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4
|
|
// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double**
|
|
// CHECK20-NEXT: store double* [[A2]], double** [[TMP29]], align 4
|
|
// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4
|
|
// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024)
|
|
// CHECK20-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
|
|
// CHECK20: omp_offload.failed6:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]]
|
|
// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]]
|
|
// CHECK20: omp_offload.cont7:
|
|
// CHECK20-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32
|
|
// CHECK20-NEXT: ret i32 [[CONV]]
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP7]], align 4
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]])
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK20: omp_offload.failed:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]]
|
|
// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK20: omp_offload.cont:
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]]
|
|
// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4
|
|
// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4
|
|
// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4
|
|
// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4
|
|
// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4
|
|
// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
|
|
// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
|
|
// CHECK20: omp_offload.failed6:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]]
|
|
// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]]
|
|
// CHECK20: omp_offload.cont7:
|
|
// CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1
|
|
// CHECK20-NEXT: ret i32 [[ADD8]]
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20)
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK20: omp_offload.failed:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]]
|
|
// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK20: omp_offload.cont:
|
|
// CHECK20-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
|
|
// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16*
|
|
// CHECK20-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP13]], align 4
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4
|
|
// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4
|
|
// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP18]], align 4
|
|
// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4
|
|
// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4
|
|
// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP23]], align 4
|
|
// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK20-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32
|
|
// CHECK20-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]])
|
|
// CHECK20-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]]
|
|
// CHECK20: omp_offload.failed2:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]]
|
|
// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT3]]
|
|
// CHECK20: omp_offload.cont3:
|
|
// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: ret i32 [[TMP30]]
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
|
// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
|
|
// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
|
// CHECK20-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK20-NEXT: store double 2.500000e+00, double* [[A]], align 4
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
|
// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
|
// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
|
// CHECK20-SAME: () #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20)
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*))
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
|
// CHECK20-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
|
|
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
|
|
// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11
|
|
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
|
|
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK20-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK21-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
|
|
// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
|
|
// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
|
|
// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK21-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK21-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK21-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK21-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
|
|
// CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK21-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK21-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK21-NEXT: store double 2.500000e+00, double* [[A2]], align 8
|
|
// CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK21-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8
|
|
// CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32
|
|
// CHECK21-NEXT: ret i32 [[CONV4]]
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]]
|
|
// CHECK21-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK21-NEXT: ret i32 [[ADD2]]
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK21-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK21-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK21-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
|
|
// CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK21-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK22-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
|
|
// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
|
|
// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
|
|
// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK22-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK22-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK22-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK22-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
|
|
// CHECK22-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK22-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK22-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK22-NEXT: store double 2.500000e+00, double* [[A2]], align 8
|
|
// CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK22-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8
|
|
// CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32
|
|
// CHECK22-NEXT: ret i32 [[CONV4]]
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]]
|
|
// CHECK22-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK22-NEXT: ret i32 [[ADD2]]
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK22-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK22-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK22-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
|
|
// CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK22-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
|
|
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
|
|
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
|
|
// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK23-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK23-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK23-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
|
|
// CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK23-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK23-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK23-NEXT: store double 2.500000e+00, double* [[A2]], align 4
|
|
// CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK23-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4
|
|
// CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32
|
|
// CHECK23-NEXT: ret i32 [[CONV4]]
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]]
|
|
// CHECK23-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK23-NEXT: ret i32 [[ADD2]]
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK23-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK23-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
|
|
// CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK23-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
|
|
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
|
|
// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
|
|
// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK24-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK24-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK24-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
|
|
// CHECK24-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK24-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK24-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK24-NEXT: store double 2.500000e+00, double* [[A2]], align 4
|
|
// CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK24-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4
|
|
// CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32
|
|
// CHECK24-NEXT: ret i32 [[CONV4]]
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]]
|
|
// CHECK24-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK24-NEXT: ret i32 [[ADD2]]
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK24-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK24-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
|
|
// CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK24-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
|
// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
|
|
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
|
// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
|
// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
|
|
// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
|
|
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
|
// CHECK25-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
|
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK25-NEXT: store double 2.500000e+00, double* [[A]], align 8
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
|
// CHECK25-SAME: () #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20)
|
|
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
|
// CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
|
|
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
|
|
// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
|
|
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
|
|
// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
|
// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
|
|
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
|
// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
|
// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]])
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
|
|
// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
|
|
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
|
// CHECK26-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
|
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK26-NEXT: store double 2.500000e+00, double* [[A]], align 8
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
|
// CHECK26-SAME: () #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20)
|
|
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
|
// CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
|
|
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
|
|
// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
|
|
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]])
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
|
|
// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
|
// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
|
|
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
|
// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
|
// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]])
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
|
|
// CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
|
// CHECK27-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
|
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK27-NEXT: store double 2.500000e+00, double* [[A]], align 4
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
|
// CHECK27-SAME: () #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20)
|
|
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
|
// CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
|
|
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
|
|
// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
|
|
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
|
|
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
|
// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
|
|
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
|
// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
|
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
|
// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]])
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
|
|
// CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
|
// CHECK28-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
|
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK28-NEXT: store double 2.500000e+00, double* [[A]], align 4
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
|
// CHECK28-SAME: () #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20)
|
|
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
|
// CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
|
|
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
|
|
// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
|
|
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]])
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
|
|
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK29-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK29-NEXT: entry:
|
|
// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
|
|
// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
|
|
// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
|
|
// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK29-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK29-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK29-NEXT: entry:
|
|
// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK29-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK29-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK29-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
|
|
// CHECK29-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK29-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK29-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK29-NEXT: store double 2.500000e+00, double* [[A2]], align 8
|
|
// CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK29-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8
|
|
// CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32
|
|
// CHECK29-NEXT: ret i32 [[CONV4]]
|
|
//
|
|
//
|
|
// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK29-NEXT: entry:
|
|
// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]]
|
|
// CHECK29-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK29-NEXT: ret i32 [[ADD2]]
|
|
//
|
|
//
|
|
// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK29-NEXT: entry:
|
|
// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK29-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK29-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK29-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
|
|
// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK29-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
//
|
|
// CHECK30-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK30-NEXT: entry:
|
|
// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
|
|
// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
|
|
// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
|
|
// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK30-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK30-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK30-NEXT: entry:
|
|
// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK30-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK30-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK30-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
|
|
// CHECK30-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK30-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK30-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK30-NEXT: store double 2.500000e+00, double* [[A2]], align 8
|
|
// CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK30-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8
|
|
// CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32
|
|
// CHECK30-NEXT: ret i32 [[CONV4]]
|
|
//
|
|
//
|
|
// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK30-NEXT: entry:
|
|
// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]]
|
|
// CHECK30-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK30-NEXT: ret i32 [[ADD2]]
|
|
//
|
|
//
|
|
// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK30-NEXT: entry:
|
|
// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK30-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK30-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK30-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
|
|
// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK30-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
//
|
|
// CHECK31-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK31-NEXT: entry:
|
|
// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
|
|
// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
|
|
// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
|
|
// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK31-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK31-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK31-NEXT: entry:
|
|
// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK31-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK31-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK31-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
|
|
// CHECK31-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK31-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK31-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK31-NEXT: store double 2.500000e+00, double* [[A2]], align 4
|
|
// CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK31-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4
|
|
// CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32
|
|
// CHECK31-NEXT: ret i32 [[CONV4]]
|
|
//
|
|
//
|
|
// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK31-NEXT: entry:
|
|
// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]]
|
|
// CHECK31-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK31-NEXT: ret i32 [[ADD2]]
|
|
//
|
|
//
|
|
// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK31-NEXT: entry:
|
|
// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK31-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK31-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK31-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
|
|
// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK31-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
//
|
|
// CHECK32-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK32-NEXT: entry:
|
|
// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
|
|
// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
|
|
// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
|
|
// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK32-NEXT: ret i32 [[TMP6]]
|
|
//
|
|
//
|
|
// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK32-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK32-NEXT: entry:
|
|
// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK32-NEXT: store i32 1, i32* [[B]], align 4
|
|
// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK32-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]]
|
|
// CHECK32-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
|
|
// CHECK32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK32-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK32-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK32-NEXT: store double 2.500000e+00, double* [[A2]], align 4
|
|
// CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK32-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4
|
|
// CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32
|
|
// CHECK32-NEXT: ret i32 [[CONV4]]
|
|
//
|
|
//
|
|
// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK32-NEXT: entry:
|
|
// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]]
|
|
// CHECK32-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK32-NEXT: ret i32 [[ADD2]]
|
|
//
|
|
//
|
|
// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK32-NEXT: entry:
|
|
// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[B:%.*]] = alloca i16, align 2
|
|
// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
|
// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK32-NEXT: store i16 1, i16* [[B]], align 2
|
|
// CHECK32-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK32-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2
|
|
// CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2
|
|
// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
|
|
// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK32-NEXT: ret i32 [[TMP3]]
|
|
//
|