Tatyana Krasnukha f665f6a279 [ARC] Add instruction subset for the ARC backend. ... Reviewers: petecoup, kparzysz Reviewed By: petecoup Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37983 llvm-svn: 319609		2017-12-02 05:25:17 +00:00
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AArch64	[AArch64][TableGen] Skip tied result operands for InstAlias	2017-11-20 14:36:40 +00:00
AMDGPU	[AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodes	2017-11-27 17:14:35 +00:00
ARC	[ARC] Add instruction subset for the ARC backend.	2017-12-02 05:25:17 +00:00
ARM	[ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode	2017-10-18 14:47:37 +00:00
Hexagon	[Hexagon] Remove trailing spaces, NFC	2017-11-22 20:43:00 +00:00
Lanai	[lanai] Add Lanai backend.	2016-03-28 13:09:54 +00:00
Mips	Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."	2017-11-14 22:26:42 +00:00
PowerPC	[Power9] Add missing Power9 instructions.	2017-09-19 15:22:36 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ	[SystemZ] Add support for IBM z14 processor (3/3)	2017-07-17 17:44:20 +00:00
X86	Avoid unecessary opsize byte in segment move to memory	2017-11-21 19:28:13 +00:00
XCore	…