forked from OSchip/llvm-project
816 lines
30 KiB
C++
816 lines
30 KiB
C++
//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. --*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is responsible for emitting a description of the target
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// instruction set for the code generator.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenDAGPatterns.h"
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#include "CodeGenInstruction.h"
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#include "CodeGenSchedule.h"
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#include "CodeGenTarget.h"
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#include "PredicateExpander.h"
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#include "SequenceToOffsetTable.h"
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#include "TableGenBackends.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <cassert>
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#include <cstdint>
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#include <map>
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#include <string>
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#include <utility>
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#include <vector>
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using namespace llvm;
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namespace {
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class InstrInfoEmitter {
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RecordKeeper &Records;
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CodeGenDAGPatterns CDP;
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const CodeGenSchedModels &SchedModels;
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public:
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InstrInfoEmitter(RecordKeeper &R):
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Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
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// run - Output the instruction set description.
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void run(raw_ostream &OS);
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private:
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void emitEnums(raw_ostream &OS);
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typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
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/// The keys of this map are maps which have OpName enum values as their keys
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/// and instruction operand indices as their values. The values of this map
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/// are lists of instruction names.
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typedef std::map<std::map<unsigned, unsigned>,
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std::vector<std::string>> OpNameMapTy;
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typedef std::map<std::string, unsigned>::iterator StrUintMapIter;
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/// Generate member functions in the target-specific GenInstrInfo class.
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///
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/// This method is used to custom expand TIIPredicate definitions.
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/// See file llvm/Target/TargetInstPredicates.td for a description of what is
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/// a TIIPredicate and how to use it.
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void emitTIIHelperMethods(raw_ostream &OS, StringRef TargetName,
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bool ExpandDefinition = true);
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/// Expand TIIPredicate definitions to functions that accept a const MCInst
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/// reference.
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void emitMCIIHelperMethods(raw_ostream &OS, StringRef TargetName);
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void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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Record *InstrInfo,
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std::map<std::vector<Record*>, unsigned> &EL,
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const OperandInfoMapTy &OpInfo,
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raw_ostream &OS);
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void emitOperandTypeMappings(
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raw_ostream &OS, const CodeGenTarget &Target,
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ArrayRef<const CodeGenInstruction *> NumberedInstructions);
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void initOperandMapData(
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ArrayRef<const CodeGenInstruction *> NumberedInstructions,
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StringRef Namespace,
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std::map<std::string, unsigned> &Operands,
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OpNameMapTy &OperandMap);
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void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target,
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ArrayRef<const CodeGenInstruction*> NumberedInstructions);
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// Operand information.
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void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
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std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
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};
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} // end anonymous namespace
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static void PrintDefList(const std::vector<Record*> &Uses,
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unsigned Num, raw_ostream &OS) {
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OS << "static const MCPhysReg ImplicitList" << Num << "[] = { ";
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for (Record *U : Uses)
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OS << getQualifiedName(U) << ", ";
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OS << "0 };\n";
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}
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//===----------------------------------------------------------------------===//
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// Operand Info Emission.
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//===----------------------------------------------------------------------===//
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std::vector<std::string>
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InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
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std::vector<std::string> Result;
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for (auto &Op : Inst.Operands) {
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// Handle aggregate operands and normal operands the same way by expanding
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// either case into a list of operands for this op.
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std::vector<CGIOperandList::OperandInfo> OperandList;
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// This might be a multiple operand thing. Targets like X86 have
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// registers in their multi-operand operands. It may also be an anonymous
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// operand, which has a single operand, but no declared class for the
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// operand.
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DagInit *MIOI = Op.MIOperandInfo;
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if (!MIOI || MIOI->getNumArgs() == 0) {
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// Single, anonymous, operand.
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OperandList.push_back(Op);
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} else {
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for (unsigned j = 0, e = Op.MINumOperands; j != e; ++j) {
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OperandList.push_back(Op);
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auto *OpR = cast<DefInit>(MIOI->getArg(j))->getDef();
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OperandList.back().Rec = OpR;
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}
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}
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for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
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Record *OpR = OperandList[j].Rec;
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std::string Res;
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if (OpR->isSubClassOf("RegisterOperand"))
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OpR = OpR->getValueAsDef("RegClass");
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if (OpR->isSubClassOf("RegisterClass"))
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Res += getQualifiedName(OpR) + "RegClassID, ";
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else if (OpR->isSubClassOf("PointerLikeRegClass"))
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Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
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else
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// -1 means the operand does not have a fixed register class.
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Res += "-1, ";
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// Fill in applicable flags.
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Res += "0";
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// Ptr value whose register class is resolved via callback.
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if (OpR->isSubClassOf("PointerLikeRegClass"))
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Res += "|(1<<MCOI::LookupPtrRegClass)";
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// Predicate operands. Check to see if the original unexpanded operand
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// was of type PredicateOp.
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if (Op.Rec->isSubClassOf("PredicateOp"))
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Res += "|(1<<MCOI::Predicate)";
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// Optional def operands. Check to see if the original unexpanded operand
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// was of type OptionalDefOperand.
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if (Op.Rec->isSubClassOf("OptionalDefOperand"))
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Res += "|(1<<MCOI::OptionalDef)";
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// Branch target operands. Check to see if the original unexpanded
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// operand was of type BranchTargetOperand.
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if (Op.Rec->isSubClassOf("BranchTargetOperand"))
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Res += "|(1<<MCOI::BranchTarget)";
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// Fill in operand type.
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Res += ", ";
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assert(!Op.OperandType.empty() && "Invalid operand type.");
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Res += Op.OperandType;
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// Fill in constraint info.
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Res += ", ";
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const CGIOperandList::ConstraintInfo &Constraint =
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Op.Constraints[j];
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if (Constraint.isNone())
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Res += "0";
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else if (Constraint.isEarlyClobber())
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Res += "(1 << MCOI::EARLY_CLOBBER)";
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else {
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assert(Constraint.isTied());
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Res += "((" + utostr(Constraint.getTiedOperand()) +
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" << 16) | (1 << MCOI::TIED_TO))";
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}
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Result.push_back(Res);
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}
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}
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return Result;
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}
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void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
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OperandInfoMapTy &OperandInfoIDs) {
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// ID #0 is for no operand info.
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unsigned OperandListNum = 0;
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OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
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OS << "\n";
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const CodeGenTarget &Target = CDP.getTargetInfo();
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for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
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std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
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unsigned &N = OperandInfoIDs[OperandInfo];
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if (N != 0) continue;
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N = ++OperandListNum;
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OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
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for (const std::string &Info : OperandInfo)
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OS << "{ " << Info << " }, ";
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OS << "};\n";
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}
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}
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/// Initialize data structures for generating operand name mappings.
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///
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/// \param Operands [out] A map used to generate the OpName enum with operand
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/// names as its keys and operand enum values as its values.
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/// \param OperandMap [out] A map for representing the operand name mappings for
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/// each instructions. This is used to generate the OperandMap table as
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/// well as the getNamedOperandIdx() function.
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void InstrInfoEmitter::initOperandMapData(
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ArrayRef<const CodeGenInstruction *> NumberedInstructions,
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StringRef Namespace,
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std::map<std::string, unsigned> &Operands,
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OpNameMapTy &OperandMap) {
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unsigned NumOperands = 0;
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for (const CodeGenInstruction *Inst : NumberedInstructions) {
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if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
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continue;
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std::map<unsigned, unsigned> OpList;
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for (const auto &Info : Inst->Operands) {
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StrUintMapIter I = Operands.find(Info.Name);
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if (I == Operands.end()) {
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I = Operands.insert(Operands.begin(),
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std::pair<std::string, unsigned>(Info.Name, NumOperands++));
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}
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OpList[I->second] = Info.MIOperandNo;
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}
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OperandMap[OpList].push_back(Namespace.str() + "::" +
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Inst->TheDef->getName().str());
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}
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}
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/// Generate a table and function for looking up the indices of operands by
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/// name.
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///
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/// This code generates:
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/// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry
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/// for each operand name.
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/// - A 2-dimensional table called OperandMap for mapping OpName enum values to
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/// operand indices.
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/// - A function called getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
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/// for looking up the operand index for an instruction, given a value from
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/// OpName enum
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void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS,
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const CodeGenTarget &Target,
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ArrayRef<const CodeGenInstruction*> NumberedInstructions) {
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StringRef Namespace = Target.getInstNamespace();
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std::string OpNameNS = "OpName";
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// Map of operand names to their enumeration value. This will be used to
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// generate the OpName enum.
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std::map<std::string, unsigned> Operands;
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OpNameMapTy OperandMap;
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initOperandMapData(NumberedInstructions, Namespace, Operands, OperandMap);
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OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n";
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OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n";
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OS << "namespace llvm {\n";
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OS << "namespace " << Namespace << " {\n";
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OS << "namespace " << OpNameNS << " {\n";
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OS << "enum {\n";
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for (const auto &Op : Operands)
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OS << " " << Op.first << " = " << Op.second << ",\n";
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OS << "OPERAND_LAST";
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OS << "\n};\n";
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OS << "} // end namespace OpName\n";
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OS << "} // end namespace " << Namespace << "\n";
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OS << "} // end namespace llvm\n";
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OS << "#endif //GET_INSTRINFO_OPERAND_ENUM\n\n";
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OS << "#ifdef GET_INSTRINFO_NAMED_OPS\n";
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OS << "#undef GET_INSTRINFO_NAMED_OPS\n";
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OS << "namespace llvm {\n";
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OS << "namespace " << Namespace << " {\n";
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OS << "LLVM_READONLY\n";
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OS << "int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {\n";
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if (!Operands.empty()) {
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OS << " static const int16_t OperandMap [][" << Operands.size()
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<< "] = {\n";
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for (const auto &Entry : OperandMap) {
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const std::map<unsigned, unsigned> &OpList = Entry.first;
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OS << "{";
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// Emit a row of the OperandMap table
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for (unsigned i = 0, e = Operands.size(); i != e; ++i)
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OS << (OpList.count(i) == 0 ? -1 : (int)OpList.find(i)->second) << ", ";
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OS << "},\n";
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}
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OS << "};\n";
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OS << " switch(Opcode) {\n";
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unsigned TableIndex = 0;
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for (const auto &Entry : OperandMap) {
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for (const std::string &Name : Entry.second)
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OS << " case " << Name << ":\n";
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OS << " return OperandMap[" << TableIndex++ << "][NamedIdx];\n";
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}
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OS << " default: return -1;\n";
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OS << " }\n";
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} else {
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// There are no operands, so no need to emit anything
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OS << " return -1;\n";
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}
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OS << "}\n";
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OS << "} // end namespace " << Namespace << "\n";
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OS << "} // end namespace llvm\n";
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OS << "#endif //GET_INSTRINFO_NAMED_OPS\n\n";
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}
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/// Generate an enum for all the operand types for this target, under the
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/// llvm::TargetNamespace::OpTypes namespace.
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/// Operand types are all definitions derived of the Operand Target.td class.
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void InstrInfoEmitter::emitOperandTypeMappings(
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raw_ostream &OS, const CodeGenTarget &Target,
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ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
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StringRef Namespace = Target.getInstNamespace();
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std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand");
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std::vector<Record *> RegisterOperands =
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Records.getAllDerivedDefinitions("RegisterOperand");
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std::vector<Record *> RegisterClasses =
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Records.getAllDerivedDefinitions("RegisterClass");
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OS << "#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
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OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
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OS << "namespace llvm {\n";
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OS << "namespace " << Namespace << " {\n";
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OS << "namespace OpTypes {\n";
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OS << "enum OperandType {\n";
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unsigned EnumVal = 0;
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for (const std::vector<Record *> *RecordsToAdd :
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{&Operands, &RegisterOperands, &RegisterClasses}) {
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for (const Record *Op : *RecordsToAdd) {
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if (!Op->isAnonymous())
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OS << " " << Op->getName() << " = " << EnumVal << ",\n";
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++EnumVal;
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}
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}
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OS << " OPERAND_TYPE_LIST_END" << "\n};\n";
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OS << "} // end namespace OpTypes\n";
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OS << "} // end namespace " << Namespace << "\n";
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OS << "} // end namespace llvm\n";
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OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n\n";
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OS << "#ifdef GET_INSTRINFO_OPERAND_TYPE\n";
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OS << "#undef GET_INSTRINFO_OPERAND_TYPE\n";
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OS << "namespace llvm {\n";
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OS << "namespace " << Namespace << " {\n";
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OS << "LLVM_READONLY\n";
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OS << "static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {\n";
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// TODO: Factor out instructions with same operands to compress the tables.
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if (!NumberedInstructions.empty()) {
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std::vector<int> OperandOffsets;
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std::vector<Record *> OperandRecords;
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int CurrentOffset = 0;
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for (const CodeGenInstruction *Inst : NumberedInstructions) {
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OperandOffsets.push_back(CurrentOffset);
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for (const auto &Op : Inst->Operands) {
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const DagInit *MIOI = Op.MIOperandInfo;
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if (!MIOI || MIOI->getNumArgs() == 0) {
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// Single, anonymous, operand.
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OperandRecords.push_back(Op.Rec);
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++CurrentOffset;
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} else {
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for (Init *Arg : make_range(MIOI->arg_begin(), MIOI->arg_end())) {
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OperandRecords.push_back(cast<DefInit>(Arg)->getDef());
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++CurrentOffset;
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}
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}
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}
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}
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// Emit the table of offsets for the opcode lookup.
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OS << " const int Offsets[] = {\n";
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for (int I = 0, E = OperandOffsets.size(); I != E; ++I)
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OS << " " << OperandOffsets[I] << ",\n";
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OS << " };\n";
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// Add an entry for the end so that we don't need to special case it below.
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OperandOffsets.push_back(OperandRecords.size());
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// Emit the actual operand types in a flat table.
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OS << " const int OpcodeOperandTypes[] = {\n ";
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for (int I = 0, E = OperandRecords.size(), CurOffset = 1; I != E; ++I) {
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// We print each Opcode's operands in its own row.
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if (I == OperandOffsets[CurOffset]) {
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OS << "\n ";
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// If there are empty rows, mark them with an empty comment.
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while (OperandOffsets[++CurOffset] == I)
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OS << "/**/\n ";
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}
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Record *OpR = OperandRecords[I];
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if ((OpR->isSubClassOf("Operand") ||
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OpR->isSubClassOf("RegisterOperand") ||
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OpR->isSubClassOf("RegisterClass")) &&
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!OpR->isAnonymous())
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OS << "OpTypes::" << OpR->getName();
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else
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OS << -1;
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OS << ", ";
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}
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OS << "\n };\n";
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OS << " return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];\n";
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} else {
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OS << " llvm_unreachable(\"No instructions defined\");\n";
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}
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OS << "}\n";
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OS << "} // end namespace " << Namespace << "\n";
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OS << "} // end namespace llvm\n";
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OS << "#endif // GET_INSTRINFO_OPERAND_TYPE\n\n";
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}
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void InstrInfoEmitter::emitMCIIHelperMethods(raw_ostream &OS,
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StringRef TargetName) {
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RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
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if (TIIPredicates.empty())
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return;
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OS << "#ifdef GET_INSTRINFO_MC_HELPER_DECLS\n";
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OS << "#undef GET_INSTRINFO_MC_HELPER_DECLS\n\n";
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OS << "namespace llvm {\n";
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OS << "class MCInst;\n\n";
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OS << "namespace " << TargetName << "_MC {\n\n";
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for (const Record *Rec : TIIPredicates) {
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OS << "bool " << Rec->getValueAsString("FunctionName")
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<< "(const MCInst &MI);\n";
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}
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OS << "\n} // end namespace " << TargetName << "_MC\n";
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OS << "} // end namespace llvm\n\n";
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OS << "#endif // GET_INSTRINFO_MC_HELPER_DECLS\n\n";
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OS << "#ifdef GET_INSTRINFO_MC_HELPERS\n";
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OS << "#undef GET_INSTRINFO_MC_HELPERS\n\n";
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OS << "namespace llvm {\n";
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OS << "namespace " << TargetName << "_MC {\n\n";
|
|
|
|
PredicateExpander PE(TargetName);
|
|
PE.setExpandForMC(true);
|
|
|
|
for (const Record *Rec : TIIPredicates) {
|
|
OS << "bool " << Rec->getValueAsString("FunctionName");
|
|
OS << "(const MCInst &MI) {\n";
|
|
|
|
OS.indent(PE.getIndentLevel() * 2);
|
|
PE.expandStatement(OS, Rec->getValueAsDef("Body"));
|
|
OS << "\n}\n\n";
|
|
}
|
|
|
|
OS << "} // end namespace " << TargetName << "_MC\n";
|
|
OS << "} // end namespace llvm\n\n";
|
|
|
|
OS << "#endif // GET_GENISTRINFO_MC_HELPERS\n";
|
|
}
|
|
|
|
void InstrInfoEmitter::emitTIIHelperMethods(raw_ostream &OS,
|
|
StringRef TargetName,
|
|
bool ExpandDefinition) {
|
|
RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
|
|
if (TIIPredicates.empty())
|
|
return;
|
|
|
|
PredicateExpander PE(TargetName);
|
|
PE.setExpandForMC(false);
|
|
|
|
for (const Record *Rec : TIIPredicates) {
|
|
OS << (ExpandDefinition ? "" : "static ") << "bool ";
|
|
if (ExpandDefinition)
|
|
OS << TargetName << "InstrInfo::";
|
|
OS << Rec->getValueAsString("FunctionName");
|
|
OS << "(const MachineInstr &MI)";
|
|
if (!ExpandDefinition) {
|
|
OS << ";\n";
|
|
continue;
|
|
}
|
|
|
|
OS << " {\n";
|
|
OS.indent(PE.getIndentLevel() * 2);
|
|
PE.expandStatement(OS, Rec->getValueAsDef("Body"));
|
|
OS << "\n}\n\n";
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Main Output.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// run - Emit the main instruction description records for the target...
|
|
void InstrInfoEmitter::run(raw_ostream &OS) {
|
|
emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS);
|
|
emitEnums(OS);
|
|
|
|
OS << "#ifdef GET_INSTRINFO_MC_DESC\n";
|
|
OS << "#undef GET_INSTRINFO_MC_DESC\n";
|
|
|
|
OS << "namespace llvm {\n\n";
|
|
|
|
CodeGenTarget &Target = CDP.getTargetInfo();
|
|
const std::string &TargetName = Target.getName();
|
|
Record *InstrInfo = Target.getInstructionSet();
|
|
|
|
// Keep track of all of the def lists we have emitted already.
|
|
std::map<std::vector<Record*>, unsigned> EmittedLists;
|
|
unsigned ListNumber = 0;
|
|
|
|
// Emit all of the instruction's implicit uses and defs.
|
|
for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
|
|
Record *Inst = II->TheDef;
|
|
std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
|
|
if (!Uses.empty()) {
|
|
unsigned &IL = EmittedLists[Uses];
|
|
if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
|
|
}
|
|
std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
|
|
if (!Defs.empty()) {
|
|
unsigned &IL = EmittedLists[Defs];
|
|
if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
|
|
}
|
|
}
|
|
|
|
OperandInfoMapTy OperandInfoIDs;
|
|
|
|
// Emit all of the operand info records.
|
|
EmitOperandInfo(OS, OperandInfoIDs);
|
|
|
|
// Emit all of the MCInstrDesc records in their ENUM ordering.
|
|
//
|
|
OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
|
|
ArrayRef<const CodeGenInstruction*> NumberedInstructions =
|
|
Target.getInstructionsByEnumValue();
|
|
|
|
SequenceToOffsetTable<std::string> InstrNames;
|
|
unsigned Num = 0;
|
|
for (const CodeGenInstruction *Inst : NumberedInstructions) {
|
|
// Keep a list of the instruction names.
|
|
InstrNames.add(Inst->TheDef->getName());
|
|
// Emit the record into the table.
|
|
emitRecord(*Inst, Num++, InstrInfo, EmittedLists, OperandInfoIDs, OS);
|
|
}
|
|
OS << "};\n\n";
|
|
|
|
// Emit the array of instruction names.
|
|
InstrNames.layout();
|
|
OS << "extern const char " << TargetName << "InstrNameData[] = {\n";
|
|
InstrNames.emit(OS, printChar);
|
|
OS << "};\n\n";
|
|
|
|
OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {";
|
|
Num = 0;
|
|
for (const CodeGenInstruction *Inst : NumberedInstructions) {
|
|
// Newline every eight entries.
|
|
if (Num % 8 == 0)
|
|
OS << "\n ";
|
|
OS << InstrNames.get(Inst->TheDef->getName()) << "U, ";
|
|
++Num;
|
|
}
|
|
|
|
OS << "\n};\n\n";
|
|
|
|
// MCInstrInfo initialization routine.
|
|
OS << "static inline void Init" << TargetName
|
|
<< "MCInstrInfo(MCInstrInfo *II) {\n";
|
|
OS << " II->InitMCInstrInfo(" << TargetName << "Insts, "
|
|
<< TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
|
|
<< NumberedInstructions.size() << ");\n}\n\n";
|
|
|
|
OS << "} // end namespace llvm\n";
|
|
|
|
OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
|
|
|
|
// Create a TargetInstrInfo subclass to hide the MC layer initialization.
|
|
OS << "#ifdef GET_INSTRINFO_HEADER\n";
|
|
OS << "#undef GET_INSTRINFO_HEADER\n";
|
|
|
|
std::string ClassName = TargetName + "GenInstrInfo";
|
|
OS << "namespace llvm {\n";
|
|
OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
|
|
<< " explicit " << ClassName
|
|
<< "(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);\n"
|
|
<< " ~" << ClassName << "() override = default;\n";
|
|
|
|
|
|
OS << "\n};\n} // end namespace llvm\n";
|
|
|
|
OS << "#endif // GET_INSTRINFO_HEADER\n\n";
|
|
|
|
OS << "#ifdef GET_INSTRINFO_HELPER_DECLS\n";
|
|
OS << "#undef GET_INSTRINFO_HELPER_DECLS\n\n";
|
|
emitTIIHelperMethods(OS, TargetName, /* ExpandDefintion = */false);
|
|
OS << "\n";
|
|
OS << "#endif // GET_INSTRINFO_HELPER_DECLS\n\n";
|
|
|
|
OS << "#ifdef GET_INSTRINFO_HELPERS\n";
|
|
OS << "#undef GET_INSTRINFO_HELPERS\n\n";
|
|
emitTIIHelperMethods(OS, TargetName, /* ExpandDefintion = */true);
|
|
OS << "#endif // GET_INSTRINFO_HELPERS\n\n";
|
|
|
|
OS << "#ifdef GET_INSTRINFO_CTOR_DTOR\n";
|
|
OS << "#undef GET_INSTRINFO_CTOR_DTOR\n";
|
|
|
|
OS << "namespace llvm {\n";
|
|
OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
|
|
OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
|
|
OS << "extern const char " << TargetName << "InstrNameData[];\n";
|
|
OS << ClassName << "::" << ClassName
|
|
<< "(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)\n"
|
|
<< " : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {\n"
|
|
<< " InitMCInstrInfo(" << TargetName << "Insts, " << TargetName
|
|
<< "InstrNameIndices, " << TargetName << "InstrNameData, "
|
|
<< NumberedInstructions.size() << ");\n}\n";
|
|
OS << "} // end namespace llvm\n";
|
|
|
|
OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n";
|
|
|
|
emitOperandNameMappings(OS, Target, NumberedInstructions);
|
|
|
|
emitOperandTypeMappings(OS, Target, NumberedInstructions);
|
|
|
|
emitMCIIHelperMethods(OS, TargetName);
|
|
}
|
|
|
|
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
|
|
Record *InstrInfo,
|
|
std::map<std::vector<Record*>, unsigned> &EmittedLists,
|
|
const OperandInfoMapTy &OpInfo,
|
|
raw_ostream &OS) {
|
|
int MinOperands = 0;
|
|
if (!Inst.Operands.empty())
|
|
// Each logical operand can be multiple MI operands.
|
|
MinOperands = Inst.Operands.back().MIOperandNo +
|
|
Inst.Operands.back().MINumOperands;
|
|
|
|
OS << " { ";
|
|
OS << Num << ",\t" << MinOperands << ",\t"
|
|
<< Inst.Operands.NumDefs << ",\t"
|
|
<< Inst.TheDef->getValueAsInt("Size") << ",\t"
|
|
<< SchedModels.getSchedClassIdx(Inst) << ",\t0";
|
|
|
|
CodeGenTarget &Target = CDP.getTargetInfo();
|
|
|
|
// Emit all of the target independent flags...
|
|
if (Inst.isPreISelOpcode) OS << "|(1ULL<<MCID::PreISelOpcode)";
|
|
if (Inst.isPseudo) OS << "|(1ULL<<MCID::Pseudo)";
|
|
if (Inst.isReturn) OS << "|(1ULL<<MCID::Return)";
|
|
if (Inst.isEHScopeReturn) OS << "|(1ULL<<MCID::EHScopeReturn)";
|
|
if (Inst.isBranch) OS << "|(1ULL<<MCID::Branch)";
|
|
if (Inst.isIndirectBranch) OS << "|(1ULL<<MCID::IndirectBranch)";
|
|
if (Inst.isCompare) OS << "|(1ULL<<MCID::Compare)";
|
|
if (Inst.isMoveImm) OS << "|(1ULL<<MCID::MoveImm)";
|
|
if (Inst.isMoveReg) OS << "|(1ULL<<MCID::MoveReg)";
|
|
if (Inst.isBitcast) OS << "|(1ULL<<MCID::Bitcast)";
|
|
if (Inst.isAdd) OS << "|(1ULL<<MCID::Add)";
|
|
if (Inst.isTrap) OS << "|(1ULL<<MCID::Trap)";
|
|
if (Inst.isSelect) OS << "|(1ULL<<MCID::Select)";
|
|
if (Inst.isBarrier) OS << "|(1ULL<<MCID::Barrier)";
|
|
if (Inst.hasDelaySlot) OS << "|(1ULL<<MCID::DelaySlot)";
|
|
if (Inst.isCall) OS << "|(1ULL<<MCID::Call)";
|
|
if (Inst.canFoldAsLoad) OS << "|(1ULL<<MCID::FoldableAsLoad)";
|
|
if (Inst.mayLoad) OS << "|(1ULL<<MCID::MayLoad)";
|
|
if (Inst.mayStore) OS << "|(1ULL<<MCID::MayStore)";
|
|
if (Inst.mayRaiseFPException) OS << "|(1ULL<<MCID::MayRaiseFPException)";
|
|
if (Inst.isPredicable) OS << "|(1ULL<<MCID::Predicable)";
|
|
if (Inst.isConvertibleToThreeAddress) OS << "|(1ULL<<MCID::ConvertibleTo3Addr)";
|
|
if (Inst.isCommutable) OS << "|(1ULL<<MCID::Commutable)";
|
|
if (Inst.isTerminator) OS << "|(1ULL<<MCID::Terminator)";
|
|
if (Inst.isReMaterializable) OS << "|(1ULL<<MCID::Rematerializable)";
|
|
if (Inst.isNotDuplicable) OS << "|(1ULL<<MCID::NotDuplicable)";
|
|
if (Inst.Operands.hasOptionalDef) OS << "|(1ULL<<MCID::HasOptionalDef)";
|
|
if (Inst.usesCustomInserter) OS << "|(1ULL<<MCID::UsesCustomInserter)";
|
|
if (Inst.hasPostISelHook) OS << "|(1ULL<<MCID::HasPostISelHook)";
|
|
if (Inst.Operands.isVariadic)OS << "|(1ULL<<MCID::Variadic)";
|
|
if (Inst.hasSideEffects) OS << "|(1ULL<<MCID::UnmodeledSideEffects)";
|
|
if (Inst.isAsCheapAsAMove) OS << "|(1ULL<<MCID::CheapAsAMove)";
|
|
if (!Target.getAllowRegisterRenaming() || Inst.hasExtraSrcRegAllocReq)
|
|
OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)";
|
|
if (!Target.getAllowRegisterRenaming() || Inst.hasExtraDefRegAllocReq)
|
|
OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)";
|
|
if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)";
|
|
if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)";
|
|
if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)";
|
|
if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)";
|
|
if (Inst.variadicOpsAreDefs) OS << "|(1ULL<<MCID::VariadicOpsAreDefs)";
|
|
if (Inst.isAuthenticated) OS << "|(1ULL<<MCID::Authenticated)";
|
|
|
|
// Emit all of the target-specific flags...
|
|
BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
|
|
if (!TSF)
|
|
PrintFatalError(Inst.TheDef->getLoc(), "no TSFlags?");
|
|
uint64_t Value = 0;
|
|
for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
|
|
if (const auto *Bit = dyn_cast<BitInit>(TSF->getBit(i)))
|
|
Value |= uint64_t(Bit->getValue()) << i;
|
|
else
|
|
PrintFatalError(Inst.TheDef->getLoc(),
|
|
"Invalid TSFlags bit in " + Inst.TheDef->getName());
|
|
}
|
|
OS << ", 0x";
|
|
OS.write_hex(Value);
|
|
OS << "ULL, ";
|
|
|
|
// Emit the implicit uses and defs lists...
|
|
std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
|
|
if (UseList.empty())
|
|
OS << "nullptr, ";
|
|
else
|
|
OS << "ImplicitList" << EmittedLists[UseList] << ", ";
|
|
|
|
std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
|
|
if (DefList.empty())
|
|
OS << "nullptr, ";
|
|
else
|
|
OS << "ImplicitList" << EmittedLists[DefList] << ", ";
|
|
|
|
// Emit the operand info.
|
|
std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
|
|
if (OperandInfo.empty())
|
|
OS << "nullptr";
|
|
else
|
|
OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
|
|
|
|
if (Inst.HasComplexDeprecationPredicate)
|
|
// Emit a function pointer to the complex predicate method.
|
|
OS << ", -1 "
|
|
<< ",&get" << Inst.DeprecatedReason << "DeprecationInfo";
|
|
else if (!Inst.DeprecatedReason.empty())
|
|
// Emit the Subtarget feature.
|
|
OS << ", " << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
|
|
<< " ,nullptr";
|
|
else
|
|
// Instruction isn't deprecated.
|
|
OS << ", -1 ,nullptr";
|
|
|
|
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
|
|
}
|
|
|
|
// emitEnums - Print out enum values for all of the instructions.
|
|
void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
|
|
OS << "#ifdef GET_INSTRINFO_ENUM\n";
|
|
OS << "#undef GET_INSTRINFO_ENUM\n";
|
|
|
|
OS << "namespace llvm {\n\n";
|
|
|
|
CodeGenTarget Target(Records);
|
|
|
|
// We must emit the PHI opcode first...
|
|
StringRef Namespace = Target.getInstNamespace();
|
|
|
|
if (Namespace.empty())
|
|
PrintFatalError("No instructions defined!");
|
|
|
|
OS << "namespace " << Namespace << " {\n";
|
|
OS << " enum {\n";
|
|
unsigned Num = 0;
|
|
for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue())
|
|
OS << " " << Inst->TheDef->getName() << "\t= " << Num++ << ",\n";
|
|
OS << " INSTRUCTION_LIST_END = " << Num << "\n";
|
|
OS << " };\n\n";
|
|
OS << "} // end namespace " << Namespace << "\n";
|
|
OS << "} // end namespace llvm\n";
|
|
OS << "#endif // GET_INSTRINFO_ENUM\n\n";
|
|
|
|
OS << "#ifdef GET_INSTRINFO_SCHED_ENUM\n";
|
|
OS << "#undef GET_INSTRINFO_SCHED_ENUM\n";
|
|
OS << "namespace llvm {\n\n";
|
|
OS << "namespace " << Namespace << " {\n";
|
|
OS << "namespace Sched {\n";
|
|
OS << " enum {\n";
|
|
Num = 0;
|
|
for (const auto &Class : SchedModels.explicit_classes())
|
|
OS << " " << Class.Name << "\t= " << Num++ << ",\n";
|
|
OS << " SCHED_LIST_END = " << Num << "\n";
|
|
OS << " };\n";
|
|
OS << "} // end namespace Sched\n";
|
|
OS << "} // end namespace " << Namespace << "\n";
|
|
OS << "} // end namespace llvm\n";
|
|
|
|
OS << "#endif // GET_INSTRINFO_SCHED_ENUM\n\n";
|
|
}
|
|
|
|
namespace llvm {
|
|
|
|
void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
|
|
InstrInfoEmitter(RK).run(OS);
|
|
EmitMapTable(RK, OS);
|
|
}
|
|
|
|
} // end namespace llvm
|