Manman Ren 1be131ba27 X86: enable CSE between CMP and SUB ... We perform the following: 1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering. 2> Modify MachineCSE to correctly handle implicit defs. 3> Convert SUB back to CMP if possible at peephole. Removed pattern matching of (a>b) ? (a-b):0 and like, since they are handled by peephole now. rdar://11873276 llvm-svn: 161462		2012-08-08 00:51:41 +00:00
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ARM	Add stack spill / reload instructions for DTriple and DQuad register classes, which	2012-08-04 13:16:12 +00:00
CPP	test commit	2012-07-18 17:53:05 +00:00
CellSPU	Refactor and check "onlyReadsMemory" before optimizing builtins.	2012-08-03 23:29:17 +00:00
Generic	Fix a bug in the scalarization of BUILD_VECTOR. BUILD_VECTOR elements may be wider than the output element type. Make sure to trunc them if needed.	2012-07-15 20:39:08 +00:00
Hexagon	Refactor and check "onlyReadsMemory" before optimizing builtins.	2012-08-03 23:29:17 +00:00
MBlaze	Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu	2012-03-25 09:02:19 +00:00
MSP430	These tests used intrinsics with the wrong prototype. They weren't caught because	2012-05-27 19:35:41 +00:00
Mips	1. Redo mips16 instructions to avoid multiple opcodes for same instruction.	2012-08-03 22:57:02 +00:00
NVPTX	Add llvm.fabs intrinsic.	2012-05-28 21:48:37 +00:00
PowerPC	MFTB on PPC64 should really be encoded using MFSPR.	2012-08-06 21:21:44 +00:00
SPARC	test/CodeGen/SPARC/private.ll: Fixup. Forgot to prune old RUN lines.	2012-07-03 04:29:20 +00:00
Thumb	Fix the remaining TCL-style quotes found in the testsuite. This is	2012-07-02 19:09:46 +00:00
Thumb2	[arm-fast-isel] Add support for vararg function calls.	2012-07-19 09:49:00 +00:00
X86	X86: enable CSE between CMP and SUB	2012-08-08 00:51:41 +00:00
XCore	Fix pattern for MKMSK instruction.	2012-06-13 17:59:12 +00:00