maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/mlir/lib/Dialect
History
Aart Bik c8d5dcb035 [mlir][sparse] refactor loop sequence codegen 
This refactoring adds a few "event" functions (start/end loop-seq/loop) for
readability of the core function of codegen. This also prepares sparse tensor
output codegen, where these "event" functions will provide convenient
placeholders to start or stop insertion bookkeeping.

This revision also includes a few various minor changes that kept on
pending in my local workspace.

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D112506
 		2021-10-26 13:42:21 -07:00
..
AMX [mlir:OpConversionPattern] Add overloads for taking an Adaptor instead of ArrayRef 2021-09-24 17:51:41 +00:00
Affine [mlir] Switch arith, llvm, std & shape dialects to accessors prefixed both form. 2021-10-24 18:36:33 -07:00
Arithmetic [mlir] Switch arith, llvm, std & shape dialects to accessors prefixed both form. 2021-10-24 18:36:33 -07:00
ArmNeon [mlir] Generare .cpp.inc files for dialects. 2021-06-29 20:10:30 +00:00
ArmSVE [MLIR] Replace std ops with arith dialect ops 2021-10-13 03:07:03 +00:00
Async [mlir] Switch arith, llvm, std & shape dialects to accessors prefixed both form. 2021-10-24 18:36:33 -07:00
Complex [MLIR] Replace std ops with arith dialect ops 2021-10-13 03:07:03 +00:00
DLTI [ODS/AsmParser] Don't pass MLIRContext with DialectAsmParser. 2021-09-30 05:10:28 +00:00
EmitC [MLIR] Replace std ops with arith dialect ops 2021-10-13 03:07:03 +00:00
GPU [mlir][RFC] Refactor layout representation in MemRefType 2021-10-19 12:31:15 +03:00
LLVMIR [mlir] Switch arith, llvm, std & shape dialects to accessors prefixed both form. 2021-10-24 18:36:33 -07:00
Linalg [mlir][Linalg] Allow comprehensive bufferization to use callbacks for alloc/dealloc. 2021-10-25 12:43:10 -07:00
Math [mlir] Use float literals to make Windows build happy. 2021-10-26 21:36:04 +02:00
MemRef [mlir] Switch arith, llvm, std & shape dialects to accessors prefixed both form. 2021-10-24 18:36:33 -07:00
OpenACC [mlir] Switch arith, llvm, std & shape dialects to accessors prefixed both form. 2021-10-24 18:36:33 -07:00
OpenMP [mlir][OpenMP]Support for modifiers in workshare loops 2021-10-22 14:19:33 +01:00
PDL [ODS/AsmParser] Don't pass MLIRContext with DialectAsmParser. 2021-09-30 05:10:28 +00:00
PDLInterp [mlir] Generare .cpp.inc files for dialects. 2021-06-29 20:10:30 +00:00
Quant [MLIR] Replace std ops with arith dialect ops 2021-10-13 03:07:03 +00:00
SCF [mlir] Switch arith, llvm, std & shape dialects to accessors prefixed both form. 2021-10-24 18:36:33 -07:00
SPIRV [mlir][spirv] Add memory semantics verify for atomic operations 2021-10-14 00:00:55 +08:00
Shape [mlir] Switch arith, llvm, std & shape dialects to accessors prefixed both form. 2021-10-24 18:36:33 -07:00
SparseTensor [mlir][sparse] refactor loop sequence codegen 2021-10-26 13:42:21 -07:00
StandardOps [mlir] Fix getVectorReductionOp 2021-10-26 08:42:34 -07:00
Tensor [mlir] Switch arith, llvm, std & shape dialects to accessors prefixed both form. 2021-10-24 18:36:33 -07:00
Tosa [mlir][tosa] Correct tosa.avg_pool2d for specification error 2021-10-25 14:41:16 -07:00
Utils [mlir] Add an interface to allow operations to specify how they can be tiled. 2021-08-30 16:31:18 -07:00
Vector [mlir] Fix getVectorReductionOp 2021-10-26 08:42:34 -07:00
X86Vector [MLIR] Replace std ops with arith dialect ops 2021-10-13 03:07:03 +00:00
CMakeLists.txt [MLIR] Split arith dialect from the std dialect 2021-10-06 19:25:51 +00:00
Traits.cpp [mlir] Fix broadcasting check with 1 values 2021-07-11 20:41:33 -07:00