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llvm-project/llvm/test/MC/Disassembler/AMDGPU
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Sam Kolton a6792a39c4 [AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwa 
Summary: Real instruction should copy constraints from real instruction. This allows auto-generated disassembler to correctly process tied operands.

Reviewers: nhaustov, vpykhtin, tstellarAMD

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D27847

llvm-svn: 290336
 		2016-12-22 11:30:48 +00:00
..
dpp_vi.txt [AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwa 2016-12-22 11:30:48 +00:00
ds_vi.txt [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed. 2016-10-21 14:49:22 +00:00
flat_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
lit.local.cfg
…
literal16_vi.txt AMDGPU: Fix handling of 16-bit immediates 2016-12-10 00:39:12 +00:00
mov.txt
…
mubuf_vi.txt [AMDGPU][mc] Add support for buffer_load_dwordx3, buffer_store_dwordx3. 2016-10-07 15:53:16 +00:00
nop.txt
…
sdwa_vi.txt [AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwa 2016-12-22 11:30:48 +00:00
smem_vi.txt [AMDGPU] Disassembler: fix s_buffer_store_dword instructions 2016-12-05 09:58:51 +00:00
smrd_vi.txt [AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions. 2016-10-31 16:07:39 +00:00
sop1_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
sop2_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
sopc_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
sopk_vi.txt [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers. 2016-04-27 15:17:03 +00:00
sopp_vi.txt [AMDGPU][llvm-mc] Add support for sendmsg(...) syntax. 2016-05-06 17:48:48 +00:00
trap_vi.txt [AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers. 2016-05-24 12:05:16 +00:00
vintrp.txt AMDGPU: Change vintrp printing 2016-12-14 16:36:12 +00:00
vop1.txt AMDGPU: Fix handling of 16-bit immediates 2016-12-10 00:39:12 +00:00
vop1_vi.txt [AMDGPU] Add some VI disassembler tests missing from previous autogeneration due to different filecheck prefix. NFC. 2016-04-08 05:42:20 +00:00
vop2_vi.txt AMDGPU: Fix name for v_ashrrev_i16 2016-12-16 17:40:11 +00:00
vop3_vi.txt [AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when src2 == VCC. 2016-06-06 15:23:43 +00:00
vopc_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00