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AsmParser
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[AArch64][v8.5A] Add Memory Tagging instructions
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2018-10-02 10:04:39 +00:00 |
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Disassembler
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[AArch64][v8.5A] Add Memory Tagging instructions
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2018-10-02 10:04:39 +00:00 |
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InstPrinter
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[AArch64][v8.5A] Add Branch Target Identification instructions
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2018-09-27 14:54:33 +00:00 |
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MCTargetDesc
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[AARCH64][FIX] Emit data symbol for constant pool data
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2018-10-11 14:10:32 +00:00 |
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TargetInfo
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Utils
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[AArch64][v8.5A] Add Branch Target Identification instructions
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2018-09-27 14:54:33 +00:00 |
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AArch64.h
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[AArch64][v8.5A] Branch Target Identification code-generation pass
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2018-10-08 14:04:24 +00:00 |
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AArch64.td
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[AArch64][v8.5A] Add MTE as an optional AArch64 extension
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2018-10-02 09:36:28 +00:00 |
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AArch64A53Fix835769.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64A57FPLoadBalancing.cpp
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llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)
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2018-09-27 02:13:45 +00:00 |
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AArch64AdvSIMDScalarPass.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64AsmPrinter.cpp
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[AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI
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2018-10-08 14:09:15 +00:00 |
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AArch64BranchTargets.cpp
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[AArch64][v8.5A] Branch Target Identification code-generation pass
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2018-10-08 14:04:24 +00:00 |
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AArch64CallLowering.cpp
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[AArch64] Support adding X[8-15,18] registers as CSRs.
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2018-09-22 22:17:50 +00:00 |
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AArch64CallLowering.h
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[GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value
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2018-08-02 08:33:31 +00:00 |
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AArch64CallingConvention.h
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AArch64CallingConvention.td
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[AArch64] Implement aarch64_vector_pcs codegen support.
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2018-09-12 12:10:22 +00:00 |
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AArch64CleanupLocalDynamicTLSPass.cpp
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AArch64CollectLOH.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64CondBrTuning.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64ConditionOptimizer.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64ConditionalCompares.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64DeadRegisterDefinitionsPass.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64ExpandPseudoInsts.cpp
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[AArch64] Add Tiny Code Model for AArch64
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2018-08-22 11:31:39 +00:00 |
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AArch64FalkorHWPFFix.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64FastISel.cpp
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[AArch64] Support adding X[8-15,18] registers as CSRs.
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2018-09-22 22:17:50 +00:00 |
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AArch64FrameLowering.cpp
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[AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI
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2018-10-08 14:09:15 +00:00 |
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AArch64FrameLowering.h
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Remove \brief commands from doxygen comments.
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2018-05-01 15:54:18 +00:00 |
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AArch64GenRegisterBankInfo.def
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AArch64ISelDAGToDAG.cpp
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[AArch64][v8.5A] Add speculation restriction system registers
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2018-09-27 14:05:46 +00:00 |
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AArch64ISelLowering.cpp
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[AARCH64] Improve vector popcnt lowering with ADDLP
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2018-10-15 21:15:58 +00:00 |
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AArch64ISelLowering.h
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[AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IR
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2018-09-19 14:51:42 +00:00 |
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AArch64InstrAtomics.td
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[AArch64] Improve v8.1-A code-gen for atomic load-and
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2018-02-12 17:03:11 +00:00 |
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AArch64InstrFormats.td
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[AArch64][v8.5A] Add Memory Tagging instructions
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2018-10-02 10:04:39 +00:00 |
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AArch64InstrInfo.cpp
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Use llvm::{all,any,none}_of instead std::{all,any,none}_of. NFC
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2018-10-19 06:12:02 +00:00 |
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AArch64InstrInfo.h
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[MachineOutliner][AArch64] Add support for saving LR to a register
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2018-07-30 17:45:28 +00:00 |
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AArch64InstrInfo.td
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[AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI
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2018-10-08 14:09:15 +00:00 |
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AArch64InstructionSelector.cpp
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[AArch64] Add Tiny Code Model for AArch64
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2018-08-22 11:31:39 +00:00 |
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AArch64LegalizerInfo.cpp
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[AArch64][GlobalISel] Make G_BLOCK_ADDR legal.
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2018-07-31 00:08:56 +00:00 |
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AArch64LegalizerInfo.h
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AArch64LoadStoreOptimizer.cpp
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[MI] Change the array of `MachineMemOperand` pointers to be
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2018-08-16 21:30:05 +00:00 |
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AArch64MCInstLower.cpp
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[MinGW] [AArch64] Add stubs for potential automatic dllimported variables
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2018-09-04 20:56:21 +00:00 |
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AArch64MCInstLower.h
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AArch64MachineFunctionInfo.h
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Remove trailing space
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2018-07-30 19:41:25 +00:00 |
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AArch64MacroFusion.cpp
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[PATCH] [NFC][AArch64] Fix refactoring of macro fusion
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2018-10-16 17:41:45 +00:00 |
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AArch64MacroFusion.h
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AArch64PBQPRegAlloc.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h
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AArch64PreLegalizerCombiner.cpp
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Add the missing new files from r343654
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2018-10-03 02:21:30 +00:00 |
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AArch64PromoteConstant.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64RedundantCopyElimination.cpp
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[CodeGen][AArch64] Use RegUnits to track register aliases. (NFC)
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2018-05-23 17:49:38 +00:00 |
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AArch64RegisterBankInfo.cpp
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AArch64RegisterBankInfo.h
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AArch64RegisterBanks.td
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…
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AArch64RegisterInfo.cpp
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[Aarch64] Fix memcpy that was copying 4x too many bytes
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2018-09-23 18:43:28 +00:00 |
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AArch64RegisterInfo.h
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[TargetRegisterInfo] Remove temporary hook enableMultipleCopyHints()
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2018-10-05 14:23:11 +00:00 |
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AArch64RegisterInfo.td
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[AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI
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2018-10-08 14:09:15 +00:00 |
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AArch64SIMDInstrOpt.cpp
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[TargetSchedule] shrink interface for init(); NFCI
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2018-04-08 19:56:04 +00:00 |
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AArch64SVEInstrInfo.td
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[AArch64][SVE] Asm: Enable instructions to be prefixed.
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2018-07-30 16:05:45 +00:00 |
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AArch64SchedA53.td
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[AArch64] Clean-up a few over-eager regexps in models.
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2018-03-23 11:00:42 +00:00 |
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AArch64SchedA57.td
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AArch64SchedA57WriteRes.td
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…
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AArch64SchedCyclone.td
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AArch64SchedExynosM1.td
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[ExynosM1][Sched] Fix resource usage in scheduling model.
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2018-06-11 07:33:08 +00:00 |
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AArch64SchedExynosM3.td
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[ExynosM3] Fix scheduling info.
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2018-05-18 13:10:41 +00:00 |
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AArch64SchedFalkor.td
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[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
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2018-03-18 19:56:15 +00:00 |
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AArch64SchedFalkorDetails.td
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[AArch64][Falkor] Correct load/store increment scheduling details
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2018-03-20 13:46:35 +00:00 |
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AArch64SchedKryo.td
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[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
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2018-03-18 19:56:15 +00:00 |
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AArch64SchedKryoDetails.td
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AArch64SchedThunderX.td
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[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
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2018-03-18 19:56:15 +00:00 |
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AArch64SchedThunderX2T99.td
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[TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.
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2018-06-13 09:41:49 +00:00 |
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AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp
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AArch64SelectionDAGInfo.h
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AArch64StorePairSuppress.cpp
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Rename DEBUG macro to LLVM_DEBUG.
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2018-05-14 12:53:11 +00:00 |
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AArch64Subtarget.cpp
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[AArch64] Support adding X[8-15,18] registers as CSRs.
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2018-09-22 22:17:50 +00:00 |
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AArch64Subtarget.h
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[AArch64][v8.5A] Add Memory Tagging instructions
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2018-10-02 10:04:39 +00:00 |
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AArch64SystemOperands.td
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[AArch64][v8.5A] Add Memory Tagging system registers
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2018-10-02 09:54:35 +00:00 |
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AArch64TargetMachine.cpp
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[AArch64][v8.5A] Branch Target Identification code-generation pass
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2018-10-08 14:04:24 +00:00 |
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AArch64TargetMachine.h
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AArch64TargetObjectFile.cpp
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[AArch64] DWARF: do not generate AT_location for thread local
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2018-08-01 23:46:49 +00:00 |
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AArch64TargetObjectFile.h
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Move TargetLoweringObjectFile from CodeGen to Target to fix layering
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2018-03-23 23:58:19 +00:00 |
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AArch64TargetTransformInfo.cpp
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recommit 344472 after fixing build failure on ARM and PPC.
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2018-10-14 08:50:06 +00:00 |
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AArch64TargetTransformInfo.h
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recommit 344472 after fixing build failure on ARM and PPC.
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2018-10-14 08:50:06 +00:00 |
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CMakeLists.txt
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[AArch64][v8.5A] Branch Target Identification code-generation pass
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2018-10-08 14:04:24 +00:00 |
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LLVMBuild.txt
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SVEInstrFormats.td
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Remove extra whitespace. NFC. (test commit)
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2018-09-28 08:45:28 +00:00 |
