llvm-project/llvm/test/CodeGen
Sean Fertile d6c8736287 [PowerPC][AIX] Spill CSRs to the ABI specified stack offsets.
Extend the CSR save/restore insertion code to support both 32-bit and
64-bit AIX.

Differential Revision: https://reviews.llvm.org/D79252
2020-05-26 12:24:29 -04:00
..
AArch64 GlobalISel: Merge G_PTR_MASK with llvm.ptrmask intrinsic 2020-05-26 11:48:13 -04:00
AMDGPU AMDGPU/GlobalISel: Fix assert on 16-bit G_EXTRACT results 2020-05-26 12:14:08 -04:00
ARC
ARM [TargetPassConfig] Don't add alias analysis at optnone 2020-05-23 10:35:03 +02:00
AVR [AVR] Fix I/O instructions on XMEGA 2020-05-17 19:46:09 +12:00
BPF [BPF] Return fail if disassembled insn registers out of range 2020-05-18 18:53:23 -07:00
Generic [FPEnv] Intrinsic llvm.roundeven 2020-05-26 19:24:58 +07:00
Hexagon [ModuloSchedule] Fix epilogue peeling with illegal phi. 2020-05-07 10:04:05 -07:00
Inputs
Lanai
MIR [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
MSP430
Mips Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC" 2020-05-22 05:36:15 -06:00
NVPTX
PowerPC [PowerPC][AIX] Spill CSRs to the ABI specified stack offsets. 2020-05-26 12:24:29 -04:00
RISCV [RISCV] Support Constant Pools in Load/Store Peephole 2020-05-11 19:20:38 +01:00
SPARC
SystemZ [SystemZ] Eliminate the need to create a zero vector by reusing the VPERM mask. 2020-05-19 09:37:19 +02:00
Thumb [ARM] Don't shrink STM if it would cause an unknown base register store 2020-04-22 14:50:42 +01:00
Thumb2 [ARM] MVE VMINV/VMAXV test additions. NFC 2020-05-26 14:00:14 +01:00
VE [VE][NFC] Correct sjlj_expection test 2020-05-25 09:49:37 +02:00
WebAssembly [WebAssembly] Fix bug in custom shuffle combine 2020-05-19 12:54:15 -07:00
WinCFGuard
WinEH
X86 [DAGCombiner] try to move splat after binop with splat constant 2020-05-26 08:12:46 -04:00
XCore