forked from OSchip/llvm-project
266 lines
15 KiB
TableGen
266 lines
15 KiB
TableGen
//===-- PPCScheduleE500mc.td - e500mc Scheduling Defs ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the Freescale e500mc 32-bit
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// Power processor.
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//
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// All information is derived from the "e500mc Core Reference Manual",
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// Freescale Document Number E500MCRM, Rev. 1, 03/2012.
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//
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//===----------------------------------------------------------------------===//
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// Relevant functional units in the Freescale e500mc core:
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//
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// * Decode & Dispatch
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// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
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// queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
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def DIS0 : FuncUnit; // Dispatch stage - insn 1
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def DIS1 : FuncUnit; // Dispatch stage - insn 2
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// * Execute
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// 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
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// Some instructions can only execute in SFX0 but not SFX1.
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// The CFX has a bypass path, allowing non-divide instructions to execute
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// while a divide instruction is executed.
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def SFX0 : FuncUnit; // Simple unit 0
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def SFX1 : FuncUnit; // Simple unit 1
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def BU : FuncUnit; // Branch unit
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def CFX_DivBypass
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: FuncUnit; // CFX divide bypass path
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def CFX_0 : FuncUnit; // CFX pipeline
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def LSU_0 : FuncUnit; // LSU pipeline
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def FPU_0 : FuncUnit; // FPU pipeline
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def PPCE500mcItineraries : ProcessorItineraries<
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[DIS0, DIS1, SFX0, SFX1, BU, CFX_DivBypass, CFX_0, LSU_0, FPU_0],
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[CR_Bypass, GPR_Bypass, FPR_Bypass], [
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InstrItinData<IntSimple , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1]>],
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[4, 1, 1], // Latency = 1
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntGeneral , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1]>],
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[4, 1, 1], // Latency = 1
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntCompare , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1]>],
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[5, 1, 1], // Latency = 1 or 2
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[CR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntDivW , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [CFX_0], 0>,
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InstrStage<14, [CFX_DivBypass]>],
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[17, 1, 1], // Latency=4..35, Repeat= 4..35
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMFFS , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<8, [FPU_0]>],
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[11], // Latency = 8
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[FPR_Bypass]>,
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InstrItinData<IntMTFSB0 , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<8, [FPU_0]>],
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[11, 1, 1], // Latency = 8
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[NoBypass, NoBypass, NoBypass]>,
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InstrItinData<IntMulHW , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [CFX_0]>],
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[7, 1, 1], // Latency = 4, Repeat rate = 1
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMulHWU , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [CFX_0]>],
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[7, 1, 1], // Latency = 4, Repeat rate = 1
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMulLI , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [CFX_0]>],
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[7, 1, 1], // Latency = 4, Repeat rate = 1
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntRotate , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1]>],
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[4, 1, 1], // Latency = 1
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntShift , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1]>],
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[4, 1, 1], // Latency = 1
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntTrapW , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<2, [SFX0]>],
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[5, 1], // Latency = 2, Repeat rate = 2
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<BrB , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [BU]>],
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[4, 1], // Latency = 1
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[NoBypass, GPR_Bypass]>,
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InstrItinData<BrCR , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [BU]>],
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[4, 1, 1], // Latency = 1
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[CR_Bypass, CR_Bypass, CR_Bypass]>,
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InstrItinData<BrMCR , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [BU]>],
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[4, 1], // Latency = 1
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[CR_Bypass, CR_Bypass]>,
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InstrItinData<BrMCRX , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1]>],
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[4, 1, 1], // Latency = 1
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[CR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStDCBA , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[6, 1], // Latency = 3, Repeat rate = 1
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStDCBF , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[6, 1], // Latency = 3
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStDCBI , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[6, 1], // Latency = 3
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStLoad , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[6, 1], // Latency = 3
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStLoadUpd , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1], 0>,
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InstrStage<1, [LSU_0]>],
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[6, 1], // Latency = 3
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[GPR_Bypass, GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<LdStStore , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStStoreUpd, [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1], 0>,
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InstrStage<1, [LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<LdStICBI , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStSTFD , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[6, 1, 1], // Latency = 3
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStSTFDU , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1], 0>,
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InstrStage<1, [LSU_0]>],
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[6, 1, 1], // Latency = 3
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[GPR_Bypass, GPR_Bypass, GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<LdStLFD , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 1, 1], // Latency = 4
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[FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStLFDU , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 1, 1], // Latency = 4
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[FPR_Bypass, GPR_Bypass, GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<LdStLHA , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[6, 1], // Latency = 3
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStLHAU , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1], 0>,
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InstrStage<1, [LSU_0]>],
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[6, 1], // Latency = 3
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStLMW , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[7, 1], // Latency = r+3
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStLWARX , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<3, [LSU_0]>],
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[6, 1, 1], // Latency = 3, Repeat rate = 3
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStSTWCX , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStSync , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0]>]>,
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InstrItinData<SprMFSR , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<4, [SFX0]>],
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[7, 1],
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<SprMTMSR , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<2, [SFX0, SFX1]>],
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[5, 1], // Latency = 2, Repeat rate = 4
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<SprMTSR , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0]>],
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[5, 1],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<SprTLBSYNC , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [LSU_0], 0>]>,
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InstrItinData<SprMFCR , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<5, [SFX0]>],
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[8, 1],
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[GPR_Bypass, CR_Bypass]>,
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InstrItinData<SprMFMSR , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<4, [SFX0]>],
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[7, 1], // Latency = 4, Repeat rate = 4
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<SprMFSPR , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1]>],
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[4, 1], // Latency = 1, Repeat rate = 1
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[GPR_Bypass, CR_Bypass]>,
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InstrItinData<SprMFTB , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<4, [SFX0]>],
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[7, 1], // Latency = 4, Repeat rate = 4
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[NoBypass, GPR_Bypass]>,
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InstrItinData<SprMTSPR , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0, SFX1]>],
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[4, 1], // Latency = 1, Repeat rate = 1
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[CR_Bypass, GPR_Bypass]>,
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InstrItinData<SprMTSRIN , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<1, [SFX0]>],
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[4, 1],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<FPGeneral , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<2, [FPU_0]>],
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[11, 1, 1], // Latency = 8, Repeat rate = 2
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[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
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InstrItinData<FPAddSub , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<4, [FPU_0]>],
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[13, 1, 1], // Latency = 10, Repeat rate = 4
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[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
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InstrItinData<FPCompare , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<2, [FPU_0]>],
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[11, 1, 1], // Latency = 8, Repeat rate = 2
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[CR_Bypass, FPR_Bypass, FPR_Bypass]>,
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InstrItinData<FPDivD , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<68, [FPU_0]>],
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[71, 1, 1], // Latency = 68, Repeat rate = 68
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[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
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InstrItinData<FPDivS , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<38, [FPU_0]>],
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[41, 1, 1], // Latency = 38, Repeat rate = 38
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[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
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InstrItinData<FPFused , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<4, [FPU_0]>],
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[13, 1, 1, 1], // Latency = 10, Repeat rate = 4
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[FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
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InstrItinData<FPRes , [InstrStage<1, [DIS0, DIS1], 0>,
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InstrStage<38, [FPU_0]>],
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[41, 1], // Latency = 38, Repeat rate = 38
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[FPR_Bypass, FPR_Bypass]>
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]>;
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// ===---------------------------------------------------------------------===//
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// e500mc machine model for scheduling and other instruction cost heuristics.
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def PPCE500mcModel : SchedMachineModel {
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let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
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let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
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let LoadLatency = 5; // Optimistic load latency assuming bypass.
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// This is overriden by OperandCycles if the
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// Itineraries are queried instead.
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let Itineraries = PPCE500mcItineraries;
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}
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