forked from OSchip/llvm-project
344 lines
10 KiB
LLVM
344 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -div-rem-pairs -S -mtriple=x86_64-unknown-unknown | FileCheck %s
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declare void @foo(i32, i32)
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define void @decompose_illegal_srem_same_block(i32 %a, i32 %b) {
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; CHECK-LABEL: @decompose_illegal_srem_same_block(
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; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[A]], [[B]]
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; CHECK-NEXT: call void @foo(i32 [[REM]], i32 [[DIV]])
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; CHECK-NEXT: ret void
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;
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%rem = srem i32 %a, %b
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%div = sdiv i32 %a, %b
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call void @foo(i32 %rem, i32 %div)
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ret void
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}
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define void @decompose_illegal_urem_same_block(i32 %a, i32 %b) {
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; CHECK-LABEL: @decompose_illegal_urem_same_block(
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; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[REM:%.*]] = urem i32 [[A]], [[B]]
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; CHECK-NEXT: call void @foo(i32 [[REM]], i32 [[DIV]])
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; CHECK-NEXT: ret void
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;
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%div = udiv i32 %a, %b
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%rem = urem i32 %a, %b
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call void @foo(i32 %rem, i32 %div)
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ret void
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}
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; Hoist and optionally decompose the sdiv because it's safe and free.
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; PR31028 - https://bugs.llvm.org/show_bug.cgi?id=31028
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define i32 @hoist_sdiv(i32 %a, i32 %b) {
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; CHECK-LABEL: @hoist_sdiv(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[A]], [[B]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
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; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
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; CHECK: if:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[RET:%.*]] = phi i32 [ [[DIV]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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entry:
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%rem = srem i32 %a, %b
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%cmp = icmp eq i32 %rem, 42
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br i1 %cmp, label %if, label %end
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if:
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%div = sdiv i32 %a, %b
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br label %end
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end:
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%ret = phi i32 [ %div, %if ], [ 3, %entry ]
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ret i32 %ret
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}
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; Hoist and optionally decompose the udiv because it's safe and free.
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define i64 @hoist_udiv(i64 %a, i64 %b) {
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; CHECK-LABEL: @hoist_udiv(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[REM:%.*]] = urem i64 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[A]], [[B]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[REM]], 42
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; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
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; CHECK: if:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[RET:%.*]] = phi i64 [ [[DIV]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i64 [[RET]]
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;
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entry:
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%rem = urem i64 %a, %b
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%cmp = icmp eq i64 %rem, 42
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br i1 %cmp, label %if, label %end
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if:
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%div = udiv i64 %a, %b
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br label %end
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end:
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%ret = phi i64 [ %div, %if ], [ 3, %entry ]
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ret i64 %ret
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}
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; Hoist the srem if it's safe and free, otherwise decompose it.
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define i16 @hoist_srem(i16 %a, i16 %b) {
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; CHECK-LABEL: @hoist_srem(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i16 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[REM:%.*]] = srem i16 [[A]], [[B]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[DIV]], 42
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; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
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; CHECK: if:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[RET:%.*]] = phi i16 [ [[REM]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i16 [[RET]]
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;
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entry:
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%div = sdiv i16 %a, %b
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%cmp = icmp eq i16 %div, 42
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br i1 %cmp, label %if, label %end
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if:
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%rem = srem i16 %a, %b
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br label %end
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end:
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%ret = phi i16 [ %rem, %if ], [ 3, %entry ]
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ret i16 %ret
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}
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; Hoist the urem if it's safe and free, otherwise decompose it.
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define i8 @hoist_urem(i8 %a, i8 %b) {
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; CHECK-LABEL: @hoist_urem(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[DIV:%.*]] = udiv i8 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[REM:%.*]] = urem i8 [[A]], [[B]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[DIV]], 42
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; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
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; CHECK: if:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[RET:%.*]] = phi i8 [ [[REM]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i8 [[RET]]
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;
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entry:
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%div = udiv i8 %a, %b
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%cmp = icmp eq i8 %div, 42
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br i1 %cmp, label %if, label %end
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if:
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%rem = urem i8 %a, %b
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br label %end
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end:
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%ret = phi i8 [ %rem, %if ], [ 3, %entry ]
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ret i8 %ret
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}
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; Be careful with RAUW/invalidation if this is a srem-of-srem.
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define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-LABEL: @srem_of_srem_unexpanded(
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = srem i32 [[X]], [[T0]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[T6:%.*]] = srem i32 [[T3]], [[Y]]
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; CHECK-NEXT: ret i32 [[T6]]
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;
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%t0 = mul nsw i32 %Z, %Y
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%t1 = sdiv i32 %X, %t0
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%t2 = mul nsw i32 %t0, %t1
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%t3 = srem i32 %X, %t0
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%t4 = sdiv i32 %t3, %Y
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%t5 = mul nsw i32 %t4, %Y
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%t6 = srem i32 %t3, %Y
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ret i32 %t6
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}
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define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-LABEL: @srem_of_srem_expanded(
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[T3_RECOMPOSED:%.*]] = srem i32 [[X]], [[T0]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3_RECOMPOSED]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[T6_RECOMPOSED:%.*]] = srem i32 [[T3_RECOMPOSED]], [[Y]]
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; CHECK-NEXT: ret i32 [[T6_RECOMPOSED]]
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;
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%t0 = mul nsw i32 %Z, %Y
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%t1 = sdiv i32 %X, %t0
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%t2 = mul nsw i32 %t0, %t1
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%t3 = sub nsw i32 %X, %t2
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%t4 = sdiv i32 %t3, %Y
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%t5 = mul nsw i32 %t4, %Y
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%t6 = sub nsw i32 %t3, %t5
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ret i32 %t6
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}
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; If the ops don't match, don't do anything: signedness.
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define i32 @dont_hoist_udiv(i32 %a, i32 %b) {
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; CHECK-LABEL: @dont_hoist_udiv(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
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; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
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; CHECK: if:
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; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[A]], [[B]]
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[RET:%.*]] = phi i32 [ [[DIV]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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entry:
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%rem = srem i32 %a, %b
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%cmp = icmp eq i32 %rem, 42
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br i1 %cmp, label %if, label %end
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if:
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%div = udiv i32 %a, %b
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br label %end
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end:
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%ret = phi i32 [ %div, %if ], [ 3, %entry ]
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ret i32 %ret
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}
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; If the ops don't match, don't do anything: operation.
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define i32 @dont_hoist_srem(i32 %a, i32 %b) {
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; CHECK-LABEL: @dont_hoist_srem(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[REM:%.*]] = urem i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
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; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
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; CHECK: if:
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; CHECK-NEXT: [[REM2:%.*]] = srem i32 [[A]], [[B]]
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[RET:%.*]] = phi i32 [ [[REM2]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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entry:
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%rem = urem i32 %a, %b
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%cmp = icmp eq i32 %rem, 42
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br i1 %cmp, label %if, label %end
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if:
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%rem2 = srem i32 %a, %b
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br label %end
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end:
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%ret = phi i32 [ %rem2, %if ], [ 3, %entry ]
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ret i32 %ret
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}
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; If the ops don't match, don't do anything: operands.
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define i32 @dont_hoist_sdiv(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: @dont_hoist_sdiv(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
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; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
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; CHECK: if:
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[A]], [[C:%.*]]
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[RET:%.*]] = phi i32 [ [[DIV]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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entry:
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%rem = srem i32 %a, %b
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%cmp = icmp eq i32 %rem, 42
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br i1 %cmp, label %if, label %end
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if:
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%div = sdiv i32 %a, %c
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br label %end
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end:
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%ret = phi i32 [ %div, %if ], [ 3, %entry ]
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ret i32 %ret
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}
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; If the target doesn't have a unified div/rem op for the type, decompose rem in-place to mul+sub.
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define i128 @dont_hoist_urem(i128 %a, i128 %b) {
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; CHECK-LABEL: @dont_hoist_urem(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[A_FROZEN:%.*]] = freeze i128 [[A:%.*]]
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; CHECK-NEXT: [[B_FROZEN:%.*]] = freeze i128 [[B:%.*]]
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; CHECK-NEXT: [[DIV:%.*]] = udiv i128 [[A_FROZEN]], [[B_FROZEN]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i128 [[DIV]], 42
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; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
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; CHECK: if:
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; CHECK-NEXT: [[TMP0:%.*]] = mul i128 [[DIV]], [[B_FROZEN]]
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; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i128 [[A_FROZEN]], [[TMP0]]
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[RET:%.*]] = phi i128 [ [[REM_DECOMPOSED]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i128 [[RET]]
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;
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entry:
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%div = udiv i128 %a, %b
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%cmp = icmp eq i128 %div, 42
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br i1 %cmp, label %if, label %end
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if:
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%rem = urem i128 %a, %b
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br label %end
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end:
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%ret = phi i128 [ %rem, %if ], [ 3, %entry ]
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ret i128 %ret
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}
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; We don't hoist if one op does not dominate the other,
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; but we could hoist both ops to the common predecessor block?
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define i32 @no_domination(i1 %cmp, i32 %a, i32 %b) {
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; CHECK-LABEL: @no_domination(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[CMP:%.*]], label [[IF:%.*]], label [[ELSE:%.*]]
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; CHECK: if:
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: br label [[END:%.*]]
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; CHECK: else:
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; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A]], [[B]]
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[RET:%.*]] = phi i32 [ [[DIV]], [[IF]] ], [ [[REM]], [[ELSE]] ]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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entry:
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br i1 %cmp, label %if, label %else
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if:
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%div = sdiv i32 %a, %b
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br label %end
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else:
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%rem = srem i32 %a, %b
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br label %end
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end:
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%ret = phi i32 [ %div, %if ], [ %rem, %else ]
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ret i32 %ret
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}
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