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AArch64
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[AArch64][AsmParser] Add rcpc support in .arch_extension
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2020-07-14 10:57:11 +01:00 |
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AMDGPU
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[AMDGPU] Removed s_mov_regrd and mov_fed opcodes
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2020-07-17 19:52:54 +03:00 |
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ARM
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[ARM] VBIT/VBIF support added.
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2020-07-16 11:25:53 +01:00 |
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AVR
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[AVRInstPrinter] printOperand: support llvm-objdump --print-imm-hex
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2020-07-12 08:14:52 -07:00 |
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AsmParser
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[MC/AsmParser] layout-interdependency.s depends on having a proper triple
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2020-07-13 14:38:47 -07:00 |
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BPF
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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COFF
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[COFF] Add cg_profile directive and .llvm.call-graph-profile section
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2020-07-10 17:07:30 -07:00 |
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Disassembler
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[AMDGPU] Removed s_mov_regrd and mov_fed opcodes
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2020-07-17 19:52:54 +03:00 |
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ELF
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[MC] Support .reloc sym+constant, *, *
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2020-07-14 13:44:00 -07:00 |
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Hexagon
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[Hexagon] pX.new cannot be used with p3:0 as producer
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2020-05-19 17:06:34 -05:00 |
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Lanai
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[lit] Delete empty lines at the end of lit.local.cfg NFC
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2019-06-17 09:51:07 +00:00 |
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MSP430
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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MachO
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split darwin-version-min-load-command.s into Arm64 subtest to avoid failures
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2020-06-30 14:49:04 -07:00 |
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Mips
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[DebugInfo] Respect relocations when decoding DW_EH_PE_sdata4 & DW_EH_PE_sdata8 and support R_ARM_REL32
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2020-07-18 09:00:50 -07:00 |
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PowerPC
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[PowerPC][Power10] Add 128-bit Binary Integer Operation instruction definitions and MC Tests
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2020-07-16 17:16:43 -05:00 |
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RISCV
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[RISCV] Refactor FeatureRVCHints to make ProcessorModel more intuitive
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2020-07-09 23:07:39 -07:00 |
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Sparc
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[Object] Change ELFObjectFile<ELFT>::getFileFormatName() to use BFD names
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2020-03-16 07:42:04 -07:00 |
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SystemZ
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[SystemZ] Allow specifying integer registers as part of the address calculation
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2020-07-08 18:20:24 +02:00 |
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VE
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[VE] Support symbol with offset in assembly
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2020-07-07 04:16:51 +09:00 |
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WebAssembly
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[WebAssembly] Added 64-bit memory.grow/size/copy/fill
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2020-07-06 12:49:50 -07:00 |
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X86
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[X86] Allow lsl/lar to be parsed with a GR16, GR32, or GR64 as source register.
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2020-07-15 23:51:37 -07:00 |
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