forked from OSchip/llvm-project
601 lines
19 KiB
LLVM
601 lines
19 KiB
LLVM
; RUN: llc %s -o - -enable-shrink-wrap=true | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
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; RUN: llc %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
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;
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; Note: Lots of tests use inline asm instead of regular calls.
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; This allows to have a better control on what the allocation will do.
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; Otherwise, we may have spill right in the entry block, defeating
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; shrink-wrapping. Moreover, some of the inline asm statement (nop)
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; are here to ensure that the related paths do not end up as critical
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; edges.
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "x86_64-apple-macosx"
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; Initial motivating example: Simple diamond with a call just on one side.
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; CHECK-LABEL: foo:
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;
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; Compare the arguments and jump to exit.
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; No prologue needed.
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; ENABLE: movl %edi, [[ARG0CPY:%e[a-z]+]]
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; ENABLE-NEXT: cmpl %esi, [[ARG0CPY]]
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; ENABLE-NEXT: jge [[EXIT_LABEL:LBB[0-9_]+]]
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;
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; Prologue code.
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; (What we push does not matter. It should be some random sratch register.)
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; CHECK: pushq
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;
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; Compare the arguments and jump to exit.
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; After the prologue is set.
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; DISABLE: movl %edi, [[ARG0CPY:%e[a-z]+]]
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; DISABLE-NEXT: cmpl %esi, [[ARG0CPY]]
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; DISABLE-NEXT: jge [[EXIT_LABEL:LBB[0-9_]+]]
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;
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; Store %a in the alloca.
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; CHECK: movl [[ARG0CPY]], 4(%rsp)
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; Set the alloca address in the second argument.
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; CHECK-NEXT: leaq 4(%rsp), %rsi
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; Set the first argument to zero.
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; CHECK-NEXT: xorl %edi, %edi
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; CHECK-NEXT: callq _doSomething
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;
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; With shrink-wrapping, epilogue is just after the call.
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; ENABLE-NEXT: addq $8, %rsp
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;
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; CHECK: [[EXIT_LABEL]]:
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;
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; Without shrink-wrapping, epilogue is in the exit block.
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; Epilogue code. (What we pop does not matter.)
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; DISABLE-NEXT: popq
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;
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; CHECK-NEXT: retq
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define i32 @foo(i32 %a, i32 %b) {
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%tmp = alloca i32, align 4
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%tmp2 = icmp slt i32 %a, %b
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br i1 %tmp2, label %true, label %false
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true:
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store i32 %a, i32* %tmp, align 4
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%tmp4 = call i32 @doSomething(i32 0, i32* %tmp)
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br label %false
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false:
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%tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
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ret i32 %tmp.0
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}
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; Function Attrs: optsize
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declare i32 @doSomething(i32, i32*)
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; Check that we do not perform the restore inside the loop whereas the save
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; is outside.
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; CHECK-LABEL: freqSaveAndRestoreOutsideLoop:
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;
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; Shrink-wrapping allows to skip the prologue in the else case.
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; ENABLE: testl %edi, %edi
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; ENABLE: je [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; Prologue code.
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; Make sure we save the CSR used in the inline asm: rbx.
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; CHECK: pushq %rbx
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;
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; DISABLE: testl %edi, %edi
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; DISABLE: je [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; SUM is in %esi because it is coalesced with the second
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; argument on the else path.
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; CHECK: xorl [[SUM:%esi]], [[SUM]]
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; CHECK-NEXT: movl $10, [[IV:%e[a-z]+]]
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;
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; Next BB.
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; CHECK: [[LOOP:LBB[0-9_]+]]: ## %for.body
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; CHECK: movl $1, [[TMP:%e[a-z]+]]
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; CHECK: addl [[TMP]], [[SUM]]
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; CHECK-NEXT: decl [[IV]]
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; CHECK-NEXT: jne [[LOOP]]
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;
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; Next BB.
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; SUM << 3.
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; CHECK: shll $3, [[SUM]]
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;
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; Jump to epilogue.
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; DISABLE: jmp [[EPILOG_BB:LBB[0-9_]+]]
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;
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; DISABLE: [[ELSE_LABEL]]: ## %if.else
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; Shift second argument by one and store into returned register.
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; DISABLE: addl %esi, %esi
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; DISABLE: [[EPILOG_BB]]: ## %if.end
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;
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; Epilogue code.
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; CHECK-DAG: popq %rbx
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; CHECK-DAG: movl %esi, %eax
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; CHECK: retq
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;
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; ENABLE: [[ELSE_LABEL]]: ## %if.else
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; Shift second argument by one and store into returned register.
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; ENABLE: addl %esi, %esi
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; ENABLE-NEXT: movl %esi, %eax
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; ENABLE-NEXT: retq
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define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) {
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entry:
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%tobool = icmp eq i32 %cond, 0
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br i1 %tobool, label %if.else, label %for.preheader
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for.preheader:
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tail call void asm "nop", ""()
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
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%sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ]
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%call = tail call i32 asm "movl $$1, $0", "=r,~{ebx}"()
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%add = add nsw i32 %call, %sum.04
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%inc = add nuw nsw i32 %i.05, 1
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%exitcond = icmp eq i32 %inc, 10
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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%shl = shl i32 %add, 3
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br label %if.end
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if.else: ; preds = %entry
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%mul = shl nsw i32 %N, 1
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br label %if.end
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if.end: ; preds = %if.else, %for.end
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%sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
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ret i32 %sum.1
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}
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declare i32 @something(...)
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; Check that we do not perform the shrink-wrapping inside the loop even
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; though that would be legal. The cost model must prevent that.
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; CHECK-LABEL: freqSaveAndRestoreOutsideLoop2:
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; Prologue code.
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; Make sure we save the CSR used in the inline asm: rbx.
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; CHECK: pushq %rbx
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; CHECK: nop
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; CHECK: xorl [[SUM:%e[a-z]+]], [[SUM]]
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; CHECK-NEXT: movl $10, [[IV:%e[a-z]+]]
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; Next BB.
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; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ## %for.body
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; CHECK: movl $1, [[TMP:%e[a-z]+]]
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; CHECK: addl [[TMP]], [[SUM]]
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; CHECK-NEXT: decl [[IV]]
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; CHECK-NEXT: jne [[LOOP_LABEL]]
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; Next BB.
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; CHECK: ## %for.exit
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; CHECK: nop
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; CHECK: popq %rbx
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; CHECK-NEXT: retq
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define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {
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entry:
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br label %for.preheader
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for.preheader:
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tail call void asm "nop", ""()
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%i.04 = phi i32 [ 0, %for.preheader ], [ %inc, %for.body ]
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%sum.03 = phi i32 [ 0, %for.preheader ], [ %add, %for.body ]
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%call = tail call i32 asm "movl $$1, $0", "=r,~{ebx}"()
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%add = add nsw i32 %call, %sum.03
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%inc = add nuw nsw i32 %i.04, 1
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%exitcond = icmp eq i32 %inc, 10
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br i1 %exitcond, label %for.exit, label %for.body
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for.exit:
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tail call void asm "nop", ""()
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br label %for.end
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for.end: ; preds = %for.body
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ret i32 %add
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}
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; Check with a more complex case that we do not have save within the loop and
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; restore outside.
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; CHECK-LABEL: loopInfoSaveOutsideLoop:
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;
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; ENABLE: testl %edi, %edi
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; ENABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; Prologue code.
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; Make sure we save the CSR used in the inline asm: rbx.
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; CHECK: pushq %rbx
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;
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; DISABLE: testl %edi, %edi
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; DISABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; CHECK: nop
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; CHECK: xorl [[SUM:%esi]], [[SUM]]
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; CHECK-NEXT: movl $10, [[IV:%e[a-z]+]]
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;
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; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ## %for.body
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; CHECK: movl $1, [[TMP:%e[a-z]+]]
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; CHECK: addl [[TMP]], [[SUM]]
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; CHECK-NEXT: decl [[IV]]
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; CHECK-NEXT: jne [[LOOP_LABEL]]
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; Next BB.
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; CHECK: nop
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; CHECK: shll $3, [[SUM]]
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;
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; DISABLE: jmp [[EPILOG_BB:LBB[0-9_]+]]
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;
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; DISABLE: [[ELSE_LABEL]]: ## %if.else
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; Shift second argument by one and store into returned register.
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; DISABLE: addl %esi, %esi
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; DISABLE: [[EPILOG_BB]]: ## %if.end
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;
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; Epilogue code.
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; CHECK-DAG: popq %rbx
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; CHECK-DAG: movl %esi, %eax
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; CHECK: retq
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;
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; ENABLE: [[ELSE_LABEL]]: ## %if.else
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; Shift second argument by one and store into returned register.
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; ENABLE: addl %esi, %esi
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; ENABLE-NEXT: movl %esi, %eax
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; ENABLE-NEXT: retq
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define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) {
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entry:
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%tobool = icmp eq i32 %cond, 0
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br i1 %tobool, label %if.else, label %for.preheader
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for.preheader:
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tail call void asm "nop", ""()
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
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%sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ]
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%call = tail call i32 asm "movl $$1, $0", "=r,~{ebx}"()
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%add = add nsw i32 %call, %sum.04
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%inc = add nuw nsw i32 %i.05, 1
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%exitcond = icmp eq i32 %inc, 10
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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tail call void asm "nop", "~{ebx}"()
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%shl = shl i32 %add, 3
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br label %if.end
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if.else: ; preds = %entry
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%mul = shl nsw i32 %N, 1
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br label %if.end
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if.end: ; preds = %if.else, %for.end
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%sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
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ret i32 %sum.1
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}
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declare void @somethingElse(...)
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; Check with a more complex case that we do not have restore within the loop and
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; save outside.
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; CHECK-LABEL: loopInfoRestoreOutsideLoop:
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;
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; ENABLE: testl %edi, %edi
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; ENABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; Prologue code.
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; Make sure we save the CSR used in the inline asm: rbx.
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; CHECK: pushq %rbx
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;
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; DISABLE: testl %edi, %edi
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; DISABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; CHECK: nop
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; CHECK: xorl [[SUM:%esi]], [[SUM]]
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; CHECK-NEXT: movl $10, [[IV:%e[a-z]+]]
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;
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; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ## %for.body
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; CHECK: movl $1, [[TMP:%e[a-z]+]]
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; CHECK: addl [[TMP]], [[SUM]]
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; CHECK-NEXT: decl [[IV]]
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; CHECK-NEXT: jne [[LOOP_LABEL]]
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; Next BB.
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; CHECK: shll $3, [[SUM]]
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;
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; DISABLE: jmp [[EPILOG_BB:LBB[0-9_]+]]
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;
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; DISABLE: [[ELSE_LABEL]]: ## %if.else
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; Shift second argument by one and store into returned register.
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; DISABLE: addl %esi, %esi
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; DISABLE: [[EPILOG_BB]]: ## %if.end
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;
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; Epilogue code.
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; CHECK-DAG: popq %rbx
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; CHECK-DAG: movl %esi, %eax
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; CHECK: retq
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;
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; ENABLE: [[ELSE_LABEL]]: ## %if.else
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; Shift second argument by one and store into returned register.
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; ENABLE: addl %esi, %esi
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; ENABLE-NEXT: movl %esi, %eax
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; ENABLE-NEXT: retq
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define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) #0 {
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entry:
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%tobool = icmp eq i32 %cond, 0
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br i1 %tobool, label %if.else, label %if.then
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if.then: ; preds = %entry
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tail call void asm "nop", "~{ebx}"()
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br label %for.body
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for.body: ; preds = %for.body, %if.then
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%i.05 = phi i32 [ 0, %if.then ], [ %inc, %for.body ]
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%sum.04 = phi i32 [ 0, %if.then ], [ %add, %for.body ]
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%call = tail call i32 asm "movl $$1, $0", "=r,~{ebx}"()
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%add = add nsw i32 %call, %sum.04
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%inc = add nuw nsw i32 %i.05, 1
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%exitcond = icmp eq i32 %inc, 10
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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%shl = shl i32 %add, 3
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br label %if.end
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if.else: ; preds = %entry
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%mul = shl nsw i32 %N, 1
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br label %if.end
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if.end: ; preds = %if.else, %for.end
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%sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
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ret i32 %sum.1
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}
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; Check that we handle function with no frame information correctly.
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; CHECK-LABEL: emptyFrame:
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; CHECK: ## %entry
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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define i32 @emptyFrame() {
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entry:
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ret i32 0
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}
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; Check that we handle inline asm correctly.
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; CHECK-LABEL: inlineAsm:
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;
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; ENABLE: testl %edi, %edi
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; ENABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; Prologue code.
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; Make sure we save the CSR used in the inline asm: rbx.
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; CHECK: pushq %rbx
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;
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; DISABLE: testl %edi, %edi
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; DISABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; CHECK: nop
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; CHECK: movl $10, [[IV:%e[a-z]+]]
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;
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; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ## %for.body
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; Inline asm statement.
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; CHECK: addl $1, %ebx
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; CHECK: decl [[IV]]
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; CHECK-NEXT: jne [[LOOP_LABEL]]
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; Next BB.
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; CHECK: nop
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; CHECK: xorl %esi, %esi
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;
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; DISABLE: jmp [[EPILOG_BB:LBB[0-9_]+]]
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;
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; DISABLE: [[ELSE_LABEL]]: ## %if.else
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; Shift second argument by one and store into returned register.
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; DISABLE: addl %esi, %esi
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; DISABLE: [[EPILOG_BB]]: ## %if.end
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;
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; Epilogue code.
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; CHECK-DAG: popq %rbx
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; CHECK-DAG: movl %esi, %eax
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; CHECK: retq
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;
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; ENABLE: [[ELSE_LABEL]]: ## %if.else
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; Shift second argument by one and store into returned register.
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; ENABLE: addl %esi, %esi
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; ENABLE-NEXT: movl %esi, %eax
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; ENABLE-NEXT: retq
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define i32 @inlineAsm(i32 %cond, i32 %N) {
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entry:
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%tobool = icmp eq i32 %cond, 0
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br i1 %tobool, label %if.else, label %for.preheader
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for.preheader:
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tail call void asm "nop", ""()
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.03 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
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tail call void asm "addl $$1, %ebx", "~{ebx}"()
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%inc = add nuw nsw i32 %i.03, 1
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%exitcond = icmp eq i32 %inc, 10
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br i1 %exitcond, label %for.exit, label %for.body
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for.exit:
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tail call void asm "nop", ""()
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br label %if.end
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if.else: ; preds = %entry
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%mul = shl nsw i32 %N, 1
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br label %if.end
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if.end: ; preds = %for.body, %if.else
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%sum.0 = phi i32 [ %mul, %if.else ], [ 0, %for.exit ]
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ret i32 %sum.0
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}
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; Check that we handle calls to variadic functions correctly.
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; CHECK-LABEL: callVariadicFunc:
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;
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; ENABLE: testl %edi, %edi
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; ENABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; Prologue code.
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; CHECK: pushq
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;
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; DISABLE: testl %edi, %edi
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; DISABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; Setup of the varags.
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; CHECK: movl %esi, (%rsp)
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: %esi, %edi
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; CHECK-NEXT: %esi, %edx
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|
; CHECK-NEXT: %esi, %r8d
|
|
; CHECK-NEXT: %esi, %r9d
|
|
; CHECK-NEXT: %esi, %ecx
|
|
; CHECK-NEXT: callq _someVariadicFunc
|
|
; CHECK-NEXT: movl %eax, %esi
|
|
; CHECK-NEXT: shll $3, %esi
|
|
;
|
|
; ENABLE-NEXT: addq $8, %rsp
|
|
; ENABLE-NEXT: movl %esi, %eax
|
|
; ENABLE-NEXT: retq
|
|
;
|
|
; DISABLE: jmp [[IFEND_LABEL:LBB[0-9_]+]]
|
|
;
|
|
; CHECK: [[ELSE_LABEL]]: ## %if.else
|
|
; Shift second argument by one and store into returned register.
|
|
; CHECK: addl %esi, %esi
|
|
;
|
|
; DISABLE: [[IFEND_LABEL]]: ## %if.end
|
|
;
|
|
; Epilogue code.
|
|
; CHECK-NEXT: movl %esi, %eax
|
|
; DISABLE-NEXT: popq
|
|
; CHECK-NEXT: retq
|
|
define i32 @callVariadicFunc(i32 %cond, i32 %N) {
|
|
entry:
|
|
%tobool = icmp eq i32 %cond, 0
|
|
br i1 %tobool, label %if.else, label %if.then
|
|
|
|
if.then: ; preds = %entry
|
|
%call = tail call i32 (i32, ...) @someVariadicFunc(i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N)
|
|
%shl = shl i32 %call, 3
|
|
br label %if.end
|
|
|
|
if.else: ; preds = %entry
|
|
%mul = shl nsw i32 %N, 1
|
|
br label %if.end
|
|
|
|
if.end: ; preds = %if.else, %if.then
|
|
%sum.0 = phi i32 [ %shl, %if.then ], [ %mul, %if.else ]
|
|
ret i32 %sum.0
|
|
}
|
|
|
|
declare i32 @someVariadicFunc(i32, ...)
|
|
|
|
; Check that we use LEA not to clobber EFLAGS.
|
|
%struct.temp_slot = type { %struct.temp_slot*, %struct.rtx_def*, %struct.rtx_def*, i32, i64, %union.tree_node*, %union.tree_node*, i8, i8, i32, i32, i64, i64 }
|
|
%union.tree_node = type { %struct.tree_decl }
|
|
%struct.tree_decl = type { %struct.tree_common, i8*, i32, i32, %union.tree_node*, i48, %union.anon, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %struct.rtx_def*, %struct.rtx_def*, %union.anon.1, %union.tree_node*, %union.tree_node*, %union.tree_node*, i64, %struct.lang_decl* }
|
|
%struct.tree_common = type { %union.tree_node*, %union.tree_node*, i32 }
|
|
%union.anon = type { i64 }
|
|
%union.anon.1 = type { %struct.function* }
|
|
%struct.function = type { %struct.eh_status*, %struct.stmt_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, i8*, %union.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.ix86_args, %struct.rtx_def*, %struct.rtx_def*, i8*, %struct.initial_value_struct*, i32, %union.tree_node*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %union.tree_node*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i64, %union.tree_node*, %union.tree_node*, %struct.rtx_def*, %struct.rtx_def*, i32, %struct.rtx_def**, %struct.temp_slot*, i32, i32, i32, %struct.var_refs_queue*, i32, i32, i8*, %union.tree_node*, %struct.rtx_def*, i32, i32, %struct.machine_function*, i32, i32, %struct.language_function*, %struct.rtx_def*, i24 }
|
|
%struct.eh_status = type opaque
|
|
%struct.stmt_status = type opaque
|
|
%struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
|
|
%struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %union.tree_node*, %struct.sequence_stack*, i32, i32, i8*, i32, i8*, %union.tree_node**, %struct.rtx_def** }
|
|
%struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %union.tree_node*, %struct.sequence_stack* }
|
|
%struct.varasm_status = type opaque
|
|
%struct.ix86_args = type { i32, i32, i32, i32, i32, i32, i32 }
|
|
%struct.initial_value_struct = type opaque
|
|
%struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
|
|
%struct.machine_function = type opaque
|
|
%struct.language_function = type opaque
|
|
%struct.lang_decl = type opaque
|
|
%struct.rtx_def = type { i32, [1 x %union.rtunion_def] }
|
|
%union.rtunion_def = type { i64 }
|
|
|
|
declare hidden fastcc %struct.temp_slot* @find_temp_slot_from_address(%struct.rtx_def* readonly)
|
|
|
|
; CHECK-LABEL: useLEA:
|
|
; DISABLE: pushq
|
|
;
|
|
; CHECK: testq %rdi, %rdi
|
|
; CHECK-NEXT: je [[CLEANUP:LBB[0-9_]+]]
|
|
;
|
|
; CHECK: movzwl (%rdi), [[BF_LOAD:%e[a-z]+]]
|
|
; CHECK-NEXT: cmpl $66, [[BF_LOAD]]
|
|
; CHECK-NEXT: jne [[CLEANUP]]
|
|
;
|
|
; CHECK: movq 8(%rdi), %rdi
|
|
; CHECK-NEXT: movzwl (%rdi), %e[[BF_LOAD2:[a-z]+]]
|
|
; CHECK-NEXT: leal -54(%r[[BF_LOAD2]]), [[TMP:%e[a-z]+]]
|
|
; CHECK-NEXT: cmpl $14, [[TMP]]
|
|
; CHECK-NEXT: ja [[LOR_LHS_FALSE:LBB[0-9_]+]]
|
|
;
|
|
; CHECK: movl $24599, [[TMP2:%e[a-z]+]]
|
|
; CHECK-NEXT: btl [[TMP]], [[TMP2]]
|
|
; CHECK-NEXT: jb [[CLEANUP]]
|
|
;
|
|
; CHECK: [[LOR_LHS_FALSE]]: ## %lor.lhs.false
|
|
; CHECK: cmpl $134, %e[[BF_LOAD2]]
|
|
; CHECK-NEXT: je [[CLEANUP]]
|
|
;
|
|
; CHECK: cmpl $140, %e[[BF_LOAD2]]
|
|
; CHECK-NEXT: je [[CLEANUP]]
|
|
;
|
|
; ENABLE: pushq
|
|
; CHECK: callq _find_temp_slot_from_address
|
|
; CHECK-NEXT: testq %rax, %rax
|
|
;
|
|
; The adjustment must use LEA here (or be moved above the test).
|
|
; ENABLE-NEXT: leaq 8(%rsp), %rsp
|
|
;
|
|
; CHECK-NEXT: je [[CLEANUP]]
|
|
;
|
|
; CHECK: movb $1, 57(%rax)
|
|
;
|
|
; CHECK: [[CLEANUP]]: ## %cleanup
|
|
; DISABLE: popq
|
|
; CHECK-NEXT: retq
|
|
define void @useLEA(%struct.rtx_def* readonly %x) {
|
|
entry:
|
|
%cmp = icmp eq %struct.rtx_def* %x, null
|
|
br i1 %cmp, label %cleanup, label %if.end
|
|
|
|
if.end: ; preds = %entry
|
|
%tmp = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %x, i64 0, i32 0
|
|
%bf.load = load i32, i32* %tmp, align 8
|
|
%bf.clear = and i32 %bf.load, 65535
|
|
%cmp1 = icmp eq i32 %bf.clear, 66
|
|
br i1 %cmp1, label %lor.lhs.false, label %cleanup
|
|
|
|
lor.lhs.false: ; preds = %if.end
|
|
%arrayidx = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %x, i64 0, i32 1, i64 0
|
|
%rtx = bitcast %union.rtunion_def* %arrayidx to %struct.rtx_def**
|
|
%tmp1 = load %struct.rtx_def*, %struct.rtx_def** %rtx, align 8
|
|
%tmp2 = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %tmp1, i64 0, i32 0
|
|
%bf.load2 = load i32, i32* %tmp2, align 8
|
|
%bf.clear3 = and i32 %bf.load2, 65535
|
|
switch i32 %bf.clear3, label %if.end.55 [
|
|
i32 67, label %cleanup
|
|
i32 68, label %cleanup
|
|
i32 54, label %cleanup
|
|
i32 55, label %cleanup
|
|
i32 58, label %cleanup
|
|
i32 134, label %cleanup
|
|
i32 56, label %cleanup
|
|
i32 140, label %cleanup
|
|
]
|
|
|
|
if.end.55: ; preds = %lor.lhs.false
|
|
%call = tail call fastcc %struct.temp_slot* @find_temp_slot_from_address(%struct.rtx_def* %tmp1) #2
|
|
%cmp59 = icmp eq %struct.temp_slot* %call, null
|
|
br i1 %cmp59, label %cleanup, label %if.then.60
|
|
|
|
if.then.60: ; preds = %if.end.55
|
|
%addr_taken = getelementptr inbounds %struct.temp_slot, %struct.temp_slot* %call, i64 0, i32 8
|
|
store i8 1, i8* %addr_taken, align 1
|
|
br label %cleanup
|
|
|
|
cleanup: ; preds = %if.then.60, %if.end.55, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %lor.lhs.false, %if.end, %entry
|
|
ret void
|
|
}
|