forked from OSchip/llvm-project
61 lines
1.8 KiB
YAML
61 lines
1.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+bmi -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Test that rules where multiple operands must be the same operand successfully
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# match. Also test that the rules do not match when they're not the same
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# operand.
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---
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name: test_blsr32rr
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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# G_ADD and G_AND both use %0 so we should match this.
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body: |
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bb.1:
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liveins: %edi
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; CHECK-LABEL: name: test_blsr32rr
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
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; CHECK: [[BLSR32rr:%[0-9]+]]:gr32 = BLSR32rr [[COPY]], implicit-def %eflags
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; CHECK: %edi = COPY [[BLSR32rr]]
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%0(s32) = COPY %edi
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%1(s32) = G_CONSTANT i32 -1
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%2(s32) = G_ADD %0, %1
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%3(s32) = G_AND %2, %0
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%edi = COPY %3
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...
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---
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name: test_blsr32rr_nomatch
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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# G_ADD and G_AND use different operands so we shouldn't match this.
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body: |
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bb.1:
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liveins: %edi
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; CHECK-LABEL: name: test_blsr32rr_nomatch
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
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; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 4294967295
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; CHECK: [[DEC32r:%[0-9]+]]:gr32 = DEC32r [[MOV32ri]], implicit-def %eflags
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; CHECK: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[DEC32r]], [[COPY]], implicit-def %eflags
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; CHECK: %edi = COPY [[AND32rr]]
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%0(s32) = COPY %edi
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%1(s32) = G_CONSTANT i32 -1
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%2(s32) = G_ADD %1, %1
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%3(s32) = G_AND %2, %0
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%edi = COPY %3
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...
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