forked from OSchip/llvm-project
155 lines
3.7 KiB
YAML
155 lines
3.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
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--- |
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define i1 @test_or_i1() {
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%ret = or i1 undef, undef
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ret i1 %ret
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}
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define i8 @test_or_i8() {
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%ret = or i8 undef, undef
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ret i8 %ret
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}
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define i16 @test_or_i16() {
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%ret = or i16 undef, undef
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ret i16 %ret
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}
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define i32 @test_or_i32() {
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%ret = or i32 undef, undef
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ret i32 %ret
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}
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define i64 @test_or_i64() {
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%ret = or i64 undef, undef
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ret i64 %ret
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}
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...
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---
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name: test_or_i1
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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- { id: 2, class: _, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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; CHECK-LABEL: name: test_or_i1
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %edx
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; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
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; CHECK: [[OR:%[0-9]+]]:_(s8) = G_OR [[TRUNC]], [[TRUNC1]]
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; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[OR]](s8)
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; CHECK: RET 0
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%0(s32) = COPY %edx
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%1(s1) = G_TRUNC %0(s32)
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%2(s1) = G_OR %1, %1
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RET 0
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...
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---
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name: test_or_i8
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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constants:
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body: |
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bb.1 (%ir-block.0):
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; CHECK-LABEL: name: test_or_i8
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; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
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; CHECK: [[OR:%[0-9]+]]:_(s8) = G_OR [[DEF]], [[DEF]]
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; CHECK: %al = COPY [[OR]](s8)
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; CHECK: RET 0, implicit %al
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%0(s8) = IMPLICIT_DEF
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%1(s8) = G_OR %0, %0
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%al = COPY %1(s8)
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RET 0, implicit %al
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...
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---
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name: test_or_i16
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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constants:
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body: |
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bb.1 (%ir-block.0):
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; CHECK-LABEL: name: test_or_i16
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; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
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; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[DEF]], [[DEF]]
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; CHECK: %ax = COPY [[OR]](s16)
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; CHECK: RET 0, implicit %ax
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%0(s16) = IMPLICIT_DEF
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%1(s16) = G_OR %0, %0
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%ax = COPY %1(s16)
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RET 0, implicit %ax
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...
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---
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name: test_or_i32
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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constants:
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body: |
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bb.1 (%ir-block.0):
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; CHECK-LABEL: name: test_or_i32
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; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
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; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[DEF]], [[DEF]]
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; CHECK: %eax = COPY [[OR]](s32)
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; CHECK: RET 0, implicit %eax
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%0(s32) = IMPLICIT_DEF
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%1(s32) = G_OR %0, %0
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%eax = COPY %1(s32)
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RET 0, implicit %eax
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...
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---
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name: test_or_i64
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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constants:
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body: |
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bb.1 (%ir-block.0):
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; CHECK-LABEL: name: test_or_i64
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; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
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; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF]]
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; CHECK: %rax = COPY [[OR]](s64)
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; CHECK: RET 0, implicit %rax
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%0(s64) = IMPLICIT_DEF
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%1(s64) = G_OR %0, %0
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%rax = COPY %1(s64)
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RET 0, implicit %rax
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...
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