forked from OSchip/llvm-project
448 lines
16 KiB
LLVM
448 lines
16 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
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; FIXME: Merge into imm.ll
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; GCN-LABEL: {{^}}store_inline_imm_neg_0.0_v2i16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80008000{{$}}
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @store_inline_imm_neg_0.0_v2i16(<2 x i16> addrspace(1)* %out) #0 {
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store <2 x i16> <i16 -32768, i16 -32768>, <2 x i16> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_0.0_v2f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @store_inline_imm_0.0_v2f16(<2 x half> addrspace(1)* %out) #0 {
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store <2 x half> <half 0.0, half 0.0>, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_imm_neg_0.0_v2f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80008000{{$}}
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @store_imm_neg_0.0_v2f16(<2 x half> addrspace(1)* %out) #0 {
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store <2 x half> <half -0.0, half -0.0>, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_0.5_v2f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x38003800{{$}}
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @store_inline_imm_0.5_v2f16(<2 x half> addrspace(1)* %out) #0 {
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store <2 x half> <half 0.5, half 0.5>, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_m_0.5_v2f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0xb800b800{{$}}
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @store_inline_imm_m_0.5_v2f16(<2 x half> addrspace(1)* %out) #0 {
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store <2 x half> <half -0.5, half -0.5>, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_1.0_v2f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3c003c00{{$}}
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @store_inline_imm_1.0_v2f16(<2 x half> addrspace(1)* %out) #0 {
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store <2 x half> <half 1.0, half 1.0>, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_m_1.0_v2f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0xbc00bc00{{$}}
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @store_inline_imm_m_1.0_v2f16(<2 x half> addrspace(1)* %out) #0 {
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store <2 x half> <half -1.0, half -1.0>, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_2.0_v2f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x40004000{{$}}
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @store_inline_imm_2.0_v2f16(<2 x half> addrspace(1)* %out) #0 {
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store <2 x half> <half 2.0, half 2.0>, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_m_2.0_v2f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0xc000c000{{$}}
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @store_inline_imm_m_2.0_v2f16(<2 x half> addrspace(1)* %out) #0 {
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store <2 x half> <half -2.0, half -2.0>, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_4.0_v2f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x44004400{{$}}
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @store_inline_imm_4.0_v2f16(<2 x half> addrspace(1)* %out) #0 {
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store <2 x half> <half 4.0, half 4.0>, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_m_4.0_v2f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0xc400c400{{$}}
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @store_inline_imm_m_4.0_v2f16(<2 x half> addrspace(1)* %out) #0 {
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store <2 x half> <half -4.0, half -4.0>, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_inv_2pi_v2f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x31183118{{$}}
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @store_inline_imm_inv_2pi_v2f16(<2 x half> addrspace(1)* %out) #0 {
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store <2 x half> <half 0xH3118, half 0xH3118>, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_inline_imm_m_inv_2pi_v2f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0xb118b118{{$}}
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @store_inline_imm_m_inv_2pi_v2f16(<2 x half> addrspace(1)* %out) #0 {
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store <2 x half> <half 0xHB118, half 0xHB118>, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}store_literal_imm_v2f16:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x6c006c00
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @store_literal_imm_v2f16(<2 x half> addrspace(1)* %out) #0 {
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store <2 x half> <half 4096.0, half 4096.0>, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_0.0_v2f16:
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; GFX9: s_load_dword [[VAL:s[0-9]+]]
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; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 0{{$}}
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; GFX9: buffer_store_dword [[REG]]
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; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
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; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 0, [[VAL0]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 0, [[VAL1]]
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; VI: v_or_b32
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; VI: buffer_store_dword
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define amdgpu_kernel void @add_inline_imm_0.0_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
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%y = fadd <2 x half> %x, <half 0.0, half 0.0>
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store <2 x half> %y, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_0.5_v2f16:
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; GFX9: s_load_dword [[VAL:s[0-9]+]]
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; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 0.5{{$}}
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; GFX9: buffer_store_dword [[REG]]
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; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
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; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 0.5, [[VAL0]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 0.5, [[VAL1]]
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; VI: v_or_b32
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; VI: buffer_store_dword
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define amdgpu_kernel void @add_inline_imm_0.5_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
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%y = fadd <2 x half> %x, <half 0.5, half 0.5>
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store <2 x half> %y, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_neg_0.5_v2f16:
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; GFX9: s_load_dword [[VAL:s[0-9]+]]
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; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -0.5{{$}}
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; GFX9: buffer_store_dword [[REG]]
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; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
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; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -0.5, [[VAL0]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -0.5, [[VAL1]]
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; VI: v_or_b32
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; VI: buffer_store_dword
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define amdgpu_kernel void @add_inline_imm_neg_0.5_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
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%y = fadd <2 x half> %x, <half -0.5, half -0.5>
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store <2 x half> %y, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_1.0_v2f16:
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; GFX9: s_load_dword [[VAL:s[0-9]+]]
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; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 1.0{{$}}
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; GFX9: buffer_store_dword [[REG]]
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; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
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; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 1.0, [[VAL0]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 1.0, [[VAL1]]
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; VI: v_or_b32
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; VI: buffer_store_dword
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define amdgpu_kernel void @add_inline_imm_1.0_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
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%y = fadd <2 x half> %x, <half 1.0, half 1.0>
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store <2 x half> %y, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_neg_1.0_v2f16:
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; GFX9: s_load_dword [[VAL:s[0-9]+]]
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; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -1.0{{$}}
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; GFX9: buffer_store_dword [[REG]]
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; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
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; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -1.0, [[VAL0]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -1.0, [[VAL1]]
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; VI: v_or_b32
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; VI: buffer_store_dword
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define amdgpu_kernel void @add_inline_imm_neg_1.0_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
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%y = fadd <2 x half> %x, <half -1.0, half -1.0>
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store <2 x half> %y, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_2.0_v2f16:
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; GFX9: s_load_dword [[VAL:s[0-9]+]]
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; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 2.0{{$}}
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; GFX9: buffer_store_dword [[REG]]
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; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
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; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 2.0, [[VAL0]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 2.0, [[VAL1]]
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; VI: v_or_b32
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; VI: buffer_store_dword
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define amdgpu_kernel void @add_inline_imm_2.0_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
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%y = fadd <2 x half> %x, <half 2.0, half 2.0>
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store <2 x half> %y, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_neg_2.0_v2f16:
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; GFX9: s_load_dword [[VAL:s[0-9]+]]
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; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -2.0{{$}}
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; GFX9: buffer_store_dword [[REG]]
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; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
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; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -2.0, [[VAL0]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -2.0, [[VAL1]]
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; VI: v_or_b32
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; VI: buffer_store_dword
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define amdgpu_kernel void @add_inline_imm_neg_2.0_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
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%y = fadd <2 x half> %x, <half -2.0, half -2.0>
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store <2 x half> %y, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_4.0_v2f16:
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; GFX9: s_load_dword [[VAL:s[0-9]+]]
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; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 4.0{{$}}
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; GFX9: buffer_store_dword [[REG]]
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; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
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; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 4.0, [[VAL0]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 4.0, [[VAL1]]
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; VI: v_or_b32
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; VI: buffer_store_dword
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define amdgpu_kernel void @add_inline_imm_4.0_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
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%y = fadd <2 x half> %x, <half 4.0, half 4.0>
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store <2 x half> %y, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_neg_4.0_v2f16:
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; GFX9: s_load_dword [[VAL:s[0-9]+]]
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; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -4.0{{$}}
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; GFX9: buffer_store_dword [[REG]]
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; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
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; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -4.0, [[VAL0]]
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -4.0, [[VAL1]]
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; VI: v_or_b32
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; VI: buffer_store_dword
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define amdgpu_kernel void @add_inline_imm_neg_4.0_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
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%y = fadd <2 x half> %x, <half -4.0, half -4.0>
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store <2 x half> %y, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}commute_add_inline_imm_0.5_v2f16:
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; GFX9: buffer_load_dword [[VAL:v[0-9]+]]
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; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 0.5
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; GFX9: buffer_store_dword [[REG]]
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; VI: buffer_load_dword
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; VI-NOT: and
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; VI: v_lshrrev_b32_e32 {{v[0-9]+}}, 16,
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 0.5, v{{[0-9]+}}
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 0.5, v{{[0-9]+}}
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; VI: v_or_b32
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; VI: buffer_store_dword
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define amdgpu_kernel void @commute_add_inline_imm_0.5_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
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%x = load <2 x half>, <2 x half> addrspace(1)* %in
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%y = fadd <2 x half> %x, <half 0.5, half 0.5>
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store <2 x half> %y, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}commute_add_literal_v2f16:
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; GFX9: buffer_load_dword [[VAL:v[0-9]+]]
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; GFX9: s_mov_b32 [[K:s[0-9]+]], 0x64006400
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; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[K]], [[VAL]]
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; GFX9: buffer_store_dword [[REG]]
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; VI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x6400{{$}}
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; VI-DAG: buffer_load_dword
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; VI-NOT: and
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; VI: v_lshrrev_b32_e32 {{v[0-9]+}}, 16,
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, [[K]], v{{[0-9]+}}
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; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, [[K]], v{{[0-9]+}}
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; VI: v_or_b32
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; VI: buffer_store_dword
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define amdgpu_kernel void @commute_add_literal_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
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%x = load <2 x half>, <2 x half> addrspace(1)* %in
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%y = fadd <2 x half> %x, <half 1024.0, half 1024.0>
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store <2 x half> %y, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}add_inline_imm_1_v2f16:
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; GFX9: s_load_dword [[VAL:s[0-9]+]]
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; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 1{{$}}
|
|
; GFX9: buffer_store_dword [[REG]]
|
|
|
|
; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
|
|
; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
|
|
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 1, [[VAL0]]
|
|
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 1, [[VAL1]]
|
|
; VI: v_or_b32
|
|
; VI: buffer_store_dword
|
|
define amdgpu_kernel void @add_inline_imm_1_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
|
|
%y = fadd <2 x half> %x, <half 0xH0001, half 0xH0001>
|
|
store <2 x half> %y, <2 x half> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_2_v2f16:
|
|
; GFX9: s_load_dword [[VAL:s[0-9]+]]
|
|
; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 2{{$}}
|
|
; GFX9: buffer_store_dword [[REG]]
|
|
|
|
; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
|
|
; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
|
|
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 2, [[VAL0]]
|
|
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 2, [[VAL1]]
|
|
; VI: v_or_b32
|
|
; VI: buffer_store_dword
|
|
define amdgpu_kernel void @add_inline_imm_2_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
|
|
%y = fadd <2 x half> %x, <half 0xH0002, half 0xH0002>
|
|
store <2 x half> %y, <2 x half> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_16_v2f16:
|
|
; GFX9: s_load_dword [[VAL:s[0-9]+]]
|
|
; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 16{{$}}
|
|
; GFX9: buffer_store_dword [[REG]]
|
|
|
|
; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
|
|
; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
|
|
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 16, [[VAL0]]
|
|
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 16, [[VAL1]]
|
|
; VI: v_or_b32
|
|
; VI: buffer_store_dword
|
|
define amdgpu_kernel void @add_inline_imm_16_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
|
|
%y = fadd <2 x half> %x, <half 0xH0010, half 0xH0010>
|
|
store <2 x half> %y, <2 x half> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_neg_1_v2f16:
|
|
; GFX9: s_load_dword [[VAL:s[0-9]+]]
|
|
; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -1{{$}}
|
|
; GFX9: buffer_store_dword [[REG]]
|
|
|
|
; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
|
|
; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
|
|
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -1, [[VAL0]]
|
|
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -1, [[VAL1]]
|
|
; VI: v_or_b32
|
|
; VI: buffer_store_dword
|
|
define amdgpu_kernel void @add_inline_imm_neg_1_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
|
|
%y = fadd <2 x half> %x, <half 0xHFFFF, half 0xHFFFF>
|
|
store <2 x half> %y, <2 x half> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_neg_2_v2f16:
|
|
; GFX9: s_load_dword [[VAL:s[0-9]+]]
|
|
; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -2{{$}}
|
|
; GFX9: buffer_store_dword [[REG]]
|
|
|
|
; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
|
|
; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
|
|
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -2, [[VAL0]]
|
|
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -2, [[VAL1]]
|
|
; VI: v_or_b32
|
|
; VI: buffer_store_dword
|
|
define amdgpu_kernel void @add_inline_imm_neg_2_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
|
|
%y = fadd <2 x half> %x, <half 0xHFFFE, half 0xHFFFE>
|
|
store <2 x half> %y, <2 x half> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_neg_16_v2f16:
|
|
; GFX9: s_load_dword [[VAL:s[0-9]+]]
|
|
; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -16{{$}}
|
|
; GFX9: buffer_store_dword [[REG]]
|
|
|
|
; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
|
|
; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
|
|
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -16, [[VAL0]]
|
|
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -16, [[VAL1]]
|
|
; VI: v_or_b32
|
|
; VI: buffer_store_dword
|
|
define amdgpu_kernel void @add_inline_imm_neg_16_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
|
|
%y = fadd <2 x half> %x, <half 0xHFFF0, half 0xHFFF0>
|
|
store <2 x half> %y, <2 x half> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_63_v2f16:
|
|
; GFX9: s_load_dword [[VAL:s[0-9]+]]
|
|
; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 63
|
|
; GFX9: buffer_store_dword [[REG]]
|
|
|
|
; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
|
|
; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
|
|
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 63, [[VAL0]]
|
|
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 63, [[VAL1]]
|
|
; VI: v_or_b32
|
|
; VI: buffer_store_dword
|
|
define amdgpu_kernel void @add_inline_imm_63_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
|
|
%y = fadd <2 x half> %x, <half 0xH003F, half 0xH003F>
|
|
store <2 x half> %y, <2 x half> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_64_v2f16:
|
|
; GFX9: s_load_dword [[VAL:s[0-9]+]]
|
|
; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 64
|
|
; GFX9: buffer_store_dword [[REG]]
|
|
|
|
; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
|
|
; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
|
|
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 64, [[VAL0]]
|
|
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 64, [[VAL1]]
|
|
; VI: v_or_b32
|
|
; VI: buffer_store_dword
|
|
define amdgpu_kernel void @add_inline_imm_64_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 {
|
|
%y = fadd <2 x half> %x, <half 0xH0040, half 0xH0040>
|
|
store <2 x half> %y, <2 x half> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { nounwind }
|