forked from OSchip/llvm-project
23 lines
1.0 KiB
LLVM
23 lines
1.0 KiB
LLVM
; RUN: llc -march=amdgcn -enable-no-signed-zeros-fp-math=0 < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-SAFE %s
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; RUN: llc -march=amdgcn -enable-no-signed-zeros-fp-math=1 < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-UNSAFE %s
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; RUN: llc -march=amdgcn -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-UNSAFE %s
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; Test that the -enable-no-signed-zeros-fp-math flag works
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; GCN-LABEL: {{^}}fneg_fsub_f32:
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; GCN: v_subrev_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}
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; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[SUB]]
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; GCN-UNSAFE-NOT: xor
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define amdgpu_kernel void @fneg_fsub_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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%b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
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%a = load float, float addrspace(1)* %in, align 4
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%b = load float, float addrspace(1)* %b_ptr, align 4
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%result = fsub float %a, %b
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%neg.result = fsub float -0.0, %result
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store float %neg.result, float addrspace(1)* %out, align 4
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ret void
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}
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attributes #0 = { nounwind }
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