forked from OSchip/llvm-project
60 lines
2.1 KiB
LLVM
60 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+xop | FileCheck %s --check-prefix=XOP
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefix=AVX512
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; fold (rot (rot x, c1), c2) -> rot x, c1+c2
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define <4 x i32> @combine_vec_rot_rot(<4 x i32> %x) {
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; XOP-LABEL: combine_vec_rot_rot:
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; XOP: # %bb.0:
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; XOP-NEXT: vprotd {{.*}}(%rip), %xmm0, %xmm0
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; XOP-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_rot_rot:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vprolvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX512-NEXT: retq
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%1 = lshr <4 x i32> %x, <i32 1, i32 2, i32 3, i32 4>
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%2 = shl <4 x i32> %x, <i32 31, i32 30, i32 29, i32 28>
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%3 = or <4 x i32> %1, %2
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%4 = lshr <4 x i32> %3, <i32 12, i32 13, i32 14, i32 15>
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%5 = shl <4 x i32> %3, <i32 20, i32 19, i32 18, i32 17>
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%6 = or <4 x i32> %4, %5
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ret <4 x i32> %6
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}
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define <4 x i32> @combine_vec_rot_rot_splat(<4 x i32> %x) {
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; XOP-LABEL: combine_vec_rot_rot_splat:
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; XOP: # %bb.0:
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; XOP-NEXT: vprotd $7, %xmm0, %xmm0
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; XOP-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_rot_rot_splat:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vprold $7, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%1 = lshr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
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%2 = shl <4 x i32> %x, <i32 29, i32 29, i32 29, i32 29>
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%3 = or <4 x i32> %1, %2
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%4 = lshr <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22>
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%5 = shl <4 x i32> %3, <i32 10, i32 10, i32 10, i32 10>
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%6 = or <4 x i32> %4, %5
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ret <4 x i32> %6
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}
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define <4 x i32> @combine_vec_rot_rot_splat_zero(<4 x i32> %x) {
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; XOP-LABEL: combine_vec_rot_rot_splat_zero:
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; XOP: # %bb.0:
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; XOP-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_rot_rot_splat_zero:
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; AVX512: # %bb.0:
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; AVX512-NEXT: retq
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%1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
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%2 = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
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%3 = or <4 x i32> %1, %2
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%4 = lshr <4 x i32> %3, <i32 31, i32 31, i32 31, i32 31>
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%5 = shl <4 x i32> %3, <i32 1, i32 1, i32 1, i32 1>
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%6 = or <4 x i32> %4, %5
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ret <4 x i32> %6
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}
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